IMPORTANT: SBC5206 development system uses different memory mapping wh

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IMPORTANT: SBC5206 development system uses different memory mapping wh

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MCF5206 COLDFIRE Assembly Header, Sample Initialization File Test Code Developed John Cunningham Motorola Imaging Storage Systems Division Austin, beta (6/27/97) This file contains following information designers using MCF5206: 1)Assembly header listing (i.e. EQUATES memory map) 2)Module initialization code (SIM,UART, TIMER etc.) 3)Sample test code TIMER UART 4)Batch file assembling with DIAB DATA assembler 5)Initialization file MCF5206 development system 6)DIAB DATA linker file **************** Introduction This file provides examples initializing configuring various modules COLDFIRE 5206 processor. explanation module configured shown prior actual code. best viewed using WORDPAD NOTEPAD Microsoft. This code written were specific design. specifications that design are: 1)Code space less than (only address lines 0:23 used) 2)Dram size Meg, bank utilized 3)Upper addresses used chip selects 4)Both UARTS used interrupts 5)MBUS port (I2C) used, (interrupts disabled) 5)Parallel port used 6)Timers used (interrupts disabled) 8)SRAM used. Stack pointer SRAM 9)Cache disabled
IMPORTANT: SBC5206 development system uses different memory mapping when compared this initialization example code. evaluation board* boots FLASH sets code space DRAM. lines that have been commented enable this code work* SBC5206 development system ALSO: Make sure least power supply with development system. 800ma wall-pack power supply been known have enough current when running UARTs. 5206 development system sets these registers following values: RAMBAR $20000000 MBAR $10000000 CACR $00000000 ACR0 $FFFF60E4 ACR1 $FFFF60E4 VBAR $00000000 This code been tested SBC5206 eval system with DRAM, CHIP SELECTS, register commented ";". This code gives designer idea initialize test many modules registers 5206. This code used, embedded application, where code DRAM, CHIP SELECTS, configured shown this example. user just needs uncomment lines.
Unfortunately, this code only been tested with 5206 development system written now. responsibility user verify that this example code works their design (i.e. with specific lines uncommented such CACHE DRAM initialization code). ************** Memory ************** memory this example follows. Note: This example assumed 29F040 flash memory size which Mbit 524,288 bytes entire code space used. Remember, this differs using SBC5206 development system. $00000000 usable code space $000F0000 $00700000 table DRAM space meg) $00AFFFFF $00B00000 unused $20000000
SRAM space (512 bytes)
-unused
$FFEFFFFF -$FFF003FD -unused -$FFFF0200 -unused -$FFFFF000 -Module base (496 bytes) $FFFF01F0
************************ DIAB DATA batch file following lines lines used compile this code. This batch file assumes following: DIAB DATA compiler located drive assembly file named 5206jc.s located directory c:\5206\test Create directory "C:\5206\test. Create file called 5206.bat with command lines listed below copy into C:\5206\test directory.(Make sure remove comments.) c:\diab\3.7a\win32\bin\das c:\5206\test\5206jc.o
-WDDTARGET=MCF5200-WDDOBJECT=F c:\5206\test\5206jc.s c:\diab\3.7a\win32\bin\dldnew -YS,. -YP,c:\diab\3.7a\ace0fs c:\5206\test\5206jc.elf c:\5206\test\5206jc.o ace_diab.lnk c:\diab\3.7a\win32\bin\ddump c:\5206\test\5206jc.hex c:\5206\test\5206jc.elf *********************** DIAB DATA link file addition batch file assembly file, DIAB DATA uses link file. this design, copy lines listed below into C:\5206\test directory name file "Ace_diab.lnk". More information about DIAB DATA linker found COLDFIRE that came with SBC5206 development system promo boards. This contains manual format. manual provides examples define change attributes associated with linker. MEMORY 0x10000,len 0x100000 SECTIONS .text: >ram .data: >ram .bss: >ram _HEAP_START ADDR(.bss)+SIZEOF(.bss); _SP_INIT ADDR(ram)+SIZEOF(ram); STKTOP _SP_INIT; _HEAP_END _SP_INIT-0x800; _SP_END _HEAP_END; _DATA_ROM ADDR(.text)+SIZEOF(.text); _DATA_RAM ADDR(.data); _DATA_END ADDR(.data)+SIZEOF(.data); _BSS_START ADDR(.bss); _BSS_END ADDR(.bss)+SIZEOF(.bss); _HEAP_START _HEAP_START; _SP_INIT _SP_INIT; _HEAP_END _HEAP_END; _SP_END _SP_END; _DATA_ROM _DATA_ROM; _DATA_RAM _DATA_RAM; _DATA_END _DATA_END;
_BSS_START _BSS_START; _BSS_END _BSS_END; EQUATES SECTION MBAR (Module Base Address Register)defines base address internal peripheral registers. accessed space $C0F MOVEC instruction. COLDFIRE 5206 User manual, 7-1. example setting MBAR location $10000000 would move.l #$10000000,D0 movec D0,MBAR assembler/compiler knows store system control register MBAR "MBAR" does have defined statement Make sure type "MBAR" (Not case sensitive). other registers offsets MBAR. created variable* called MBARx used "EQU" statement define value. Make sure give MBARx value same value stored MBAR. Example MBARx $10000000 MBARx value defined provide valid addresses rest memory map. MBARx that commented below this design example. commented enable this code SBC5206 development system. using this code example without development system, comment line that sets MBARx $10000000 uncomment line that sets $FFFFF000.
also commented SBC5206 development system. properly VBR, should stored external SRAM/RAM location. suggest uing first $3FF your vector tables. Therefore, this code this design example comment line that sets VBRx $00000000 line that sets $00700000 which beginning DRAM. RAMBARx same SBC5206 development system. Registers Memory NOTE: registers must accessed through MOVEC instruction Registers that "MOVEC" command are: 1)MBR 2)VBR 3)CACR 4)ACR0 5)ACR1 6)RAMBAR assembler/compiler recognizes above listed names have defined statement. example below will store correct value MBAR. This also true VBR, CACR, ACR0, ACR1, RAMBAR Example: move.l #value,D0 ;Load data register with value movec D0,MBAR ;Place value into register Register Location internal CACR $00000002 Cache Control Register, 32-bit, ACR0 $00000000 Access Control Register 32-bit, ACR1 $00000000 Access Control Register 32-bit, $00000801 Vector Base Register, 32-bit, RAMBAR $00000C04 SRAM Base Address Register, 32-bit, ;MBARx $FFFFF000 ;Module Base Address value ;($FFFFF000 $FFFFF1F0)(496 bytes) MBARx $10000000 ;Module Base Address value ;($10000000 $100001F0)(496 bytes) should somewhere SRAM. 5206 development system comes with where executes program code. 5206 development system begins executing code
address $00010000 sets location $00000000. entire vector table uses 1024 bytes (Interrupts 0-255, bytes each). This example initialization sets DRAM1 bank $00700000. Therefore, using 5206 development system, user should change VBRx statement below from $00000000 $00700000 beginning RAM. VBRx $00000000 ;Vector Base Address ($000-3FC) ;1020 bytes. register "A7" load it's value RAMBARx DRAM0x $20000000 $0070 ;SRAM Base Address (512 bytes) ;and address masks 5-2,3) ;base address DRAM0, $00700000
System Integration Module SIMR MBARx+$0003 ;SIM Configuration Register, 8-bit, **************** register **************** MBARx+$00CB ;Pin Assignment Register, 8-bit, ******************************* Interrupt EQUs ******************************* ICR1 MBARx+$0014 ;Interrupt Control Register Ext1, 8-bit, ICR2 MBARx+$0015 ;Interrupt Control Register Ext2, 8-bit, ICR3 MBARx+$0016 ;Interrupt Control Register Ext3, 8-bit, ICR4 MBARx+$0017 ;Interrupt Control Register Ext4, 8-bit, ICR5 MBARx+$0018 ;Interrupt Control Register Ext5, 8-bit, ICR6 MBARx+$0019 ;Interrupt Control Register Ext6, 8-bit, ICR7 MBARx+$001A ;Interrupt Control Register Ext7, 8-bit, ICR8 MBARx+$001B ;Interrupt Control Register SWT, 8-bit, ICR9 MBARx+$001C ;Interrupt Control Register TIMER1, 8-bit, ICR10 MBARx+$001D ;Interrupt Control Register TIMER2, 8-bit, ICR11 MBARx+$001E ;Interrupt Control Register MBUS, 8-bit, ICR12 MBARx+$001F ;Interrupt Control Register UART1, 8-bit, ICR13 MBARx+$0020 ;Interrupt Control Register UART2, 8-bit, MBARx+$0036 ;Interrupt Mask Register, 32-bit, MBARx+$003A ;Interrupt Pending Register, 32-bit, MBARx+$0040 ;Reset Status Register, 8-bit, ******************************* Software Watchdog EQUs ******************************* SYPCR MBARx+$0041 ;System Protection Control Register, 8-bit, SWIVR MBARx+$0042 ;Software Watchdog Interrupt Vector Register, 8-bit,
SWSR
MBARx+$0043 ;Software Watchdog Service Register, ;8-bit,
DRAM Controller Registers This section defines DRAM controller, 10-3 5206 users manual DCRR MBARx+$0046 ;DRAM Refresh Register, 16-bit, DCTR MBARx+$004A ;DRAM Timing Register, 16-bit, DCAR0 MBARx+$004C ;DRAM Bank Address Register, 16-bit, DCMR0 MBARx+$0050 ;DRAM Bank Mask Register, 32-bit, DCCR0 MBARx+$0057 ;DRAM Bank Control Register, 8-bit, DCAR1 MBARx+$0058 ;DRAM Bank Address Register, 16-bit, DCMR1 MBARx+$005C ;DRAM Bank Mask Register, 32-bit, DCCR1 MBARx+$0063 ;DRAM Bank Control Register, 8-bit, Chip Select Registers This section defines Chip Selects 5206 Processor information this section found Users manual. CSAR0 CSMR0 CSCR0 CSAR1 CSMR1 CSCR1 CSAR2 CSMR2 CSCR2 CSAR3 CSMR3 CSCR3 CSAR4 CSMR4 CSCR4 CSAR5 CSMR5 CSCR5 CSAR6 CSMR6 CSCR6 CSAR7 CSMR7 CSCR7 DMCR MBARx+$0064 ;Chip-Select Base Address Register, 16-bit, MBARx+$0068 ;Chip-Select Address Mask Register, 32-bit, MBARx+$006E ;Chip-Select Control Register, 16-bit, MBARx+$0070 ;Chip-Select Base Address Register, 16-bit, MBARx+$0074 ;Chip-Select Address Mask Register, 32-bit, MBARx+$007A ;Chip-Select Control Register, 16-bit, MBARx+$007C ;Chip-Select Base Address Register, 16-bit, MBARx+$0080 ;Chip-Select Address Mask Register, 32-bit, MBARx+$0086 ;Chip-Select Control Register, 16-bit, MBARx+$0088 ;Chip-Select Base Address Register, 16-bit, MBARx+$008C ;Chip-Select Address Mask Register, 32-bit, MBARx+$0092 ;Chip-Select Control Register, 16-bit, MBARx+$0094 ;Chip-Select Base Address Register, 16-bit, MBARx+$0098 ;Chip-Select Address Mask Register, 32-bit, MBARx+$009E ;Chip-Select Control Register, 16-bit, MBARx+$00A0 ;Chip-Select Base Address Register, 16-bit, MBARx+$00A4 ;Chip-Select Address Mask Register, 32-bit, MBARx+$00AA ;Chip-Select Control Register, 16-bit, MBARx+$00AC ;Chip-Select Base Address Register, 16-bit, MBARx+$00B0 ;Chip-Select Address Mask Register, 32-bit, MBARx+$00B6 ;Chip-Select Control Register, 16-bit, MBARx+$00B8 ;Chip-Select Base Address Register, 16-bit, MBARx+$00BC ;Chip-Select Address Mask Register, 32-bit, MBARx+$00C2 ;Chip-Select Control Register, 16-bit, MBARx+$00C6 ;Default Memory Control Register, 16-bit,
Timer Registers There timers MCF5206. With clock, maximum period seconds resolution 30ns. 13-1 users manual *********** Timer *********** TMR1 TRR1 TCR1 TCN1 TER1 *********** Timer *********** TMR2 TRR2 TCR2 TCN2 TER2 MBARx+$0120 ;TIMER2 Mode Register, 16-bit, MBARx+$0124 ;TIMER2 Mode Register, 16-bit, MBARx+$0128 ;TIMER2 Capture Register, 16-bit, MBARx+$012C ;TIMER2 Counter, 16-bit, MBARx+$0131 ;TIMER2 Event Register, 8-bit,
MBARx+$0100 ;TIMER1 Mode Register, 16-bit, MBARx+$0104 ;TIMER1 TIMER1 Mode Register, 16-bit, MBARx+$0108 ;TIMER1 Capture Register, 16-bit, MBARx+$010C ;TIMER1 Counter, 16-bit, MBARx+$0111 ;TIMER1 Event Register, 8-bit,
UART Module Registers MCF5206 contains universal asynchronous/synchronous receiver/transmitters (UARTS) that independently. 11-1 users manual. Note that some registers defined with same address location, such USCR. because register valid READ other valid when WRITE. 11-17, table 11-1 details 5206 user's manual. ********* UART1 ********* UMR11 UMR21 USR1 UCSR1 UCR1 URB1 UTB1 UIPCR1 UACR1 UISR1 UIMR1 MBARx+$0140 ;UART1 UMR1 Mode Register, 8-bit, MBARx+$0140 ;UART1 UMR2 Mode Register, 8-bit, MBARx+$0144 ;UART1 Status Register, 8-bit, MBARx+$0144 ;UART1 Clock Select Register, 8-bit, MBARx+$0148 ;UART1 Command Register, 8-bit, MBARx+$014C ;UART1 Receiver Buffer, 8-bit, MBARx+$014C ;UART1 Transmitter Buffer, 8-bit, MBARx+$0150 ;UART1 Input Port Change Register, 8-bit, MBARx+$0150 ;UART1 Auxiliary Control Register, 8-bit, MBARx+$0154 ;UART1 Interrupt Status Register, 8-bit, MBARx+$0154 ;UART1 Interrupt Mask Register, 8-bit,
UBG11 MBARx+$0158 ;UART1 Baud Rate Generator PreScale MSB, 8-bit, UBG21 MBARx+$015C ;UART1 Baud Rate Generator PreScale LSB, 8-bit, UIVR1 MBARx+$0170 ;UART1 Interrupt Vector Register, 8-bit, UIP1 MBARx+$0174 ;UART1 Input Port Register, 8-bit, UOP11 MBARx+$0178 ;UART1 Output Port Command, 8-bit, UOP01 MBARx+$017C ;UART1 Output Port Reset Command, 8-bit, ********* UART2 ********* UMR12 UMR22 USR2 UCSR2 UCR2 URB2 UTB2 UIPCR2 UACR2 UISR2 UIMR2 UBG12 UBG22 UIVR2 UIP2 UOP12 UOP02 MBARx+$0180 ;UART2 UMR1 Mode Register, 8-bit, MBARx+$0180 ;UART2 UMR1 Mode Register, 8-bit, MBARx+$0184 ;UART2 Status Register, 8-bit, MBARx+$0184 ;UART2 Clock Select Register, 8-bit, MBARx+$0188 ;UART2 Command Register, 8-bit, MBARx+$018C ;UART2 Receiver Buffer, 8-bit, MBARx+$018C ;UART2 Transmitter Buffer, 8-bit, MBARx+$0190 ;UART2 Input Port Change Register, 8-bit, MBARx+$0190 ;UART2 Auxiliary Control Register, 8-bit, MBARx+$0194 ;UART2 Interrupt Status Register, 8-bit, MBARx+$0194 ;UART2 Interrupt Mask Register, 8-bit, MBARx+$0198 ;UART1 Baud Rate Generator PreScale MSB, 8-bit, MBARx+$019C ;UART2 Baud Rate Generator PreScale LSB, 8-bit, MBARx+$01B0 ;UART2 Interrupt Vector Register, 8-bit, MBARx+$01B4 ;UART2 Input Port Register, 8-bit, MBARx+$01B8 ;UART2 Output Port Command, 8-bit, MBARx+$01BC ;UART2 Output Port Reset Command, 8-bit,
General Purpose These registers define 8-bit port. 8-bit port muxed with internal processor status pins "PST[3.0]" "DDATA[3.0]" debug pins. defines what function these pins have (i.e Debug parallel port). 7-16/17 port direction logic level. PADDR PADAT MBARx+$01C5 ;Port Data Direction Register, ;8-bit, MBARx+$01C9 ;Port Data Register, 8-bit,
M-BUS Registers M-bus high speed, wire, serial that provides* bidirectional serial transmission between on-board devices
compatible with Phillips standard. 12-1 5206 user's manual MADR MFDR MBCR MBSR MBDR MBARx+$01E0 MBARx+$01E4 MBARx+$01E8 MBARx+$01EC MBARx+$01F0 ;M-BUS Address Register, 8-bit, ;M-BUS Frequency Divider Register, 8-bit, ;M-BUS Control Register, 8-bit, ;M-BUS Status Register, 8-bit, ;M-BUS Data Register, 8-bit,
********************** Finish section ********************** ******************************* Interrupt vector table* This table defines where program will when interrupt occurs. Since these values loaded offset VBR, label header "VBARx" used define location. This created section. change value VBAR make sure same value VBARx section example, UART1 configuration defined UIVR interrupt register have interrupt vector ($100 hex) interrupt UART1 enabled interrupt occured,* processor would load program counter with value found interrupt vector number Since loaded that place with "UART1_INT", program will jump label UART1_INT. simple example code below shows create interrupt handling subroutine that just returns from exception UART1_INT Although there 64-255 possible "user defined interrupt vectors", only listed 64-100 below. Also, those have left them $FFFFFFFF. user this code should insert proper value these interrupt vectors V_TABLE DC.L $FFFFFFFF (Initial stack Pointer) DC.L $FFFFFFFF (Initial program counter) DC.L $FFFFFFFF (Access Error)
DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L
$FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF TIMER1_INT TIMER2_INT MBUS_INT $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF
(Address error) (Illegal Instruction) (reserved) (reserved) (reserved) (Privilege violation) (Trace) ;10(Unimplemented line-a code) (Unimplemented line-f code) (Debug Interrupt) (reserved) (Format error) (Uninitialized interrupt) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (Spurious interrupt) (Autovector (Autovector (Autovector (Autovector (Autovector (Autovector (Autovector (Trap (Trap (Trap (Trap (Trap (Trap (Trap (Trap (Trap (Trap (Trap (Trap (Trap (Trap (Trap (Trap (reserved) (reserved)
DC.L $FFFFFFFF (reserved) DC.L $FFFFFFFF (reserved)
DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L DC.L
$FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF UART1_INT UART2_INT $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF WDOG_INT $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF $FFFFFFFF
(reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (user defined interrupt) (user defined interrupt) (user defined interrupt) (user defined interrupt) (user defined interrupt) (user defined interrupt) (user defined interrupt) (user defined interrupt) (user defined interrupt) (user defined interrupt) (user defined interrupt) (user defined interrupt) (user defined interrupt) (user defined interrupt) (user defined interrupt) (user defined interrupt) (user defined interrupt) (user defined interrupt) (user defined interrupt) (user defined interrupt) (user defined interrupt) (user defined interrupt) (user defined interrupt) (user defined interrupt) (user defined interrupt) (user defined interrupt) (user defined interrupt) (user defined interrupt) (user defined interrupt) (user defined interrupt) (user defined interrupt) (user defined interrupt) (user defined interrupt) (user defined interrupt) (user defined interrupt) (user defined interrupt) ;100 (user defined interrupt)
XDEF command DIAB DATA compiler lets source level debugger where begin runing code. XDEF _main _main move.w #$2000,D0 ;Reset Interrupts move.w D0,SR ;possible levels lines below commented SBC5206 development system. using this example without development system, uncomment them. (i.e remove begnning each line. IMPORTANT: Changes using 5206 evaluation board. using this code 5206 development system, uncomment code listed below. will overwrite configurations MBR, VBR, DCAR0, RAMBARx registers. eval board SBC5206 User's manual, Diab Data compiler/assembler configuration file that sets below listed registers. This mainly SBC5206 evaluation board. SBC5206 development system users manual Base Register From $00000000 $000003FF $10000000 $100003FF RAMBAR $20000000 $200001FF DCAR0 $00000000 $01FFFFFF Define base addresses MBAR, Initialize base modules. values were defined earlier section. code below defines where each MBAR located memory map. move.l #MBARx,D0 ;define init location movec D0,MBAR ;Vector Base register. ;7-7,8 users manual register needs used load correct value register. other register, only vector table called V_TABLE used store correct
values vector interrupts, 5206 user's manual move.l A7,A6 ;save stack pointer move.l #VBRx,A7 ;define init location movec A7,VBR ;Vector Base register ;defined earlier statements $2000000 move.l A6,A7 ;restore stack clr.l clr.l lea.l VBRx,A0 ;point VBRx location lea.l V_TABLE,A1 VT_INIT move.l (A1)+,(A0)+ ;point vector table addi.l #1,D0 cmp.l #100,D0 just counter VT_INIT ;100 possible interrupts ******** CACHE Initialization Section (Users manual) cache uses only registers configuration: CACR, ACR0, ACR1. CACR register controls operation cache. ACR0 ACR1 registers define what memory space cacheable.* This accomplished setting base mask bits 5206 users manual). registers define what memory space cacheable 4-10, "CM"). ***************** registers ***************** registers define what areas memory cacheable. Bits 31:24 define base address bits 23:16 mask address comparison bits. example, define space memory, $01FFFFFF $03FFFFFF, would following: Bits 31:24 (base address) Bits 23:16 (mask) above diagram show that base address starts $01xxxxxx* mask ignores lower bits only compares upper bits (31:26). Therefore, cacheable memory goes $03FFFFFF. also possible define same memory space listed above*
non-cacheable. This accomplished setting "CM" registers. users maximum registers use. cache follows (see 4-6,7,8): Cache enabled (bit CPUSHL enabled (bit Cache freeze normal operation (bit Cache invalidated (bit Burst fetches cacheable disabled (bit Default cache mode enabled (bit Buffered writes enabled (bit Both read write capability (bit line miss fetches (bits 1,0) move.l #91000323,D0 movec D0,CACR ;disable cache other ;functions demonstration ;see 4-6,7,8 users manual ;CACRx defined section ;which $80000321 ;cached memory from $01000000 $03FFFFFF. ignore modes,enable ;ACR0, buffered writes enable ;both read write. 4-9.10
move.l #$0103C020,D0 movec D0,ACR0
******** SRAM Initialization Section (Users manual) SRAM easily since only register initialize, RAMBAR. SRAM base register byte boundary 5-2). lower bits define what type data used accessed bits 31.9 define location base address. value RAMBARx defined earlier statements section. SRAM configured, users manual, follows: 1)Base address $20000000 (bits 31:9) 2)Allow read write capabilities (bit 3)CPU space, User, Supervisor code capable (bits 5:1) 4)Validate SRAM space. After loading SRAM with valid data, enable this bit. This good design practice when powering resetting chip (bit move.l #RAMBARx+1,D0 ;define init location movec D0,RAMBAR ;SRAM base register 5-2,3) ;RAMBARx value defined ;section $20000000 ******
Initialization Section (Users manual) MCF5206 provides centralized interrupt controller following modules 1)External interrupts 2)Software Watchdog Timer 3)Timer Modules 4)MBUS (I2C) module 5)UART modules Written below code that will interrupts 5206. interrupt levels priorities were chosen random demonstrative purposes. user should define interrupt level priorities their applications lines that commented commented enable this code function SBC5206 development system ***************** SIMR register SIMR, 7-9, follows: 1)Disable watchdog when FREEZE asserted (bit 2)Disable monitor when FREEZE asserted (bit 3)5206 will negate signal move.b #%11000000,D0 ;set SIMR 7-9) move.b D0,SIMR NOTE: timer MBUS peripherals cannot provide interrupt vectors.(see 7-5, paragraph). Timer MBUS peripherals only autovectored. Interrupt values were chosen randomly demonstrative purposes. user should change these their application needs. move.b #%10000100,D0 ;set Timer Interrupt move.b D0,ICR9 ;Level interrupt, Priority ;Autovector=ON, 7-10 ;avect 24+1=25 bottom 7-10 move.b move.b #%10001001,D0 ;set Timer Interrupt D0,ICR10 ;Level interrupt, Priority ;Autovector=ON,avect 24+2=26, ;see bottom 7-10 #%10001010,D0 ;set MBUS Interrupt D0,ICR11 ;Level interrupt, Priority ;Autovector=On,AVECT 24+3 ;see 7-10 #%00011011,D0 ;set UART1 Interrupt D0,ICR12 ;Level interrupt, Priority
move.b move.b
move.b move.b
;Autovector=Off move.b move.b #%00001001,D0 ;set UART2 Interrupt D0,ICR13 ;Level interrupt, Priority ;Autovector=Off
************************* register, 7-12 ************************* external interrupts enabled. UART1, UART2 interrupts disabled. MBUS, TIMER2 TIMER2 have interrupts disabled (i.e masked. 7-12 users manual). initialized theUARTs, M-BUS interrupt vectors TIMERS autovector. Enable interrupts each individualmodule register want them enabled. logic enables corresponding interrupt logic masks interrupt. Bits 13:1 used. Note: each module interrupts processor defined each module's configuration. move.w move.w #$3FFE,D0 D0,IMR ;set (interrupt mask ;register) interrupts ;see 7-12 users manual
****************** Watchdog timer ****************** move.b #$00,D0 move.b D0,SYPCR move.b move.b #70,D0 D0,SWIVR
;Disable "Watchdog" monitor ;see 7-14 users manual ;Watchdog interrupt vector ;the processor knows vector ;vector offset $118 ;see 7-16 users manual ;$70 random choice
****** CHIP SELECT Initialization Section (Users manual) chip select control external memory DRAM. this example, chip select single external FLASH device, 29F040. address lines data output. code size becomes larger than FLASH device, larger device used. Remember that MCF5206 address lines A28:24 muxed with CS/WE. your code exceeds (i.e. bits wide), will need alter register correct CS/WE/Address logic. This shown 7-17 assignments table
Chip select (CS0) will 29F040. entire address space address lines) will dedicated FLASH. additional peripherals that added should other chip selects defined somewhere above memory FLASH user code (i.e. address lines up)* Chip select addresses $001F0000 $001FFFFF (65K space). This used external peripheral. configured user data (UD). *NOTE: These lines have been commented SBC5206 development board. **************** *Chip select **************** move.w move.w
#$0000,D0 D0,CSAR0
;set base address Chip Select $00000000. ;see 8-29,30 users manual
***************** *CSMR0 register This register defines address mask what types accesses defined memory space enabled. CSAR register defined base address. this example that $00000000. define space from $00000000 $000FFFFF, CSMR register needs mask lower bits. logic means: this comparison. table below shows that once address call higher occurs, will fall outside range Chips Select Bits (CSARx) (CSMR0 reg)0 above table shows that access higher defined chip select 8-30,31 details. move.l #$000F0000,D0 ;set mask register move.l D0,CSMR0 ;0-19 (i.e. $00000000 $000FFFFF). ;All access types (SC,SD,UC,UD ;C/I) valid. 8-30,31 users manual
***************** *CSCR0 register
CSCR0 chip select control register defined follows (see 8-(33-38) users manual): 1)longest wait states until asserted (bits 13-10) 2)bursting enabled (bit 3)port size data bits (bits 7,6) 4)Chip select asserted with address (bit 8-35 5)Release address when negate writes (bit 8-36 6)Release address when negates reads (bit 8-37 7)No writes this address space (user code) 8-38 8)Allow reads this address space (bit 8-38 move.w move.w #$3F41,D0 D0,CSCR0 ;set chip select ;control register
*************** *Chip select *************** move.w move.w
#$0010,D0 D0,CSAR1
;set base address Chip Select $00100000. ;see 8-29,30 users manual ;set mask register addresses ;$00100000 $001FFFFF (65K space) ;Only valid access (user data) ;See 8-30,31 users manual
move.l #$000F001C,D0 move.l D0,CSMR1
***************** *DMCR register other memory spaces associated with chip selects DRAM banks considered "default memory". This register configures memory space. This similar CACR registers. move.w #$0000,D0 ;define control register move.w D0,DMCR ;memory defined chip select ;select registers. ;see 8-(38-43)of users manual following lines register. 7-16,17, table 7-9. this example register been enable pins follows: 1)output reset UART2 pin(PAR_7) 2)set IRQ7,4,1 inputs (PAR_6) 3)set general purpose (PAR_5,4) 4)WE[3:0] activated (PAR_3,2,1,0)
move.b move.b
#%00000000,D0 D0,PAR
;set (Pin Assignment Register.) ;see 7-16,17 users manual
INDIVIDUAL MODULE INITIALIZATION (Sections Parallel Port Initialization Section (Users manual) 5206 parallel port general I/O. pins muxed with DEBUG pins. This example initialization code sets parallel port. port follows: configured input Bits configured outputs set. outputs logic proper operation, PAR, bits 7-16,17) needs initialized logic move.b move.b move.b move.b #%01111111,D0 D0,PADDR #$7F,D0 D0,PADAT ;Bit input, bits outputs ;see users manual ;Initialize Parallel port Data reg. ;outputs logic "1". ;see 9-2,3 users manual
**** *10* DRAM Initialization Section (Users manual) DRAM controller glueless banks, 128K 256M byte sizes 2)Normal, fast page, burst mode. Also supports 3)Programmable refresh rates Each bank individually programmable except refresh registers (DCCR DCTR). These registers apply both banks. example below sets 4meg, normal mode, page,* memory bank refresh rates fastest* refresh rates. Bank therefore assumed used this example. registers initialized are: 1)DCTR sets refresh rate 2)DCAR sets base address memory bank 3)DCMR defines size DRAM memory. Also defines what kinds transfers occur such user, supervisor, etc.
4)DCCR defines port size, page size, page mode, DCAR0 register This example initializes DRAM address $00700000. This defined earlier section with variable DRAM0x. size DRAM initialized DCMR register. ******************* DCMR Register following table defines typical values common DRAM configurations. Load values into DCMR register each size. following table assumes transfer types (user, supervisor), bits left zero logic "0". this register used,* therefore, larger DRAM will always have fifth position. example, DRAM will have base address size from $FFFFF. will have size from 3FFFFF. 10-59 5206 users manual. DRAM SIZE DCMR value 128K $00000000 256K $00020000 512K $00060000 $000E0000 $001E0000 $003E0000 $007E0000 $00FE0000 Example code setting DRAM bank move.l #$007E0000,D0 move.l D0,DCMR0 NOTE: Base address located anywhere long does conflict with other memory spaces such code memory EPROM. suggested that DRAM should located above 128K memory space (i.e. 17). ***************** DCTR register DCTR register fastest rates. Make sure DRAM matches timing requirements change some values DCTR register accordingly. specific* DRAM chosen this designer should
this section match specifications their DRAM* DCTR register initialized follows: 1)Don't drive address signals during alt. master (bit 2)Standard DRAM, used (bit 3)/RAS asserts sys_clk before /CAS (bit 4)/RAS negates sys_clks after /CAS asserts (bits 10,9) 5)/RAS precharges sys_clks (bits 6,5) 6)/CAS asserts sys_clks (EDO=0) (bit 7)/CAS negates sys)clks (EDO=0) (bit 8)/CAS asserts sys_clk before asserting /RAS (bit move.w move.w #$0000,D0 D0,DCTR ;set DCTR1. fastest ;cycle timing. 10-(52-58) ;the users manual
****************** DCCR0 register This register defines port width, page size, transfer mode enables. 10-60 users manual. This example configured follows: 1)32 data port size (bits 7,6) 2)512 byte page size (bits 5,4) 3)Normal mode (bits 3,2) 4)Read Write capabilities enabled (bits 1,0) move.l move.l #$03,D0 ;set DCCR0 port size, D0,DCCR0 ;512 byte page, Normal mode, ;with both read write capability ;see 10-60,61 users manual #DRAM0x,D0 ;set DRAM0 base address (bits 31-17); D0,DCAR0 ;Lower bits default zeros. ;See 10-58 users manual ;DRAM0x defined section $00700000. #!32,D0 D0,DCRR0 ;set DCRR0. refresh ;every clocks. 32*16*(1/clk freq) ;see 10-51,52 users manual ;!32 decimal
move.w move.w
move.w move.w
****
move.l #$003E0000,D0 ;set DCMR0 (DRAM0 mask register) move.l D0,DCMR0 ;4Meg size ;See 10-59 users manual
*11* UART Initialization Section (Users manual) dual UARTs 5206 initialized baud rate, bits/character, parity, etc. Some important points are: 1)To initialize UARTs MUST reset each UART register. 2)Setting each UARTs UMR1&2 registers confusing. proper initialization, reset mode register pointer* register (MISCX=001, 11-25). This sets pointer UMR1. Now, configure UMR1 register. pointer will automatically increment UMR2. write UMR2 (which same address UMR1. pointer internal processor cannot seen programmer. This also explained paragraph describing UMR1 11-17. Also, 11-34 initialization procedures ;NOTE: UART Interrupts were disabled earlier initialization section ********* UART1 ********* code below initializes UART1 described 11-25 move.b #%00100000,D0 ;UART1 receiver reset move.b D0,UCR1 ;see 11-24,25 users manual move.b move.b move.b move.b #%00110000,D0 D0,UCR1 #%00010000,D0 D0,UCR1 ;UART1 transmitter reset ;see 11-24,25 users manual ;UART1 Mode register reset ;see 11-24,25 users manual ;this sets pointer UMR1
******** UMR1 UMR1 described below: Receiver request send automatically negated when FIFO empty position (BIT 7,UMR1). When UART acting receiver, /RTS acts /CTS external UART sending data. Receiver interrupts when FIFO full, single
received byte (BIT UMR1) Error occurs BLOCK mode (bit parity (BIT 4,3,2, UMR1) bits character (BIT UMR1) Note that UMR11 UMR21 both point same address section. Resetting Mode register pointer (UCR1 register) sets pointer UMR1. After writing UMR1 pointer points UMR2. should initialize UMR2 immediately after initializing UMR1. 11-(17-21)of users manual. ******** *(UMR2)* UMR2 UART1 follows: Normal Mode echo loopback (BIT 7,6,UMR2) Transmitter ready-to send /RTS effect, (BIT UMR2) Transmitter /CTS assert effect (BIT UMR2) stop sent (BIT 3,2,1,0 UMR2) 11-(19-21) users manual move.b move.b #$F3,D0 D0,UMR11 ;set UMR1 (UART1 mode register) ;see 11-17,18,19 users manual ;After writing this register, mode ;pointer points UMR2 which have defined UMR21, section. Note that ;this same address UMR11. next ;command below ;set UMR2 (UART1 mode register) ;see 11-19,20 users manual ;select timer mode Tx/Rx clocking ;see 11-24 users manual ;Disable interrupts COS&/CTS ;see 11-29 users manual interrupts enabled ;see 11-31 users manual ;Interrupt vector ($100) ;see 11-31 users manual ;vector random choice. decimal converted processor
move.b move.b move.b move.b move.b move.b move.b move.b move.b move.b
#$07,D0 D0,UMR21 #$DD,D0 D0,UCSR1 #$00,D0 D0,UACR1 #$00,D0 D0,UIMR1 #64,D0 D0,UIVR1
vector offset value $100 UART1 (UBG11 UBG21) 11-31 Baud rate taking system clock, dividing then divide that value concatenation decimal value UBG1 UBG2. This example assumes that clock select Timer mode described 11-24 USCR register Below example some approximate common baud rates: Example: 9600 baud rate (25mhz system clock) 9600 25mhz (1/32) (1/81) where UBG1=0 UBG2=81 decimal hex) baud rate UBG1(hex) UBG2(hex) (25MHZ clock) 1200 2400 4800 9600 19200 28800 33600 56000 128000 390625 (maximum) baud rate UBG1(hex) UBG2(hex) (33MHZ clock) 1200 2400 4800 9600 19200 28800 33600 56000 128000 515625 (maximum) move.b #$00,D0 ;Set baud rate 9,600 clk) move.b D0,UBG11 ;see 11-31 users manual move.b #$51,D0 ;concatenated value $0051 move.b D0,UBG21
********* UART2 *********
code below initializes UART2 described 11-25 move.b #%00100000,D0 ;UART2 receiver reset move.b D0,UCR2 ;see 11-24,25 users manual move.b move.b move.b move.b #%00110000,D0 D0,UCR2 #%00010000,D0 D0,UCR2 ;UART2 transmitter reset ;see 11-24,25 users manual ;UART2 Mode register reset ;see 11-24,25 users manual ;this sets pointer UMR1
******** UMR1 UMR1 UART described below: Receiver request send automatically negated when FIFO empty position (BIT 7,UMR1). When UART acting receiver, /RTS acts /CTS external UART sending data. Receiver interrupts when FIFO full, single received byte (BIT UMR1) Error occurs BLOCK mode (bit parity (BIT 4,3,2, UMR1) bits character (BIT UMR1) Note that UMR1 UMR2 both point same address section. Resetting Mode register pointer (UCR1 (register) sets pointer UMR1. 11-(17-21)of users manual. ******** *(UMR2)* UMR2 UART2 follows: Normal Mode echo loopback (BIT 7,6,UMR2) Transmitter ready-to send /RTS effect, (BIT UMR2) Transmitter /CTS assert effect (BIT UMR2) stop sent (BIT 3,2,1,0 UMR2) 11-(19-21) users manual move.b move.b move.b move.b #$F3,D0 D0,UMR12 #$07,D0 D0,UMR22 ;set UMR1 (UART1 mode register) ;see 11-17,18,19 users manual ;set UMR2 (UART1 mode register) ;see 11-19,20 users manual
move.b move.b move.b move.b move.b move.b move.b move.b
#$DD,D0 D0,UCSR2 #$00,D0 D0,UACR2 #$02,D0 D0,UIMR2 #65,D0 D0,UIVR2
;select timer mode Tx/Rx clocking ;see 11-24 users manual ;Disable interrupts COS&/CTS ;see 11-29 users manual ;Interrupt only when FIFO full ;see 11-31 users manual ;Interrupt vector ;see 11-31 users manual random choice. decimal converted processor vector offset value $104
UART2 (UBG12 UBG22) 11-31 Baud rate taking system clock, dividing then divide that value concatenation decimal value UBG1 UBG2. This example assumes that clock select Timer mode described 11-24 USCR register Below example some approximate common baud rates: Example: 9600 baud rate (25mhz system clock) 9600 25mhz (1/32) (1/81) where UBG1=0 UBG2=81 decimal hex) baud rate UBG1(hex) UBG2(hex) (25MHZ clock) 1200 2400 4800 9600 19200 28800 33600 56000 128000 390625 (maximum) baud rate UBG1(hex) UBG2(hex) (33MHZ clock) 1200 2400 4800 9600 19200 28800 33600
56000 128000 515625 (maximum) move.b #$00,D0 ;Set baud rate 33,600 clk) move.b D0,UBG12 ;see 11-31 users manual move.b #$17,D0 ;HEX value $0017 move.b D0,UBG22 **** *12* M-BUS Registers M-bus high speed, wire, serial that provides* bidirectional serial transmission between on-board devices compatible with Phillips standard. Maximum operating speed 100K bps. 12-1 users manual this example M_BUS will initialized with following specifications: Address (hex) wakes receiver (MADR). value "$1A" chosen randomly. Transmit speed baud (MFDR). 12-7 MBUS master, transmitting, interrupts, transmission acknowledge bit, repeat start (MBCR). ***************** MFDR Register M-BUS baud rate 12-6,7 Baud rate taking system clock dividing prescaler values defined 12-7 users manual. This value created MFDR register. Below example table possible baud rates that have been approximated. Example: 128K baud rate (25mhz system clock) 128K 25mhz 1/192 (Hex 31)value stored MFDR points value shown 12-7 baud rate MFDR(hex) divide value (25mhz clk) 12200 2048 24400 1024 32500 48800 56000 78000
97600 baud rate MFDR(hex) divide value (33mhz clk) 8600 3840 25780 1280 36830 51560 64450 73660 85950 ***************** MADR register ***************** MADR register, 12-6, sets address that "wakes-up" M-Bus. valid value sent, M-bus will respond when enabled slave ***************** MBCR register ***************** MBCR register, 12-8,is follows: 1)M-bus enabled (bit 2)Interrupts form M-bus disabled (bit 3)M-bus master (bit 4)Set transmit mode (bit 5)No acknowledge signal generated (bit 6)No repeat start generated (bit move.b move.b move.b move.b move.b move.b #$1A,D0 D0,MADR #$36,D0 D0,MFDR #%10111100,D0 D0,MBCR ;$1A address that wakes M-BUS ;see 12-3 12-6 users manual ;Set baud rate 56,000 mhz) ;see 12-6,7 users manual ;Setup M-BUS control register ;see 12-8 users manual
Other M-BUS registers used such status data register MBSR ;M-BUS Status Register, 8-bit, MBDR ;M-BUS Data Register, 8-bit, **** *13*
Timer Initialization Section users manual 5206 timers. They free running count value reset. following examples timers: Timer will count $AFAF, toggle output, reset back $0000. This will continue infinitely until timer disabled reset occurs. interrupts set. Prescale system clock divided Therefore resolution (16*(256))/25mhz 163.84us. Time period (16*256*44976)/25mhz 7.369s. $AFAF 44976 decimal) Timer will free-running send logic pulse every time compares count value register. value, which now, randomly chosen $1234. Prescale with sys_clock initially divided setting bits register therefore, resolution (16*(127))/25mhz 81.28us. Interrupts enabled. NOTE: timers were initialized have interrupt values. examples below have interrupts disabled initialization configuration reference. initialization autovectors have been Timers CANNOT provide interrupt vectors, only autovectors. initialization code also 7-10 setting ICRs *********** Timer *********** **************** register Bits 15:8 sets prescale ($FF) Bits interrupt ("00") Bits sets output mode "toggle". interrupts("10") Bits "restart" ("1") Bits clocking source system clock/16 ("10") Bits enables/disables timer ("0") move.w move.w #$FF2C,D0 D0,TMR1 ;Setup Timer mode register (TMR1) ;see 13-4 users manual ;Bit disable timer ;See Timer test code ;this file. ;writing timer counter with ;any value resets zero
move.w move.w
#$0000,D0 D0,TCN1
***************** TRR1 register register $AFAF. timer will count this value (TCN TRR), toggle "TOUT" pin, reset $0000. 13-4,5 move.w move.w #$AFAF,D0 ;Setup Timer reference register (TRR1) D0,TRR1 ;see 13-5 users manual
Other registers used TIMER TCR1 ;TIMER1 Capture Register, 16-bit, TER1 ;TIMER1 Event Register, 8-bit, *********** Timer *********** ***************** TMR2 register ***************** Bits 15:8 prescale ($7F) Bits capture mode interrupt ("00") Bits output mode "pulse" interrupt ("00")* Bits free-running ("0") Bits clocking source clk/16 ("10") Bits enables timer ("0") move.w #$7F04,D0 ;Setup Timer mode register (TMR2) move.w D0,TMR2 ;see 13-4 users manual move.w move.w #$1234,D0 D0,TRR2 ;Set Timer reference $1234 ;see 13-5 users manual
move.w #$0000,D0 ;writing timer counter with move.w D0,TCN2 ;any value resets zero 0ther registers used TCR2 ;TIMER2 Capture Register, 16-bit, TER2 ;TIMER2 Event Register, 8-bit, MODULE INITIALIZATION
MAIN code. Written below some code segments show explain some modules 5206 used configured. brief explanation each follows: TIMER1 code segment This piece code counts $AFAF times. Everytime reaches $AFAF sets output reference (and pin). counter resets after reaching $AFAF begins counting again. Once counter reaches 2,the code segment finishes* runs UART TRANSMIT code segment. UART TRANSMIT code segment This piece code transmits message terminal such WIN95 Hyperterm. sends message "Welcome Motorola's COLDFIRE!!!" After completing this section, Program moves UART RECEIVE code segment. UART RECEIVE code segment This piece code recieves characters from terminal such WIN95 Hyperterm. polls RxRDY character stores into memory. After receiving characters moves UART INTERRUPT WITH INTERRUPTS code segment. must send characters exit this part program otherwise will continue loop. UART RECEIVE WITH INTERRUPTS code segment This piece code recieves characters from terminal such WIN95 Hyperterm. uses interrupts service storing character into memory. counts characters stores into memory. After receiving characters program halts executing HALT command. must send characters exit this part program. XDEF _test_code _test_code RAMBARx+$200,A7 ;Setup stack pointer (A7) point ;SRAM. SRAM will used ;part stack. ******************** TIMER1 test code This simple piece code enables TIMER1 increments counter each time toggles output. (See TIMER1 configuration code). code monitors register 13-6 users manual). When "ref" register counter increment until reaches decimal. Then code will jump loop, disable TIMER1 next piece code. This creates delay approximatly 14.74 seconds. lea.l
INFO: must write bit, register clear T1_TST clr.l ;clear D3-D0 data registers clr.l clr.l clr.l move.w move.w move.b move.b move.w bset move.w T1_LP move.b btst TER1,D1 #1,D1 T1_LP ;load Timer Event register into ;Does TRR1=TCN1. (i.e. 'ref", set? TRR1 defined $AFAF Timer1 initialization ;If("0")then continue looping. next ;command below when #$0000,D0 D0,TCN1 #$03,D1 D1,TER1 TMR1,D0 #0,D0 D0,TMR1 write value resets zeros. 13-5 users ;manual ;reset writing 13-6 ;these lines enable timer setting TMR1 ;see 13-4 users manual
addi.l #1,D2 ;count from cmp.l #2,D2 ;does T1_FIN ;Finish equal move.b move.b T1_FIN move.w bclr move.w move.b move.b move.w move.w #$02,D1 D1,TER1 T1_LP TMR1,D0 #0,D0 D0,TMR1 #$02,D1 D1,TER1 #$0000,D3 D3,TCN1 ;reset writing 13-6 ;loop until ;these lines disable TIMER1 clearing TMR1 13-4 ;reset 13-6 ;reset counter zero's 13-5
**************************** UART1 transmit test code code below prints message UART message "Welcome Motorola COLDFIRE". code keeps sending
UART until number recognized character string. using debugger, computer check this code. Connect serial cable form 5206 board (connector J6). Win95's Hyperterminal with following settings: 9600 baud, data bits,1 stop bit, parity, Hardware flow control=none Then this program 5206 board. message "Welcome Motorola's COLDFIRE" should appear Hyper* terminal screen. Make sure turn 16550 UARTs disabled. This done WIN95 Hyperterminal under advanced settings. U1_T lea.l clr.l clr.l move.b move.b LOOP1 move.b cmp.l move.b UART_T,A1 #%00000100,D1 D1,UCR1 (A1)+,D0 #$30,D0 URT_FIN D0,UTB1 ;set address pointer ;beginning string ;clear registers ;enable transmitter 11-25,26) ;and disable receiver ;load character into ;from "MOT" ascii line character acsii jump loop ;load value transmit ;buffer. Loading UTB1 ;begins transmission ;test (transmitter empty)
WAIT move.b btst URT_FIN
USR1,D1 #$03,D1 WAIT LOOP1
UART1 transmit test code ******************************* UART1 receive test code code below receives text data from terminal. best way* this code create text file alphabet
send 5206 board This code pools RxRDY character been received. has, gets stored into memory address pointer pointer incremented counter counts charcaters. When counter, reaches (i.e.0-25=26)the routine leaves loop ends this part UART receive test code. U1_R lea.l UART_R,A1 ;set address pointer ;beginning string clr.l clr.l clr.l move.b move.b RWAIT move.b btst move.b move.b #%00001001,D1 D1,UCR1 USR1,D1 #$0,D1 RWAIT URB1,D0 D0,(A1)+ ;load character into ;and store storage ;UART_R ;count (0-25) ;has character been received? "0", then loop RWAIT ;clear registers
;enable receiver(pg 11-25,26) ;and disable transmitter
addi.l #1,D2 cmp.l #25,D2 UR_FIN RWAIT UR_FIN
UART1 receive test code (Interrupts Enabled) This code does exactly what UART1 receive code does except interrupts implemented. processor interrupts when URT1 receives character. interrupt routine called "URT1_INT" simply stores value into memory block called "URT_R_INT". After characters received, code disables interrupts stops with HALT command. interrupt vectors were defined section URT1 assigned vector #64. vector table, vector number points URT1_INT
lea.l clr.l clr.l clr.l move.b move.b move.b move.b move.b move.b
U1_RINT,A0 #%00100000,D0 D0,UCR1 #%00001001,D0 D0,UCR1 #%00010000,D0 D0,UCR1
;set address pointer ;beginning string ;clear registers ;UART1 receiver reset ;see 11-24,25 users manual ;enable receiver(pg 11-25,26) ;and disable transmitter ;UART1 Mode register reset ;see 11-24,25 users manual ;this sets pointer UMR1
UMR1 interrupts RxRDY (bit move.b #$B3,D0 move.b D0,UMR11 defined
;set UMR1 (UART1 mode register) ;see 11-17,18,19 users manual ;After writing this register, mode ;pointer points UMR2 which have UMR21, section. next ;command below
move.b move.b move.w bclr move.w
#$07,D0 D0,UMR21 IMR,D0 #12,D0 D0,IMR
;set UMR2 (UART1 mode register) ;see 11-19,20 users manual ;enable interrupts UART1 ;see 7-12 users manual used lines code retain ;original settings 7-12 ;set receiver interrupt ;RxRDY. This UIMR1
move.b move.b
#$02,D0 D0,UIMR1
Below loop that will continue until D2=10. when character received, interrupt will occur load character into storage bytes located "URT1_R_INT". interrupt will return loop below. When D2=10 processor will leave loop, disable UART1 interrupts halt* clr.l clr.l UNTIL_10
move.b move.w cmp.l move.w bset move.w
USR1,D1 IPR,D1 #10,D2 UNTIL_10 IMR,D0 #12,D0 D0,IMR ;loop until D2=10 ;disable interrupts UART1 ;see 7-12 users manual ;stop processing
halt ****************************** Interrupt handler routines ****************************** UART1_INT move.b URB1,D0 move.b addi.l #1,D2 UART2_INT TIMER1_INT TIMER2_INT MBUS_INT WDOG_INT move.b move.b move.b move.b $55,D0 D0,SWSR $AA,D0 D0,SWSR D0,(A0)+
;load received character ;into register ;load character into ;and store storage ;URT1_RINT ;count (0-9)
Definitions reserved memory bytes UART_T .ascii "Welcome Motorola's COLDFIRE!!0" UART_R DS.B U1_RINT ;Storage characters (alphabet) ;from terminal
DS.B
;Storage characters (alphabet) ;from terminal

IMPORTANT: SBC5206 development system uses different memory mapping wh

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