Hardware Functional Specification Document Number: X31B-A-001-09
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S1D13706 Embedded Memory Controller
Hardware Functional Specification
Document Number: X31B-A-001-09
Copyright 1999, 2004 Epson Research Development, Inc. Rights Reserved. Information this document subject change without notice. download this document, only your evaluating Seiko Epson/EPSON products. modify document. Epson Research Development, Inc. disclaims representation that contents this document accurate current. Programs/Technologies described this document contain material protected under U.S. and/or International Patent laws. EPSON registered trademark Seiko Epson Corporation. other Trademarks property their respective owners
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S1D13706 X31B-A-001-09
Hardware Functional Specification Issue Date: 2004/02/09
Epson Research Development Vancouver Design Center
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Table Contents
Introduction Scope Overview Description Features Integrated Frame Buffer Interface Display Support Display Modes Display Features Clock Source Miscellaneous
Typical System Implementation Diagrams Pins Pinout Diagram TQFP15 100pin Pinout Diagram Form Descriptions 4.3.1 Host Interface 4.3.2 Interface 4.3.3 Clock Input 4.3.4 Miscellaneous 4.3.5 Power Ground Summary Configuration Options Host Interface Mapping Interface Mapping
D.C. Characteristics A.C. Characteristics Clock Timing 6.1.1 Input Clocks 6.1.2 Internal Clocks Interface Timing 6.2.1 Generic Interface Timing 6.2.2 Generic Interface Timing (e.g. ISA) 6.2.3 Hitachi SH-4 Interface Timing 6.2.4 Hitachi SH-3 Interface Timing 6.2.5 Motorola MC68K Interface Timing (e.g. MC68000) 6.2.6 Motorola MC68K Interface Timing (e.g. MC68030)
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6.2.7 Motorola REDCAP2 Interface Timing 6.2.8 Motorola DragonBall Interface Timing with DTACK (e.g. MC68EZ328/MC68VZ328) 6.2.9 Motorola DragonBall Interface Timing DTACK (e.g. MC68EZ328/MC68VZ328) Power Sequencing 6.3.1 Passive/TFT Power-On Sequence 6.3.2 Passive/TFT Power-Off Sequence Display Interface 6.4.1 Generic Panel Timing 6.4.2 Single Monochrome 4-Bit Panel Timing 6.4.3 Single Monochrome 8-Bit Panel Timing 6.4.4 Single Color 4-Bit Panel Timing 6.4.5 Single Color 8-Bit Panel Timing (Format 6.4.6 Single Color 8-Bit Panel Timing (Format 6.4.7 Single Color 16-Bit Panel Timing 6.4.8 Generic Panel Timing 6.4.9 9/12/18-Bit Panel Timing 6.4.10 160x160 Sharp `Direct' HR-TFT Panel Timing (e.g. LQ031B1DDxx) 6.4.11 320x240 Sharp `Direct' HR-TFT Panel Timing (e.g. LQ039Q2DS01) 6.4.12 160x240 Epson D-TFD Panel Timing (e.g. LF26SCR) 6.4.13 320x240 Epson D-TFD Panel Timing (e.g. LF37SQR) Clocks Clock Descriptions 7.1.1 BCLK 7.1.2 MCLK 7.1.3 PCLK 7.1.4 PWMCLK Clock Selection Clocks versus Functions .101 .109 .115 .120
Registers Register Mapping Register Register Descriptions 8.3.1 Read-Only Configuration Registers 8.3.2 Clock Configuration Registers 8.3.3 Look-Up Table Registers 8.3.4 Panel Configuration Registers 8.3.5 Display Mode Registers 8.3.6 Picture-in-Picture Plus (PIP+) Registers 8.3.7 Miscellaneous Registers
S1D13706 X31B-A-001-09
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8.3.8 8.3.9
General Pins Registers Pulse Width Modulation (PWM) Clock Contrast Voltage (CV) Pulse Configuration Registers
Frame Rate Calculation
Display Data Formats
Look-Up Table Architecture 11.1 Monochrome Modes 11.2 Color Modes SwivelView. 12.1 Concept 12.2 SwivelView. 12.2.1 Register Programming 12.3 180° SwivelView. 12.3.1 Register Programming 12.4 270° SwivelView. 12.4.1 Register Programming Picture-in-Picture Plus (PIP+) 13.1 Concept 13.2 With SwivelView Enabled 13.2.1 SwivelView 13.2.2 SwivelView 180° 13.2.3 SwivelView 270°
Big-Endian Interface 14.1 Byte Swapping Data 14.1.1 Color Depth 14.1.2 1/2/4/8 Color Depth
Power Save Mode Mechanical Data References Sales Technical Support
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List Tables
Table 4-1: Pinout Assignments Form (S1D13706D00A) Table 4-2: Host Interface Descriptions Table 4-3: Interface Descriptions Table 4-4: Clock Input Descriptions. Table 4-5: Miscellaneous Descriptions Table 4-6: Power Ground Descriptions Table 4-7: Summary Power-On/Reset Options Table 4-8: Host Interface Mapping Table 4-9: Interface Mapping Table 5-1: Absolute Maximum Ratings Table 5-2: Recommended Operating Conditions Table 5-3: Electrical Characteristics 3.3V typical Table 6-1: Clock Input Requirements CLKI when CLKI BCLK divide Table 6-2: Clock Input Requirements CLKI when CLKI BCLK divide Table 6-3: Clock Input Requirements CLKI2 Table 6-4: Internal Clock Requirements Table 6-5: Generic Interface Timing Table 6-6: Generic Interface Timing Table 6-7: Hitachi SH-4 Interface Timing Table 6-8: Hitachi SH-3 Interface Timing Table 6-9: Motorola MC68K Interface Timing Table 6-10: Motorola MC68K Interface Timing Table 6-11: Motorola REDCAP2 Interface Timing. Table 6-12: Motorola DragonBall Interface with DTACK Timing Table 6-13: Motorola DragonBall Interface without DTACK Timing Table 6-14: Passive/TFT Power-On Sequence Timing Table 6-15: Passive/TFT Power-Off Sequence Timing Table 6-16: Panel Timing Parameter Definition Register Summary Table 6-17: Single Monochrome 4-Bit Panel A.C. Timing Table 6-18: Single Monochrome 8-Bit Panel A.C. Timing Table 6-19: Single Color 4-Bit Panel A.C. Timing Table 6-20: Single Color 8-Bit Panel A.C. Timing (Format Table 6-21: Single Color 8-Bit Panel A.C. Timing (Format Table 6-22: Single Color 16-Bit Panel A.C. Timing Table 6-23: A.C. Timing Table 6-24: 160x160 Sharp `Direct' HR-TFT Horizontal Timing Table 6-25: 160x160 Sharp `Direct' HR-TFT Panel Vertical Timing
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Table 6-26: 320x240 Sharp `Direct' HR-TFT Panel Horizontal Timing Table 6-27: 320x240 Sharp `Direct' HR-TFT Panel Vertical Timing Table 6-28: 160x240 Epson D-TFD Panel Horizontal Timing Table 6-29: 160x240 Epson D-TFD Panel Horizontal Timing Table 6-30: 160x240 Epson D-TFD Panel Vertical Timing Table 6-31: 320x240 Epson D-TFD Panel Horizontal Timing Table 6-32: 320x240 Epson D-TFD Panel Horizontal Timing Table 6-33: 320x240 Epson D-TFD Panel Vertical Timing Table 7-1: BCLK Clock Selection Table 7-2: MCLK Clock Selection. Table 7-3: PCLK Clock Selection Table 7-4: Relationship between MCLK PCLK. Table 7-5: PWMCLK Clock Selection. Table 7-6: S1D13706 Internal Clock Requirements Table 8-1: S1D13706 Register Table 8-2: MCLK Divide Selection Table 8-3: PCLK Divide Selection. Table 8-4: PCLK Source Selection. Table 8-5: Panel Data Width Selection Table 8-6: Active Panel Resolution Selection Table 8-7: Panel Type Selection Table 8-8: Inverse Video Mode Select Options Table 8-9: Bit-per-pixel Selection Table 8-10: SwivelViewMode Select Options Table 8-11: 32-bit Address Increments Color Depth Table 8-12: 32-bit Address Increments Color Depth Table 8-13: 32-bit Address Increments Color Depth Table 8-14: 32-bit Address Increments Color Depth Table 8-15: Clock Control Table 8-16: Pulse Control Table 8-17: Clock Divide Select Options Table 8-18: Pulse Divide Select Options Table 8-19: PWMOUT Duty Cycle Select Options Table 15-1: Power Save Mode Function Summary
.102 .102 .102 .110 .111 .112 .116 .117 .118 .119 .126 .127 .128 .128 .129 .149
S1D13706 X31B-A-001-09
Hardware Functional Specification Issue Date: 2004/02/09
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List Figures
Figure 3-1: Figure 3-2: Figure 3-3: Figure 3-4: Figure 3-5: Figure 3-6: Figure 3-7: Figure 3-8: Figure 4-1: Figure 4-2: Figure 6-1: Figure 6-2: Figure 6-3: Figure 6-4: Figure 6-5: Figure 6-6: Figure 6-7: Figure 6-8: Figure 6-9: Figure 6-10: Figure 6-11: Figure 6-12: Figure 6-13: Figure 6-14: Figure 6-15: Figure 6-16: Figure 6-17: Figure 6-18: Figure 6-19: Figure 6-20: Figure 6-21: Figure 6-22: Figure 6-23: Figure 6-24: Figure 6-25: Figure 6-26: Figure 6-27: Typical System Diagram (Generic Bus) Typical System Diagram (Generic Bus) Typical System Diagram (Hitachi SH-4 Bus) Typical System Diagram (Hitachi SH-3 Bus) Typical System Diagram (MC68K Motorola 16-Bit 68000) Typical System Diagram (MC68K Motorola 32-Bit 68030) Typical System Diagram (Motorola REDCAP2 Bus) Typical System Diagram (Motorola MC68EZ328/MC68VZ328 "DragonBall" Bus) Pinout Diagram TQFP15 100pin (S1D13706F00A) Pinout Diagram Form (S1D13706D00A) Clock Input Requirements Generic Interface Timing Generic Interface Timing Hitachi SH-4 Interface Timing Hitachi SH-3 Interface Timing Motorola MC68K Interface Timing. Motorola MC68K Interface Timing. Motorola REDCAP2 Interface Timing Motorola DragonBall Interface with DTACK Timing Motorola DragonBall Interface without DTACK# Timing Passive/TFT Power-On Sequence Timing Passive/TFT Power-Off Sequence Timing Panel Timing Parameters Generic Panel Timing Single Monochrome 4-Bit Panel Timing Single Monochrome 4-Bit Panel A.C. Timing Single Monochrome 8-Bit Panel Timing Single Monochrome 8-Bit Panel A.C. Timing Single Color 4-Bit Panel Timing Single Color 4-Bit Panel A.C. Timing Single Color 8-Bit Panel Timing (Format Single Color 8-Bit Panel A.C. Timing (Format Single Color 8-Bit Panel Timing (Format Single Color 8-Bit Panel A.C. Timing (Format Single Color 16-Bit Panel Timing Single Color 16-Bit Panel A.C. Timing Generic Panel Timing
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Figure 6-28: Figure 6-29: Figure 6-30: Figure 6-31: Figure 6-32: Figure 6-33: Figure 6-34: Figure 6-35: Figure 6-36: Figure 6-37: Figure 6-38: Figure 6-39: Figure 7-1: Figure 8-1: Figure 8-2: Figure 10-1: Figure 11-1: Figure 11-2: Figure 11-3: Figure 11-4: Figure 11-5: Figure 11-6: Figure 11-7: Figure 11-8: Figure 12-1: Figure 12-2: Figure 12-3: Figure 13-1: Figure 13-2: Figure 13-3: Figure 13-4: Figure 14-1: Figure 14-2: Figure 16-1:
18-Bit Panel Timing A.C. Timing 160x160 Sharp `Direct' HR-TFT Panel Horizontal Timing 160x160 Sharp `Direct' HR-TFT Panel Vertical Timing. 320x240 Sharp `Direct' HR-TFT Panel Horizontal Timing 320x240 Sharp `Direct' HR-TFT Panel Vertical Timing. 160x240 Epson D-TFD Panel Horizontal Timing 160x240 Epson D-TFD Panel Horizontal Timing 160x240 Epson D-TFD Panel Vertical Timing 320x240 Epson D-TFD Panel Horizontal Timing 320x240 Epson D-TFD Panel Horizontal Timing 320x240 Epson D-TFD Panel Vertical Timing Clock Selection Display Data Byte/Word Swap Clock/CV Pulse Block Diagram 4/8/16 Bit-Per-Pixel Display Data Memory Organization Bit-per-pixel Monochrome Mode Data Output Path Bit-per-pixel Monochrome Mode Data Output Path Bit-per-pixel Monochrome Mode Data Output Path Bit-per-pixel Monochrome Mode Data Output Path Bit-Per-Pixel Color Mode Data Output Path Bit-Per-Pixel Color Mode Data Output Path Bit-Per-Pixel Color Mode Data Output Path Bit-per-pixel Color Mode Data Output Path Relationship Between Screen Image Image Refreshed SwivelView. Relationship Between Screen Image Image Refreshed SwivelView.140 Relationship Between Screen Image Image Refreshed SwivelView.141 Picture-in-Picture Plus with SwivelView disabled Picture-in-Picture Plus with SwivelView enabled Picture-in-Picture Plus with SwivelView 180° enabled Picture-in-Picture Plus with SwivelView 270° enabled Byte-swapping Byte-swapping 1/2/4/8 Mechanical Data 100pin TQFP15 (S1D13706F00A)
S1D13706 X31B-A-001-09
Hardware Functional Specification Issue Date: 2004/02/09
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Introduction
Scope
This Hardware Functional Specification S1D13706 Embedded Memory Controller. Included this document timing diagrams, characteristics, register descriptions, power management descriptions. This document intended audiences: Video Subsystem Designers Software Developers. additional documentation related S1D13706 Section "References" page 151. This document updated appropriate. Please check Epson Research Development Website www.erd.epson.com latest revision this document before beginning development. appreciate your comments documentation. Please contact email documentation@erd.epson.com.
Overview Description
S1D13706 color/monochrome graphics controller with embedded byte SRAM display buffer. While supporting other panel types, S1D13706 only controller directly interface both Epson D-TFD Sharp HR-TFT family products thus removing requirement external Timing Control This high level integration provides cost, power, single chip solution meet demands embedded markets such Mobile Communications devices Palm-size PCs, where board size battery life major concerns. S1D13706 utilizes guaranteed low-latency architecture providing support microprocessors without READY/WAIT# handshaking signals. 32-bit internal data path provides high performance bandwidth into display memory allowing fast screen updates. Products requiring rotated display image take advantage SwivelView feature which provides hardware rotation display memory transparent software application. S1D13706 also provides support "Picture-in-Picture Plus" variable size Overlay window). S1D13706 provides impressive support Palm handhelds, however impartiality type operating system makes ideal display solution wide variety applications.
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Features
Integrated Frame Buffer
Embedded byte SRAM display buffer.
Interface
Direct support following interfaces: Generic interface using WAIT# signal. Hitachi SH-3. Hitachi SH-4. Motorola M68K. Motorola MC68EZ328/MC68VZ328 DragonBall. Motorola "REDCAP2" WAIT# signal. 8-bit processor support with "glue logic". "Fixed" low-latency access times. Registers memory-mapped M/R# input selects between memory register address space. complete byte display buffer directly contiguously available through 17-bit address bus. Single level write buffer.
Display Support
Single-panel, single-drive passive displays. 4/8-bit monochrome interface. 4/8/16-bit color interface. Active Matrix interface. 9/12/18-bit interface. `Direct' support 18-bit Epson D-TFD interface. `Direct' support 18-bit Sharp HR-TFT interface.
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Hardware Functional Specification Issue Date: 2004/02/09
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Display Modes
1/2/4/8/16 bit-per-pixel (bpp) color depths. gray shades using Frame Rate Modulation (FRM) dithering monochrome passive panels. colors passive panels. colors active matrix panels. Example resolutions: 320x240 color depth 160x160 color depth 160x240 color depth
Display Features
SwivelViewTM: 90°, 180°, 270° counter-clockwise hardware rotation display image. "Picture-in-Picture Plus": displays variable size window overlaid over background image. Double Buffering/Multi-pages: provides smooth animation instantaneous screen updates.
Clock Source
clock inputs: CLKI CLKI2. possible clock input only. clock derived from CLKI internally divided Memory clock derived from clock. internally divided Pixel clock derived from CLKI, CLKI2, clock, memory clock. internally divided
Miscellaneous
Hardware/Software Video Invert. Software Power Save mode. General Purpose Input/Output pins available. 100-pin TQFP15 package. 104-pin CFLGA package. form available.
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Typical System Implementation Diagrams
Oscillator
Generic
A[27:17] Decoder M/R#
CLKI2
HIOVDD
FPDAT[15:0] FPFRAME
16-bit Single FPFRAME Display
D[15:0] FPLINE FPSHIFT Bias Power
CSn# A[16:1] D[15:0] WE0# WE1# RD0# RD1# WAIT# BUSCLK RESET#
AB[16:1] DB[15:0] WE0# WE1# RD/WR# WAIT# CLKI RESET#
FPLINE FPSHIFT DRDY
S1D13706
Figure 3-1: Typical System Diagram (Generic Bus)
Oscillator
Generic
RD/WR# A[27:17] CSn# A[16:0] D[15:0] BHE# Decoder M/R# AB[16:0] DB[15:0] WE0# WE1#
CLKI2
FPDAT[8:0] FPFRAME
D[8:0] FPFRAME
9-bit Display
Bias Power
FPLINE FPSHIFT
FPLINE FPSHIFT DRDY
S1D13706
DRDY
WAIT#
WAIT#
BUSCLK RESET#
CLKI RESET#
Figure 3-2: Typical System Diagram (Generic Bus)
S1D13706 X31B-A-001-09 Hardware Functional Specification Issue Date: 2004/02/09
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Oscillator
SH-4
CLKI2 A[25:17] Decoder M/R# FPDAT15 FPDAT12 CSn# A[16:1] D[15:0] WE0# WE1# RD/WR# AB[16:1] DB[15:0] WE0# WE1# RD/WR# FPDAT[9:0] FPFRAME FPLINE FPSHIFT DRDY D[9:0] FPFRAME Bias Power FPLINE FPSHIFT DRDY
12-bit Display
S1D13706
RDY# CKIO RESET#
WAIT# CLKI RESET#
Figure 3-3: Typical System Diagram (Hitachi SH-4 Bus)
Oscillator
SH-3
CLKI2 A[25:17] Decoder M/R#
FPDAT[17:0] CSn# A[16:1] D[15:0] WE0# WE1# RD/WR# AB[16:1] DB[15:0] WE0# WE1# RD/WR# FPSHIFT DRDY FPFRAME
D[17:0] FPFRAME
18-bit Display
Bias Power
FPLINE
FPLINE FPSHIFT DRDY
S1D13706
WAIT# CKIO RESET#
WAIT# CLKI RESET#
Figure 3-4: Typical System Diagram (Hitachi SH-3 Bus)
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Oscillator
MC68K
WE0# A[23:17] FC0, Decoder M/R#
CLKI2
HIOVDD
FPDAT[17:0] FPFRAME FPLINE FPSHIFT
D[17:0]
18-bit HR-TFT Display
A[16:1] D[15:0] LDS# UDS# R/W# DTACK#
AB[16:1] DB[15:0] WE1# RD/WR# WAIT#
GPIO1 GPIO2 GPIO3
S1D13706
RESET#
CLKI RESET#
Figure 3-5: Typical System Diagram (MC68K Motorola 16-Bit 68000)
Oscillator
MC68K
A[31:17] FC0, CLKI2 Decoder M/R# FPDAT[17:0] FPFRAME FPLINE FPSHIFT A[16:0] D[31:16] AB[16:0] DB[15:0] DRDY GPIO0 GPIO1 R/W# SIZ1 SIZ0 DSACK1# WE1# RD/WR# WE0# WAIT# GPIO2 D[17:0] XSCL XINH YSCL DD_P1 YSCLD XSET (Bias Power)
Decoder
S1D13706
GPIO3 GPIO4 GPIO5 GPIO6
RESET#
CLKI RESET#
Figure 3-6: Typical System Diagram (MC68K Motorola 32-Bit 68030)
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Hardware Functional Specification Issue Date: 2004/02/09
Bias Power
Decoder
GPIO0
18-bit D-TFD Display
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Oscillator
A[21:17] A[16:1] D[15:0] Decoder M/R# AB[16:1] DB[15:0]
CLKI2
REDCAP2
HIOVDD
FPDAT[7:4] FPSHIFT FPFRAME FPLINE DRDY
D[3:0] FPSHIFT
4-bit Single Display
Bias Power
FPFRAME FPLINE
RESET_OUT *Note: CSn# CS0-CS4
RD/WR# WE0# WE1# CLKI RESET#
S1D13706
Figure 3-7: Typical System Diagram (Motorola REDCAP2 Bus)
Oscillator
MC68EZ328/ MC68VZ328 DragonBall
A[25:17]
RD/WR# Decoder M/R#
CLKI2
HIOVDD
FPDAT[7:0] FPSHIFT
D[7:0] FPSHIFT
8-bit Single Display
Bias Power
A[16:1] D[15:0]
AB[16:1] DB[15:0]
FPFRAME FPLINE DRDY
FPFRAME FPLINE
S1D13706
DTACK CLKO RESET
WE0# WE1# WAIT# CLKI RESET#
Figure 3-8: Typical System Diagram (Motorola MC68EZ328/MC68VZ328 "DragonBall" Bus)
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Pins
Pinout Diagram TQFP15 100pin
FPDAT17
FPDAT16
FPDAT15
FPDAT14
FPDAT13
FPDAT12
FPDAT11
FPDAT10
FPDAT9
FPDAT8
FPDAT7
NIOVDD
FPDAT6
FPDAT5
FPDAT4
FPDAT3
FPDAT2
FPDAT1
FPDAT0
FPSHIFT
FPLINE
FPFRAME
COREVDD
NIOVDD CLKI2 CNF7 CNF6 CNF5 CNF4 CNF3 CNF2 CNF1 CNF0
DRDY
NIOVDD
CVOUT GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 PWMOUT NIOVDD RD/WR# RESET# HIOVDD HIOVDD DB15 DB14 DB13 DB12 DB10 DB11 WAIT# WE0# WE1# M/R# CLKI
TESTEN AB16 AB15 AB14 AB13 AB12 AB11 AB10 COREVDD
S1D13706
Figure 4-1: Pinout Diagram TQFP15 100pin (S1D13706F00A)
Note
Package type: surface mount TQFP15
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Pinout Diagram Form
X5534D
Unusable
(0,0)
Unusable
Figure 4-2: Pinout Diagram Form (S1D13706D00A) Chip Size: 5.88 6.55 size:
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Table 4-1: Pinout Assignments Form (S1D13706D00A)
Name LVDD M/R# WE0# WE1# RD/WR# RESET# CLKI HVDD WAIT# DB15 DB14 DB13 DB12 DB11 DB10 HVDD HVDD PWMOUT GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 CVOUT DRDY HVDD (µm) -2331 -2100 -1932 -1680 -1512 -1344 -1092 -924 -672 -504 -336 1092 1260 1512 1680 1848 2100 2331 2813 2813 2813 2813 2813 2813 2813 2813 2813 2813 2813 2813 2813 2813 2813 2813 2813 2813 2813 2813 2813 2813 2813 2813 2813 2813 (µm) -3149 -3149 -3149 -3149 -3149 -3149 -3149 -3149 -3149 -3149 -3149 -3149 -3149 -3149 -3149 -3149 -3149 -3149 -3149 -3149 -3149 -3149 -3149 -3149 -2478 -2310 -2142 -1890 -1722 -1470 -1302 -1134 -882 -714 -546 -294 -126 1050 1302 1470 1722 1890 2058 2310 2478 Name LVDD FPFRAME FPLINE FPSHIFT FPDAT0 FPDAT1 FPDAT2 FPDAT3 FPDAT4 FPDAT5 FPDAT6 HVDD FPDAT7 FPDAT8 FPDAT9 FPDAT10 FPDAT11 FPDAT12 FPDAT13 FPDAT14 FPDAT15 FPDAT16 FPDAT17 HVDD CLKI2 CNF7 CNF6 CNF5 CNF4 CNF3 CNF2 CNF1 CNF0 TESTEN AB16 AB15 AB14 AB13 AB12 AB11 AB10 (µm) 2813 2100 1932 1680 1512 1344 1092 -252 -504 -672 -924 -1092 -1260 -1512 -1680 -1848 -2100 -2331 -2813 -2813 -2813 -2813 -2813 -2813 -2813 -2813 -2813 -2813 -2813 -2813 -2813 -2813 -2813 -2813 -2813 -2813 -2813 -2813 -2813 -2813 -2813 -2813 -2813 -2813 (µm) 2667 3149 3149 3149 3149 3149 3149 3149 3149 3149 3149 3149 3149 3149 3149 3149 3149 3149 3149 3149 3149 3149 3149 3149 2478 2310 2142 1890 1722 1470 1302 1134 -126 -294 -462 -714 -882 -1050 -1302 -1470 -1722 -1890 -2058 -2310 -2478
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Descriptions
Key:
LB2A LB3P LB3M Hi-Z Input Output Bi-Directional (Input/Output) Power LVTTLa Schmitt input LVTTL input LVTTL buffer (6mA/-6mA@3.3V) noise LVTTL buffer (12mA/-12mA@3.3V) noise LVTTL Output buffer (12mA/-12mA@3.3V) noise LVTTL buffer with input mask (12mA/-12mA@3.3V) Test mode control input with pull-down resistor (typical value 3.3V) High Impedance
LVTTL Voltage (see Section "D.C. Characteristics" page 31).
4.3.1 Host Interface
Table 4-2: Host Interface Descriptions
Name Type Cell RESET# Voltage State Description This input multiple functions. Generic this used should connected VSS. Generic this inputs system address (A0). SH-3/SH-4, this used should connected VSS. MC68K this inputs lower data strobe (LDS#). MC68K this inputs system address (A0). REDCAP2, this used should connected VSS. DragonBall, this used should connected VSS. Table 4-8: "Host Interface Mapping," page summary. AB[16:1] 87-99, HIOVDD System address bits 16-1.
HIOVDD
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Table 4-2: Host Interface Descriptions
Name Type Cell RESET# Voltage State Description Input data from system data bus. Generic these pins connected D[15:0]. Generic these pins connected D[15:0]. SH-3/SH-4, these pins connected D[15:0]. MC68K these pins connected D[15:0]. MC68K these pins connected D[31:16] 32bit device (e.g. MC68030) D[15:0] 16-bit device (e.g. MC68340). REDCAP2, these pins connected D[15:0]. DragonBall, these pins connected D[15:0]. Table 4-8: "Host Interface Mapping," page summary. This input multiple functions. Generic this inputs write enable signal lower data byte (WE0#). Generic this inputs write enable signal (WE#) SH-3/SH-4, this inputs write enable signal data byte (WE0#). MC68K this must tied MC68K this inputs size (SIZ0). REDCAP2, this inputs byte enable signal D[7:0] data byte (EB1). DragonBall, this inputs byte enable signal D[7:0] data byte (LWE). Table 4-8: "Host Interface Mapping," page summary. This input multiple functions. Generic this inputs write enable signal upper data byte (WE1#). Generic this inputs byte enable signal high data byte (BHE#). SH-3/SH-4, this inputs write enable signal data byte (WE1#). MC68K this inputs upper data strobe (UDS#). MC68K this inputs data strobe (DS#). REDCAP2, this inputs byte enable signal D[15:8] data byte (EB0). DragonBall, this inputs byte enable signal D[15:8] data byte (UWE). Table 4-8: "Host Interface Mapping," page summary. HIOVDD Chip select input. Table 4-8: "Host Interface Mapping," page summary. This input used select between display buffer register address spaces S1D13706. M/R# high access display buffer access registers. Table 4-8: "Host Interface Mapping," page summary.
DB[15:0]
18-24, 27-35
LB2A
HIOVDD
Hi-Z
WE0#
HIOVDD
WE1#
HIOVDD
M/R#
HIOVDD
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Table 4-2: Host Interface Descriptions
Name Type Cell RESET# Voltage State Description This input multiple functions. Generic this must tied VDD. Generic this must tied VDD. SH-3/SH-4, this inputs start signal (BS#). MC68K this inputs address strobe (AS#). MC68K this inputs address strobe (AS#). REDCAP2, this must tied VDD. DragonBall, this must tied VDD.
HIOVDD
Table 4-8: "Host Interface Mapping," page summary. This input multiple functions. Generic this inputs read command upper data byte (RD1#). Generic this must tied VDD. SH-3/SH-4, this inputs RD/WR# signal. S1D13706 needs this signal early decode cycle. MC68K this inputs R/W# signal. MC68K this inputs R/W# signal. REDCAP2, this inputs signal. DragonBall, this must tied VDD. Table 4-8: "Host Interface Mapping," page summary. This input multiple functions. Generic this inputs read command lower data byte (RD0#). Generic this inputs read command (RD#). SH-3/SH-4, this inputs read signal (RD#). MC68K this must tied VDD. MC68K this inputs size (SIZ1). REDCAP2, this inputs output enable (OE). DragonBall, this inputs output enable (OE). Table 4-8: "Host Interface Mapping," page summary.
RD/WR#
HIOVDD
HIOVDD
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Table 4-2: Host Interface Descriptions
Name Type Cell RESET# Voltage State Description During data transfer, this output driven active force system insert wait states. driven inactive indicate completion data transfer. WAIT# released high impedance state after data transfer complete. active polarity configurable. Table 4-7: "Summary PowerOn/Reset Options," page Generic this outputs wait signal (WAIT#). Generic this outputs wait signal (WAIT#). SH-3 mode, this outputs wait request signal (WAIT#). SH-4 mode, this outputs device ready signal (RDY#). MC68K this outputs data transfer acknowledge signal (DTACK#). MC68K this outputs data transfer size acknowledge (DSACK1#). REDCAP2, this unused (Hi-Z). DragonBall, this outputs data transfer acknowledge signal (DTACK). Table 4-8: "Host Interface Mapping," page summary. RESET# HIOVDD Active input internal registers default state force signals their inactive states.
WAIT#
LB2A
HIOVDD
Hi-Z
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4.3.2 Interface
Table 4-3: Interface Descriptions
Name FPDAT[17:0] Type 74-64, 61-55 Cell LB3P RESET# Voltage State NIOVDD Panel Data bits 17-0. This output multiple functions. Frame Pulse Sharp HR-TFT Epson D-TFD Table 4-9: "LCD Interface Mapping," page summary. This output multiple functions. Line Pulse Sharp HR-TFT Epson D-TFD Table 4-9: "LCD Interface Mapping," page summary. This output multiple functions. Shift Clock Sharp HR-TFT XSCL Epson D-TFD Table 4-9: "LCD Interface Mapping," page summary. This output multiple functions. Display enable (DRDY) panels shift clock (FPSHIFT2) passive with Format interface Epson D-TFD backplane bias signal (MOD) other panels Table 4-9: "LCD Interface Mapping," page summary. This multiple functions. Sharp HR-TFT XINH Epson D-TFD General purpose (GPIO0) Hardware Video Invert Description
FPFRAME
LB3P
NIOVDD
FPLINE
LB3P
NIOVDD
FPSHIFT
LB3P
NIOVDD
DRDY
NIOVDD
GPIO0
LB3M
NIOVDD
Table 4-9: "LCD Interface Mapping," page summary. This multiple functions. Sharp HR-TFT YSCL Epson D-TFD General purpose (GPIO1) Table 4-9: "LCD Interface Mapping," page summary.
GPIO1
LB3M
NIOVDD
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Table 4-3: Interface Descriptions
Name Type Cell RESET# Voltage State Description This multiple functions. Sharp HR-TFT Epson D-TFD General purpose (GPIO2) Table 4-9: "LCD Interface Mapping," page summary. This multiple functions. Sharp HR-TFT Epson D-TFD General purpose (GPIO3) Table 4-9: "LCD Interface Mapping," page summary. This multiple functions. GPIO4 LB3M NIOVDD Epson D-TFD General purpose (GPIO4) Table 4-9: "LCD Interface Mapping," page summary. This multiple functions. GPIO5 LB3M NIOVDD DD_P1 Epson D-TFD General purpose (GPIO5) Table 4-9: "LCD Interface Mapping," page summary. This multiple functions. GPIO6 LB3M NIOVDD YSCLD Epson D-TFD General purpose (GPIO6) Table 4-9: "LCD Interface Mapping," page summary. This output multiple functions. PWMOUT LB3P NIOVDD Clock output General purpose output This output multiple functions. CVOUT LB3P NIOVDD Pulse Output General purpose output
GPIO2
LB3M
NIOVDD
GPIO3
LB3M
NIOVDD
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4.3.3 Clock Input
Table 4-4: Clock Input Descriptions
Name CLKI CLKI2 Type Cell RESET# Voltage State NIOVDD NIOVDD Description Typically used input clock source clock memory clock Typically used input clock source pixel clock
4.3.4 Miscellaneous
Table 4-5: Miscellaneous Descriptions
Name Type Cell RESET# Voltage State Description These inputs used configure S1D13706 Table 4-7: "Summary Power-On/Reset Options," page Note: These pins used configuration S1D13706 must connected directly VSS. General Purpose Output (possibly used controlling power). also used control signal Sharp HR-TFT panel. Test Enable input used production test only (has type pulldown resistor with typical value 3.3V).
CNF[7:0]
78-85
NIOVDD
NIOVDD
TESTEN
NIOVDD
4.3.5 Power Ground
Table 4-6: Power Ground Descriptions
Name HIOVDD Type Cell RESET# Voltage State Description pins associated with host interface pins described Section 4.3.1, "Host Interface" page pins associated with non-host interface pins described Section 4.3.2, "LCD Interface" page Section 4.3.3, "Clock Input" page Section 4.3.4, "Miscellaneous" page Core VDD. pins. pins.
NIOVDD COREVDD
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Summary Configuration Options
These pins used configuration S1D13706 must connected directly NIOVDD VSS. state CNF[6:0] latched rising edge RESET#. Changing state other time effect. Table 4-7: Summary Power-On/Reset Options
S1D13706 Configuration Input Power-On/Reset State (connected NIOVDD) Select host interface follows: CNF4 CNF2 CNF1 CNF0 Host SH-4/SH-3 interface, Endian SH-4/SH-3 interface, Little Endian MC68K Endian Reserved MC68K Endian Reserved Generic Endian Generic Little Endian Reserved Generic Little Endian REDCAP2, Endian Reserved DragonBall (MC68EZ328/MC68VZ328), Endian Reserved Reserved (Connected VSS)
CNF4,CNF[2:0]
Note: host interface 16-bit only. CNF3 CNF5 Configure GPIO pins inputs power-on WAIT# active high CLKI BCLK divide select: CNF[7:6] CNF7 CNF6 CLKI BCLK Divide Ratio Configure GPIO pins outputs power-on (for HR-TFT/D-TFD when selected) WAIT# active
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Host Interface Mapping
Table 4-8: Host Interface Mapping
S1D13706 Name AB[16:1] DB[15:0] M/R# CLKI RD/WR# WE0# WE1# WAIT# RESET# BUSCLK BUSCLK Connected BHE# WAIT# RESET# CKIO RD/WR# WE0# WE1# WAIT#/ RDY# RESET# Connected RD1# RD0# WE0# WE1# WAIT# RESET# Generic Generic Hitachi SH-3 /SH-4 A[16:1]
Motorola MC68K A[16:1] LDS# D[15:0] External Decode R/W# Connected Connected UDS# DTACK# RESET#
Motorola MC68K A[16:1] D[15:0]2
Motorola REDCAP2 A[16:1]
Motorola MC68EZ328/ MC68VZ328 DragonBall A[16:1] D[15:0] CLKO Connected DTACK RESET
A[16:1] D[15:0]
A[16:1] D[15:0]
D[15:0] CSn#
D[15:0]
External Decode
External Decode R/W# SIZ1 SIZ0 DSACK1# RESET#
Connected RESET_OUT
Note these busses used internally S1D13706 should connected target MC68K 32-bit, then these signals should connected D[31:16].
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Interface Mapping
Table 4-9: Interface Mapping
Monochrome Passive Panel Name 4-bit FPFRAME FPLINE FPSHIFT DRDY FPDAT0 FPDAT1 FPDAT2 FPDAT3 FPDAT4 FPDAT5 FPDAT6 FPDAT7 FPDAT8 FPDAT9 FPDAT10 FPDAT11 FPDAT12 FPDAT13 FPDAT14 FPDAT15 FPDAT16 FPDAT17 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 CVOUT PWMOUT driven driven driven driven driven driven driven driven driven driven driven driven driven driven GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 driven driven driven driven driven driven driven driven driven driven GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 driven driven driven driven (R2)2 (B1)2 (G1)2 (R1)2 driven driven driven driven driven driven driven driven driven driven GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 FPSHIFT2 (B5)2 (R5)2 (G4)2 (B3)2 (R3)2 (G2)2 (B1)2 (R1)2 driven driven driven driven driven driven driven driven driven driven GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 Single 8-bit 4-bit Color Passive Panel Single Format 8-bit Format 8-bit FPFRAME FPLINE FPSHIFT (G3)2 (R3)2 (B2)2 (G2)2 (R2)2 (B1)2 (G1)2 (R1)2 driven driven driven driven driven driven driven driven driven driven GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 (R6)2 (G5)2 (B4)2 (R4)2 (B5)2 (R5)2 (G4)2 (B3)2 (G3)2 (B2)2 (R2)2 (G1)2 (R3)2 (G2)2 (B1)2 (R1)2 driven driven GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 driven driven driven driven driven driven driven driven driven GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 DRDY driven driven driven driven driven driven GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 16-Bit 9-bit Others 12-bit 18-bit Color Panel Sharp HRTFT1 18-bit DCLK connect GPIO4 (output only) GPIO5 (output only) GPIO6 (output only)
Epson D-TFD1 18-bit XSCL XINH YSCL DD_P1 YSCLD
(General Purpose Output) CVOUT PWMOUT
Note
GPIO pins must configured outputs (CNF3 RESET#) when HR-TFT D-TFD interface selected. These mappings signal names commonly used each panel type, however signal names differ between panel manufacturers. values shown brackets represent color components mapped corresponding FPDATxx signals first valid edge FPSHIFT. further FPDATxx interface mapping, Section 6.4, "Display Interface" page When HR-TFT interface selected (REG[10h] bits 10), this used control HR-TFT signal. Note this same signal S1D13706 DRDY(MOD) signal used passive panels.
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D.C. Characteristics
Table 5-1: Absolute Maximum Ratings
Symbol Core VOUT TSTG TSOL Parameter Supply Voltage Supply Voltage Input Voltage Output Voltage Storage Temperature Solder Temperature/Time sec. lead Rating Units
Table 5-2: Recommended Operating Conditions
Symbol Core TOPR Parameter Supply Voltage Supply Voltage Supply Voltage Input Voltage Operating Temperature Condition Units
Note
S1D13706 requires that Core Core VDD.
Table 5-3: Electrical Characteristics 3.3V typical
Symbol IDDS Parameter Quiescent Current Input Leakage Current Output Leakage Current High Level Output Voltage Condition Quiescent Conditions -6mA (Type -12mA (Type (Type 12mA (Type LVTTL Level, LVTTL Level, LVTTL Schmitt LVTTL Schmitt LVTTL Schmitt Units
VTVH1
Level Output Voltage High Level Input Voltage Level Input Voltage High Level Input Voltage Level Input Voltage Hysteresis Voltage Pull Down Resistance Input Capacitance Output Capacitance Bi-Directional Capacitance
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A.C. Characteristics
Conditions: 2.0V 3.3V 3.3V -40° Trise Tfall inputs must nsec (10% 90%) 50pF (Bus/MPU Interface) (LCD Panel Interface)
Clock Timing
6.1.1 Input Clocks
Clock Input Waveform
TOSC
Figure 6-1: Clock Input Requirements
Table 6-1: Clock Input Requirements CLKI when CLKI BCLK divide
Symbol fOSC TOSC tPWH tPWL Parameter Input Clock Frequency (CLKI) Input Clock period (CLKI) Input Clock Pulse Width High (CLKI) Input Clock Pulse Width (CLKI) Input Clock Fall Time (10% 90%) Input Clock Rise Time (10% 90%) 1/fOSC 2.0V 1/fOSC 3.3V Units
Note
Maximum internal requirements clocks derived from CLKI must considered when determining frequency CLKI. Section 6.1.2, "Internal Clocks" page internal clock requirements.
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Table 6-2: Clock Input Requirements CLKI when CLKI BCLK divide
Symbol fOSC TOSC tPWH tPWL Parameter Input Clock Frequency (CLKI) Input Clock period (CLKI) Input Clock Pulse Width High (CLKI) Input Clock Pulse Width (CLKI) Input Clock Fall Time (10% 90%) Input Clock Rise Time (10% 90%) 1/fOSC 2.0V 1/fOSC 3.3V Units
Note
Maximum internal requirements clocks derived from CLKI must considered when determining frequency CLKI. Section 6.1.2, "Internal Clocks" page internal clock requirements. Table 6-3: Clock Input Requirements CLKI2
Symbol fOSC TOSC tPWH tPWL Parameter Input Clock Frequency (CLKI2) Input Clock period (CLKI2) Input Clock Pulse Width High (CLKI2) Input Clock Pulse Width (CLKI2) Input Clock Fall Time (10% 90%) Input Clock Rise Time (10% 90%) 1/fOSC 2.0V 1/fOSC 3.3V Units
Note
Maximum internal requirements clocks derived from CLKI2 must considered when determining frequency CLKI2. Section 6.1.2, "Internal Clocks" page internal clock requirements.
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6.1.2 Internal Clocks
Table 6-4: Internal Clock Requirements
Symbol fBCLK fMCLK fPCLK Clock frequency Memory Clock frequency Pixel Clock frequency Parameter 2.0V 3.3V Units
fPWMCLK Clock frequency
Note
further information internal clocks, refer Section "Clocks" page
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Interface Timing
following section includes interface Timing both 2.0V 3.3V. 2.0V timings based Core 2.0V. 3.3V timings based Core 3.3V.
6.2.1 Generic Interface Timing
TCLK A[16:1] M/R# RD0#,RD1# WE0#,WE1#
WAIT# D[15:0](write) D[15:0](read) VALID
Figure 6-2: Generic Interface Timing
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Table 6-5: Generic Interface Timing
Symbol fCLK TCLK Parameter Clock frequency Clock period Clock pulse width high Clock pulse width A[16:1], M/R# setup first rising edge where either RD0#, RD1# WE0#, WE1# A[16:1], M/R# hold from either RD0#, RD1# WE0#, WE1# rising edge setup rising edge hold from either RD0#, RD1# WE0#, WE1# rising edge RD0#, RD1#, WE0#, WE1# asserted MCLK BCLK RD0#, RD1#, WE0#, WE1# asserted MCLK BCLK RD0#, RD1#, WE0#, WE1# asserted MCLK BCLK RD0#, RD1#, WE0#, WE1# asserted MCLK BCLK RD0#, RD1#, WE0#, WE1# setup rising edge Falling edge either RD0#, RD1# WE0#, WE1# WAIT# driven Rising edge either RD0#, RD1# WE0#, WE1# WAIT# high impedance D[15:0] setup third rising edge where WE0#, WE1# (write cycle) (see note D[15:0] hold from WAIT# rising edge (write cycle) RD0#, RD1# falling edge D[15:0] driven (read cycle) WAIT# rising edge D[15:0] valid (read cycle) RD0#, RD1# rising edge D[15:0] high impedance (read cycle) 2.0V 1/fCLK 22.5 22.5 11.5 13.5 17.5 1/fCLK 11.5 13.5 17.5 3.3V Unit TCLK TCLK TCLK TCLK
delay from when data placed until data latched into write buffer.
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6.2.2 Generic Interface Timing (e.g. ISA)
TBUSCLK BUSCLK SA[16:0] M/R#, SBHE# MEMR# MEMW#
IOCHRDY SD[15:0] (write) SD[15:0] (read) VALID
Figure 6-3: Generic Interface Timing
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Table 6-6: Generic Interface Timing
Symbol fBUSCLK TBUSCLK Parameter 2.0V 1/fBUSCLK 11.5 13.5 17.5 3.3V Unit TBUSCLK TBUSCLK TBUSCLK TBUSCLK
Clock frequency Clock period 1/fBUSCLK Clock pulse width high 22.5 Clock pulse width 22.5 SA[16:0], M/R#, SBHE# setup first BUSCLK rising edge where either MEMR# MEMW# SA[16:0], M/R#, SBHE# hold from either MEMR# MEMW# rising edge setup BUSCLK rising edge hold from either MEMR# MEMW# rising edge MEMR#/MEMW# asserted MCLK BCLK MEMR#/MEMW# asserted MCLK BCLK MEMR#/MEMW# asserted MCLK BCLK MEMR#/MEMW# asserted MCLK BCLK MEMR# MEMW# setup BUSCLK rising edge Falling edge either MEMR# MEMW# IOCHRDY driven Rising edge either MEMR# MEMW# IOCHRDY high impedance SD[15:0] setup third BUSCLK rising edge where MEMW# (write cycle) (see note SD[15:0] hold from IOCHRDY rising edge (write cycle) MEMR# falling edge SD[15:0] driven (read cycle) IOCHRDY rising edge SD[15:0] valid (read cycle) Rising edge MEMR# SD[15:0] high impedance (read cycle)
delay from when data placed until data latched into write buffer.
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6.2.3 Hitachi SH-4 Interface Timing
TCKIO CKIO A[16:1], M/R# RD/WR# CSn# WEn# RDY# Hi-Z D[15:0] (write) Hi-Z D[15:0] (read) Hi-Z VALID Hi-Z Hi-Z Hi-Z
Figure 6-4: Hitachi SH-4 Interface Timing
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Table 6-7: Hitachi SH-4 Interface Timing
Symbol fCKIO TCKIO Clock frequency Clock period Clock pulse width Clock pulse width high A[16:1], M/R#, RD/WR# setup CKIO A[16:1], M/R#, RD/WR# hold from CSn# setup hold CSn# setup CSn# high setup CKIO WEn# asserted MCLK BCLK (max. MCLK 50MHz) WEn# asserted MCLK BCLK WEn# asserted MCLK BCLK WEn# asserted MCLK BCLK Falling edge D[15:0] driven (read cycle) Falling edge CSn# RDY# driven high CKIO RDY# CSn# high RDY# high Falling edge CKIO RDY# high impedance D[15:0] setup CKIO after (write cycle) (see note D[15:0] hold (write cycle) RDY# falling edge D[15:0] valid (read cycle) Rising edge D[15:0] high impedance (read cycle) 1/fCKIO 22.5 22.5 11.5 13.5 18.5 Parameter 2.0V 1/fCKIO 11.5 13.5 18.5 3.3V Unit TCKIO TCKIO TCKIO TCKIO
delay from when data placed until data latched into write buffer. Note
Minimum software WAIT state required.
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6.2.4 Hitachi SH-3 Interface Timing
TCKIO CKIO A[16:1], M/R# RD/WR# CSn# WEn# WAIT# Hi-Z D[15:0] (write) Hi-Z D[15:0] (read) Hi-Z VALID Hi-Z Hi-Z Hi-Z
Figure 6-5: Hitachi SH-3 Interface Timing
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Table 6-8: Hitachi SH-3 Interface Timing
Symbol fCKIO TCKIO Clock frequency Clock period Clock pulse width Clock pulse width high A[16:1], M/R#, RD/WR# setup CKIO CSn# high setup CKIO setup hold CSn# setup A[16:1], M/R#, RD/WR# hold from WEn# asserted MCLK BCLK (max. MCLK 50MHz) WEn# asserted MCLK BCLK WEn# asserted MCLK BCLK WEn# asserted MCLK BCLK Falling edge D[15:0] driven (read cycle) Rising edge CSn# WAIT# high impedance Falling edge CSn# WAIT# driven CKIO WAIT# delay D[15:0] setup
Parameter
2.0V 1/fCKIO 22.5 22.5 11.5 13.5 18.5
3.3V 1/fCKIO 11.5 13.5 18.5
Unit TCKIO TCKIO TCKIO TCKIO
CKIO after (write cycle) (see note
D[15:0] hold (write cycle) WAIT# rising edge D[15:0] valid (read cycle) Rising edge D[15:0] high impedance (read cycle)
delay from when data placed until data latched into write buffer. Note
Minimum software WAIT state required.
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6.2.5 Motorola MC68K Interface Timing (e.g. MC68000)
TCLK A[16:1] M/R#
UDS# LDS# R/W# DTACK#
D[15:0](write) D[15:0](read)
VALID
Figure 6-6: Motorola MC68K Interface Timing
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Table 6-9: Motorola MC68K Interface Timing
Symbol fCLK TCLK Clock Frequency Clock period Clock pulse width high Clock pulse width A[16:1], M/R# setup first rising edge where UDS# LDS# A[16:1], M/R# hold from rising edge setup rising edge while CS#, AS#, UDS#/LDS# hold from rising edge asserted MCLK BCLK asserted MCLK BCLK asserted MCLK BCLK asserted MCLK BCLK setup rising edge while CS#, AS#, UDS#/LDS# setup rising edge UDS#/LDS# setup rising edge while CS#, AS#, UDS#/LDS# UDS#/LDS# high setup rising edge First rising edge where DTACK# high impedance R/W# setup rising edge before CS#, AS#, UDS# and/or LDS# R/W# hold from rising edge DTACK# driven high rising edge DTACK# rising edge D[15:0] valid third rising edge where either UDS# LDS# (write cycle) (see note D[15:0] hold from DTACK# falling edge (write cycle) UDS# and/or LDS# D[15:0] driven (read cycle) DTACK# falling edge D[15:0] valid (read cycle) UDS#, LDS# rising edge D[15:0] high impedance (read cycle) 1/fCLK 22.5 22.5 Parameter 2.0V 1/fCLK 3.3V Unit TCLK TCLK TCLK TCLK
delay from when data placed until data latched into write buffer.
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6.2.6 Motorola MC68K Interface Timing (e.g. MC68030)
TCLK A[16:0] M/R#, SIZ[1:0] R/W# DSACK1# D[31:16](write) D[31:16](read) VALID
Figure 6-7: Motorola MC68K Interface Timing
Note
information implementation Motorola Host Interface, Interfacing Motorola MC68030 Microprocessor, document number X31B-G-013-xx.
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Table 6-10: Motorola MC68K Interface Timing
Symbol fCLK TCLK Clock frequency Clock period Clock pulse width high Clock pulse width A[16:0], SIZ[1:0], M/R# setup first rising edge where A[16:0], SIZ[1:0], M/R# hold from rising edge setup rising edge hold from rising edge asserted MCLK BCLK asserted MCLK BCLK asserted MCLK BCLK asserted MCLK BCLK falling edge rising edge rising edge rising edge falling edge rising edge setup rising edge First where DSACK1# high impedance R/W# setup rising edge before R/W# hold from rising edge DSACK1# rising edge rising edge DSACK1# rising edge D[31:16] valid third rising edge where (write cycle) (see note D[31:16] hold from falling edge DSACK1# (write cycle) falling edge D[31:16] driven (read cycle) DSACK1# falling edge D[31:16] valid (read cycle) rising edge D[31:16] invalid/high impedance (read cycle) 1/fCLK 22.5 22.5 Parameter 2.0V 1/fCLK 3.3V Unit TCLK TCLK TCLK TCLK
delay from when data placed until data latched into write buffer.
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6.2.7 Motorola REDCAP2 Interface Timing
TCKO M/R# A[16:1]
(write) D[15:0] (write) (read) D[15:0] (read) Hi-Z Hi-Z
VALID
Hi-Z
VALID
Hi-Z
Note: CS4.
Figure 6-8: Motorola REDCAP2 Interface Timing
Note
further information implementing REDCAP2 microprocessor, Interfacing Motorola REDCAP2 with Integrated MCU, document number X31B-G-013-xx.
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Table 6-11: Motorola REDCAP2 Interface Timing
Symbol fCKO TCKO t13a t13b t13c t13d Clock frequency Clock period Clock pulse width Clock pulse width high A[16:1], M/R#, R/W, setup rising edge A[16:1], M/R#, R/W, hold from rising edge asserted MCLK BCLK asserted MCLK BCLK asserted MCLK BCLK asserted MCLK BCLK EB0, asserted rising edge (write cycle) EB0, de-asserted rising edge (write cycle) D[15:0] input setup rising edge after asserted (write cycle) (see note D[15:0] input hold from rising edge after asserted (write cycle) EB0, setup rising edge (read cycle) EB0, hold rising edge (read cycle) D[15:0] output delay from EB0, falling edge (read cycle) rising edge after asserted D[15:0] valid MCLK BCLK (read cycle) rising edge after asserted D[15:0] valid MCLK BCLK (read cycle) rising edge after asserted D[15:0] valid MCLK BCLK (read cycle) rising edge after asserted D[15:0] valid MCLK BCLK (read cycle) rising edge D[15:0] output Hi-Z (read cycle) 1/fCKO 4.5CKO 7CKO 8.5CKO 9CKO Parameter 2.0V 1/fCKO 4.5CKO 6.5CKO 9.5CKO 11.5CKO 3.3V Units TCKO TCKO TCKO TCKO
delay from when data placed until data latched into write buffer.
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6.2.8 Motorola DragonBall Interface Timing with DTACK (e.g. MC68EZ328/MC68VZ328)
TCLKO CLKO A[16:1] UWE/LWE (write) (read)
D[15:0] (write) Hi-Z
Hi-Z
D[15:0] (read) Hi-Z VALID
Hi-Z
DTACK
Figure 6-9: Motorola DragonBall Interface with DTACK Timing
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Table 6-12: Motorola DragonBall Interface with DTACK Timing
MC68EZ328 Symbol fCLKO TCLKO Parameter Clock frequency Clock period Clock pulse width high Clock pulse width A[16:1] setup CLKO when either UWE/LWE A[16:1] hold from rising edge asserted MCLK BCLK asserted MCLK BCLK asserted MCLK BCLK asserted MCLK BCLK setup CLKO rising edge rising edge CLKO rising edge UWE/LWE falling edge CLKO rising edge UWE/LWE rising edge rising edge falling edge CLKO rising edge hold from rising edge D[15:0] setup CLKO when CSX, UWE/LWE asserted (write cycle) (see note D[15:0] hold from rising edge (write cycle) Falling edge D[15:0] driven (read cycle) CLKO rising edge D[15:0] output Hi-Z (read cycle) falling edge DTACK driven high DTACK falling edge D[15:0] valid (read cycle) high DTACK high CLKO rising edge DTACK Hi-Z
1/fCLKO
MC68VZ328 2.0V
1/fCLKO
2.0V
3.3V
1/fCLKO
3.3V
1/fCLKO
Unit TCLKO TCLKO TCLKO TCLKO
28.1 28.1
28.1 28.1
22.5 22.5
13.5 13.5
delay from when data placed until data latched into write buffer.
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6.2.9 Motorola DragonBall Interface Timing DTACK (e.g. MC68EZ328/MC68VZ328)
TCLKO CLKO A[16:1] UWE/LWE (write) (read)
D[15:0] (write) Hi-Z
Hi-Z
D[15:0] (read) Hi-Z VALID
Hi-Z
Figure 6-10: Motorola DragonBall Interface without DTACK# Timing
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Table 6-13: Motorola DragonBall Interface without DTACK Timing
MC68EZ328 Symbol fCLKO Parameter Clock frequency
1/fCLKO
MC68VZ328 2.0V
1/fCLKO
2.0V
3.3V
1/fCLKO
3.3V
1/fCLKO
Unit TCLKO
TCLKO Clock period Clock pulse width high Clock pulse width A[16:1] setup CLKO when either UWE/LWE A[16:1] hold from rising edge asserted MCLK BCLK (CPU wait state register should programmed wait states) asserted MCLK BCLK (CPU wait state register should programmed wait states) asserted MCLK BCLK (CPU wait state register should programmed wait states) asserted MCLK BCLK (CPU wait state register should programmed wait states) setup CLKO rising edge rising edge setup CLKO rising edge UWE/LWE setup CLKO rising edge UWE/LWE rising edge rising edge setup CLKO rising edge hold from rising edge D[15:0] setup CLKO after CSX, UWE/LWE asserted (write cycle) (see note rising edge D[15:0] output Hi-Z (write cycle) Falling edge D[15:0] driven (read cycle) CLKO rising edge after asserted D[15:0] valid MCLK BCLK (read cycle) CLKO rising edge after asserted D[15:0] valid MCLK BCLK (read cycle) CLKO rising edge after asserted D[15:0] valid MCLK BCLK (read cycle) CLKO rising edge after asserted D[15:0] valid MCLK BCLK (read cycle) CLKO rising edge D[15:0] output Hi-Z (read cycle)
28.1 28.1
28.1 28.1
22.5 22.5
13.6 13.6
TCLKO
Note
Note
TCLKO
t15a
Note
Note
5.5TCLKO
TCLKO
5.5TCLKO
5.5TCLKO
5.5TCLKO
t15b
8TCLKO
8.5TCLKO
8TCLKO
8.5TCLKO
t15c
9.5TCLKO
10.5TCLKO
9.5TCLKO
10.5TCLKO
t15d
13TCLKO
14.5TCLKO
13TCLKO
14.5TCLKO
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MC68EZ328 cannot support MCLK BCLK MCLK BCLK settings without DTACK. delay from when data placed until data latched into write buffer.
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Power Sequencing
6.3.1 Passive/TFT Power-On Sequence
GPO* Power Save Mode Enable** (REG[A0h] Signals***
recommended general purpose output control bias power. **The power-on sequence activated programming Power Save Mode Enable (REG[A0h] ***LCD Signals include: FPDAT[17:0], FPSHIFT, FPLINE, FPFRAME, DRDY.
Figure 6-11: Passive/TFT Power-On Sequence Timing
Table 6-14: Passive/TFT Power-On Sequence Timing
Symbol Parameter signals active bias active Power Save Mode disabled signals active Note Note Units
controlled software must determined from bias power supply delay requirements panel connected. Note
HR-TFT Power-On/Off sequence information, Connecting Sharp HR-TFT Panels, document number X31B-G-011-xx. D-TFD Power-On/Off sequence information, Connecting Epson D-TFD Panels, document number X31B-G-012-xx.
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6.3.2 Passive/TFT Power-Off Sequence
GPO* Power Save Mode Enable** (REG[A0h] Signals***
recommended general purpose output control bias power. **The power-off sequence activated programming Power Save Mode Enable (REG[A0h] ***LCD Signals include: FPDAT[17:0], FPSHIFT, FPLINE, FPFRAME, DRDY.
Figure 6-12: Passive/TFT Power-Off Sequence Timing
Table 6-15: Passive/TFT Power-Off Sequence Timing
Symbol Parameter bias deactivated signals inactive Power Save Mode enabled signals Note Note Units
controlled software must determined from bias power supply delay requirements panel connected.
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Display Interface
timing parameters required drive flat panel display shown below. Timing details each supported panel type provided remainder this section.
HDPS
VDPS
Figure 6-13: Panel Timing Parameters
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Table 6-16: Panel Timing Parameter Definition Register Summary
Symbol HDP1 HDPS VDPS Description Horizontal Total Horizontal Display Period1 Derived From Units ((REG[12h] bits 6-0) ((REG[14h] bits 6-0) panels: ((REG[17h] bits 1-0, REG[16h] bits 7-0) Horizontal Display Period Start Position panels: ((REG[17h] bits 1-0, REG[16h] bits 7-0) FPLINE Pulse Start Position (REG[23h] bits 1-0, REG[22h] bits 7-0) FPLINE Pulse Width (REG[20h] bits 6-0) Vertical Total (REG[19h] bits 1-0, REG[18h] bits 7-0) Vertical Display Period (REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) Vertical Display Period Start Position REG[1Fh] bits 1-0, REG[1Eh] bits Lines (HT) FPFRAME Pulse Start Position REG[27h] bits 1-0, REG[26h] bits FPFRAME Pulse Width (REG[24h] bits 6-0)
passive panels, must minimum pixels must increased multiples panels, must minimum pixels must increased multiples following formulas must valid panel timings: HDPS VDPS
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6.4.1 Generic Panel Timing
Frame) FPFRAME FPLINE MOD1(DRDY) FPDAT[17:0]
Line)
FPLINE FPSHIFT 1PCLK MOD2(DRDY) HDPS FPDAT[17:0]
Figure 6-14: Generic Panel Timing
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VDPS HDPS
Vertical Total [(REG[19h] bits 1-0, REG[18h] bits 7-0) lines FPFRAME Pulse Start Position lines, because (REG[27h] bits 1-0, REG[26h] bits 7-0) FPFRAME Pulse Width [(REG[24h] bits 2-0) lines Vertical Display Period Start Position lines, because (REG[1Fh] bits 1-0, REG[1Eh] bits 7-0) Vertical Display Period [(REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) lines Horizontal Total [((REG[12h] bits 6-0) pixels FPLINE Pulse Start Position [(REG[23h] bits 1-0, REG[22h] bits 7-0) pixels FPLINE Pulse Width [(REG[20h] bits 6-0) pixels Horizontal Display Period Start Position pixels, because (REG[17h] bits 1-0, REG[16h] bits 7-0) Horizontal Display Period [((REG[14h] bits 6-0) pixels
*For passive panels, must minimum pixels must increased multiples *HPS must comply with following formula: *Panel Type Bits (REG[10h] bits 1-0) (STN) *FPFRAME Pulse Polarity (REG[24h] (active high) *FPLINE Polarity (REG[20h] (active high) *MOD1 signal when (REG[11h] bits 5-0) (MOD toggles every FPFRAME) *MOD2 signal when (REG[11h] bits 5-0) (MOD toggles every FPLINE)
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6.4.2 Single Monochrome 4-Bit Panel Timing
VNDP
FPFRAME FPLINE DRDY (MOD) FPDAT[7:4]
Invalid LINE1 LINE2 LINE3 LINE4 LINE239 LINE240 Invalid LINE1 LINE2
FPLINE DRDY (MOD)
HNDP
FPSHIFT FPDAT7 FPDAT6 FPDAT5 FPDAT4
Invalid Invalid Invalid Invalid 1-317 1-318 1-319 1-320 Invalid Invalid Invalid Invalid
Diagram drawn with FPLINE vertical blank period Example timing 320x240 panel
Figure 6-15: Single Monochrome 4-Bit Panel Timing
VNDP Vertical Display Period (REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) Lines Vertical Non-Display Period (REG[19h] bits 1-0, REG[18h] bits 7-0) (REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) Lines Horizontal Display Period ((REG[14h] bits 6-0) Horizontal Non-Display Period (((REG[12h] bits 6-0) 8Ts) (((REG[14h] bits 6-0) 8Ts)
HNDP
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Sync Timing FPFRAME
FPLINE DRDY (MOD) Data Timing FPLINE FPSHIFT FPDAT[7:4]
Figure 6-16: Single Monochrome 4-Bit Panel A.C. Timing
Table 6-17: Single Monochrome 4-Bit Panel A.C. Timing
Symbol Parameter FPFRAME setup FPLINE falling edge FPFRAME hold from FPLINE falling edge FPLINE period FPLINE pulse width transition FPLINE rising edge FPSHIFT falling edge FPLINE rising edge FPSHIFT falling edge FPLINE falling edge FPLINE falling edge FPSHIFT falling edge FPSHIFT period FPSHIFT pulse width FPSHIFT pulse width high FPDAT[7:4] setup FPSHIFT falling edge FPDAT[7:4] hold FPSHIFT falling edge FPLINE falling edge FPSHIFT rising edge note note note note note note note Units (note
t1min t2min t3min t4min t5min t6min t14min
pixel clock period t4min t3min (HPS t4min) (HDP HDPS) negative t3min HDPS (HPS t4min), negative t3min
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6.4.3 Single Monochrome 8-Bit Panel Timing
VNDP
FPFRAME FPLINE DRDY (MOD) FPDAT[7:0]
Invalid LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 Invalid LINE1 LINE2
FPLINE DRDY (MOD)
HNDP
FPSHIFT FPDAT7 FPDAT6 FPDAT5 FPDAT4 FPDAT3 FPDAT2 FPDAT1 FPDAT0
Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid 1-10 1-11 1-12 1-13 1-14 1-15 1-16 1-633 1-634 1-635 1-636 1-637 1-638 1-639 1-640 Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid
Diagram drawn with FPLINE vertical blank period Example timing 640x480 panel
Figure 6-17: Single Monochrome 8-Bit Panel Timing
VNDP Vertical Display Period (REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) Lines Vertical Non-Display Period (REG[19h] bits 1-0, REG[18h] bits 7-0) (REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) Lines Horizontal Display Period ((REG[14h] bits 6-0) Horizontal Non-Display Period (((REG[12h] bits 6-0) 8Ts) (((REG[14h] bits 6-0) 8Ts)
HNDP
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Sync Timing FPFRAME
FPLINE DRDY (MOD) Data Timing FPLINE FPSHIFT FPDAT[7:0]
Figure 6-18: Single Monochrome 8-Bit Panel A.C. Timing
Table 6-18: Single Monochrome 8-Bit Panel A.C. Timing
Symbol Parameter FPFRAME setup FPLINE falling edge FPFRAME hold from FPLINE falling edge FPLINE period FPLINE pulse width transition FPLINE rising edge FPSHIFT falling edge FPLINE rising edge FPSHIFT falling edge FPLINE falling edge FPLINE falling edge FPSHIFT falling edge FPSHIFT period FPSHIFT pulse width FPSHIFT pulse width high FPDAT[7:0] setup FPSHIFT falling edge FPDAT[7:0] hold FPSHIFT falling edge FPLINE falling edge FPSHIFT rising edge note note note note note note note Units (note
t1min t2min t3min t4min t5min t6min t14min
pixel clock period t4min t3min (HPS t4min) (HDP HDPS) negative t3min HDPS (HPS t4min), negative t3min
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6.4.4 Single Color 4-Bit Panel Timing
VNDP
FPFRAME FPLINE DRDY (MOD) FPDAT[7:4]
Invalid LINE1 LINE2 LINE3 LINE4 LINE239 LINE240 Invalid LINE1 LINE2
FPLINE DRDY (MOD)
.5Ts .5Ts .5Ts .5Ts .5Ts .5Ts .5Ts .5Ts .5Ts 2.5Ts .5Ts .5Ts .5Ts .5Ts
HNDP .5Ts
FPSHIFT
Invalid Invalid Invalid Invalid
.5Ts
.5Ts
.5Ts
.5Ts
FPDAT7 FPDAT6 FPDAT5
Notes:
1-R1 1-G1 1-B1 1-R2
1-G2 1-B2 1-R3 1-G3
1-B3 1-R4 1-G4 1-B4
1-B319 1-R320 1-G320 1-B320
Invalid Invalid Invalid Invalid
FPDAT4
FPSHIFT uses extended states order process pixels FPSHIFT clocks Pixel clock period (PCLK) Diagram drawn with FPLINE vertical blank period Example timing 320x240 panel
Figure 6-19: Single Color 4-Bit Panel Timing
VNDP Vertical Display Period (REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) Lines Vertical Non-Display Period (REG[19h] bits 1-0, REG[18h] bits 7-0) (REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) Lines Horizontal Display Period ((REG[14h] bits 6-0) Horizontal Non-Display Period (((REG[12h] bits 6-0) 8Ts) (((REG[14h] bits 6-0) 8Ts)
HNDP
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Sync Timing FPFRAME
FPLINE DRDY (MOD) Data Timing FPLINE FPSHIFT FPDAT[7:4]
Figure 6-20: Single Color 4-Bit Panel A.C. Timing
Table 6-19: Single Color 4-Bit Panel A.C. Timing
Symbol Parameter FPFRAME setup FPLINE falling edge FPFRAME hold from FPLINE falling edge FPLINE period FPLINE pulse width transition FPLINE rising edge FPSHIFT falling edge FPLINE rising edge FPSHIFT falling edge FPLINE falling edge FPLINE falling edge FPSHIFT falling edge FPSHIFT period FPSHIFT pulse width FPSHIFT pulse width high FPDAT[7:4] setup FPSHIFT falling edge FPDAT[7:4] hold FPSHIFT falling edge FPLINE falling edge FPSHIFT rising edge note note note note note note note Units (note
t1min t2min t3min t4min t5min t6min t14min
pixel clock period t4min t3min (HPS t4min) (HDP HDPS) 1.5), negative t3min HDPS (HPS t4min) negative t3min
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6.4.5 Single Color 8-Bit Panel Timing (Format
VNDP
FPFRAME FPLINE FPDAT[7:0]
Invalid
LINE1
LINE2
LINE3
LINE4
LINE239
LINE240
Invalid
LINE1
LINE2
FPLINE
HNDP
1R316 1B316 1G317 1R318 1B318 1G319 1R320 1B320
FPSHIFT FPSHIFT2
Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid
FPDAT7 FPDAT6 FPDAT5 FPDAT4 FPDAT3 FPDAT2 FPDAT1 FPDAT0
Notes:
Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid
1-R1
1-G1
1-G6
1-B6
1-B11
1-R12
1-B1
1-R2
1-R7
1-G7
1-G12
1-B12
1-G2
1-B2
1-B7
1-R8
1-R13
1-G13
1-R3
1-G3
1-G8
1-B8
1-B13
1-R14
1-B3
1-R4
1-R9
1-G9
1-G14
1-B14
1-G4
1-B4
1-B9
1-R10
1-R15
1-G15
1-R5
1-G5
1-G10
1-B10
1-B15
1-R16
1-B5
1-R6
1-R11
1-G11
1-G16
1-B16
duty cycle FPSHIFT changes order process pixels FPSHIFT/FPSHIFT2 rising edges Pixel clock period (PCLK) Diagram drawn with FPLINE vertical blank period Example timing 320x240 panel
Figure 6-21: Single Color 8-Bit Panel Timing (Format
VNDP Vertical Display Period (REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) Lines Vertical Non-Display Period (REG[19h] bits 1-0, REG[18h] bits 7-0) (REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) Lines Horizontal Display Period ((REG[14h] bits 6-0) Horizontal Non-Display Period (((REG[12h] bits 6-0) 8Ts) (((REG[14h] bits 6-0) 8Ts)
HNDP
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Sync Timing FPFRAME
FPLINE Data Timing
FPLINE FPSHIFT FPSHIFT2
FPDAT[7:0]
Figure 6-22: Single Color 8-Bit Panel A.C. Timing (Format
Table 6-20: Single Color 8-Bit Panel A.C. Timing (Format
Symbol Parameter FPFRAME setup FPLINE falling edge FPFRAME hold from FPLINE falling edge FPLINE period FPLINE pulse width FPSHIFT falling edge FPLINE rising edge FPSHIFT2 falling edge FPLINE rising edge FPSHIFT falling edge FPLINE falling edge FPSHIFT2 falling edge FPLINE falling edge FPLINE falling edge FPSHIFT rising, FPSHIFT2 falling edge FPSHIFT2, FPSHIFT period FPSHIFT2, FPSHIFT pulse width FPSHIFT2, FPSHIFT pulse width high FPDAT[7:0] setup FPSHIFT2, FPSHIFT falling edge FPDAT[7:0] hold from FPSHIFT2, FPSHIFT falling edge FPLINE falling edge FPSHIFT rising edge note note note note note note note Units (note
t1min t2min t3min t4min t6amin t6bmin t14min
pixel clock period t4min t3min (HPS t4min) (HDP HDPS), negative t3min (HDP HDPS) negative t3min HDPS (HPS t4min), negative t3min
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6.4.6 Single Color 8-Bit Panel Timing (Format
VNDP
FPFRAME FPLINE DRDY (MOD) FPDAT[7:0]
Invalid LINE1 LINE2 LINE3 LINE4 LINE239 LINE240 Invalid LINE1 LINE2
FPLINE DRDY (MOD)
HNDP 1-G318 1-B318 1-R319 1-G319 1-B319 1-R320 1-G320 1-B320 Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid
FPSHIFT FPDAT7 FPDAT6 FPDAT5 FPDAT4 FPDAT3 FPDAT2 FPDAT1 FPDAT0
Notes:
Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid
1-R1 1-G1 1-B1 1-R2 1-G2 1-B2 1-R3 1-G3
1-B3 1-R4 1-G4 1-B4 1-R5 1-B5 1-R6
1-G6 1-B6 1-R7 1-G7 1-B7 1-R8 1-G8 1-B8
duty cycle FPSHIFT changes order process pixels FPSHIFT rising clocks Pixel clock period (PCLK) Diagram drawn with FPLINE vertical blank period Example timing 320x240 panel
Figure 6-23: Single Color 8-Bit Panel Timing (Format
VNDP Vertical Display Period (REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) Lines Vertical Non-Display Period (REG[19h] bits 1-0, REG[18h] bits 7-0) (REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) Lines Horizontal Display Period ((REG[14h] bits 6-0) Horizontal Non-Display Period (((REG[12h] bits 6-0) 8Ts) (((REG[14h] bits 6-0) 8Ts)
HNDP
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Sync Timing FPFRAME
FPLINE DRDY (MOD) Data Timing FPLINE FPSHIFT FPDAT[7:0]
Figure 6-24: Single Color 8-Bit Panel A.C. Timing (Format
Table 6-21: Single Color 8-Bit Panel A.C. Timing (Format
Symbol Parameter FPFRAME setup FPLINE falling edge FPFRAME hold from FPLINE falling edge FPLINE period FPLINE pulse width transition FPLINE rising edge FPSHIFT falling edge FPLINE rising edge FPSHIFT falling edge FPLINE falling edge FPLINE falling edge FPSHIFT falling edge FPSHIFT period FPSHIFT pulse width FPSHIFT pulse width high FPDAT[7:0] setup FPSHIFT falling edge FPDAT[7:0] hold FPSHIFT falling edge FPLINE falling edge FPSHIFT rising edge note note note note note note note Units (note
t1min t2min t3min t4min t5min t6min t14min
pixel clock period t4min t3min (HPS t4min) (HDP HDPS) negative t3min HDPS (HPS t4min), negative t3min
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6.4.7 Single Color 16-Bit Panel Timing
VNDP
FPFRAME FPLINE DRDY (MOD) FPDAT[15:0]
Invalid
LINE1
LINE2
LINE3
LINE4
LINE479
LINE480
Invalid
LINE1
LINE2
FPLINE DRDY (MOD)
HNDP 1-G635 1-G636 1-R637 1-B637 1-G638 1-R639 1-B639 1-G640 1-R636 1-B636 1-G637 1-R638 1-B638 1-G639 1-R640 1-B640
FPSHIFT FPDAT15 FPDAT14 FPDAT13 FPDAT12 FPDAT7 FPDAT6 FPDAT5 FPDAT4 FPDAT11 FPDAT10 FPDAT9 FPDAT8 FPDAT3 FPDAT2 FPDAT1 FPDAT0
Notes:
Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid
1-R1 1-B1 1-G2 1-R3 1-B3 1-G4 1-R5 1-B5 1-G1 1-R2 1-B2 1-G3 1-R4 1-B4 1-G5 1-R6
1-G6 1-B11 1-R7 1-B7 1-G8 1-R9 1-B9 1-G10 1-R11 1-B6 1-G7 1-R8 1-B8 1-G9 1-R10 1-B10 1-G11 1-G12 1-R13 1-B13 1-G14 1-R15 1-B15 1-G16 1-R12 1-B12 1-G13 1-R14 1-B14 1-G15 1-R16 1-B16
Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid
duty cycle FPSHIFT changes order process pixels FPSHIFT rising clocks Pixel clock period (PCLK) Diagram drawn with FPLINE vertical blank period Example timing 640x480 panel
Figure 6-25: Single Color 16-Bit Panel Timing
VNDP Vertical Display Period (REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) Lines Vertical Non-Display Period (REG[19h] bits 1-0, REG[18h] bits 7-0) (REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) Lines Horizontal Display Period ((REG[14h] bits 6-0) Horizontal Non-Display Period (((REG[12h] bits 6-0) 8Ts) (((REG[14h] bits 6-0) 8Ts)
HNDP
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Sync Timing FPFRAME
FPLINE DRDY (MOD) Data Timing FPLINE FPSHIFT FPDAT[15:0]
Figure 6-26: Single Color 16-Bit Panel A.C. Timing
Table 6-22: Single Color 16-Bit Panel A.C. Timing
Symbol Parameter FPFRAME setup FPLINE falling edge FPFRAME hold from FPLINE falling edge FPLINE period FPLINE pulse width transition FPLINE rising edge FPSHIFT falling edge FPLINE rising edge FPSHIFT falling edge FPLINE falling edge FPLINE falling edge FPSHIFT falling edge FPSHIFT period FPSHIFT pulse width FPSHIFT pulse width high FPDAT[15:0] setup FPSHIFT rising edge FPDAT[15:0] hold FPSHIFT rising edge FPLINE falling edge FPSHIFT rising edge note note note note note note note Units (note
t1min t2min t3min t4min t5min t6min t14min
pixel clock period t4min t3min (HPS t4min) (HDP HDPS) negative t3min HDPS (HPS t4min), negative t3min
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6.4.8 Generic Panel Timing
Frame) FPFRAME VDPS FPLINE
DRDY FPDAT[17:0]
Line) FPLINE FPSHIFT DRDY HDPS FPDAT[17:0] invalid invalid
Figure 6-27: Generic Panel Timing
VDPS HDPS Vertical Total FPFRAME Pulse Start Position FPFRAME Pulse Width Vertical Display Period Start Position Vertical Display Period Horizontal Total FPLINE Pulse Start Position FPLINE Pulse Width Horizontal Display Period Start Position Horizontal Display Period [(REG[19h] bits 1-0, REG[18h] bits 7-0) lines (REG[27h] bits 1-0, REG[26h] bits 7-0) lines [(REG[24h] bits 2-0) lines (REG[1Fh] bits 1-0, REG[1Eh] bits 7-0) lines [(REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) lines [((REG[12h] bits 6-0) pixels [(REG[23h] bits 1-0, REG[22h] bits 7-0) pixels [(REG[20h] bits 6-0) pixels [(REG[17h] bits 1-0, REG[16h] bits 7-0) pixels [((REG[14h] bits 6-0) pixels
*For panels, must minimum pixels must increased multiples *Panel Type Bits (REG[10h] bits 1-0) (TFT) *FPLINE Pulse Polarity (REG[24h] (active low) *FPFRAME Polarity (REG[20h] (active low)
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6.4.9 9/12/18-Bit Panel Timing
VNDP2 VNDP1
FPFRAME FPLINE FPDAT[17:0] DRDY
LINE240 LINE1 LINE480
FPLINE
HNDP1 HNDP2
FPSHIFT DRDY
FPDAT[17:0]
invalid
1-320
invalid
Note: DRDY used indicate first pixel Example Timing 18-bit 320x240 panel
Figure 6-28: 18-Bit Panel Timing
VNDP Vertical Display Period Lines Vertical Non-Display Period VNDP1 VNDP2 Lines Vertical Non-Display Period VNDP VNDP2 Lines Vertical Non-Display Period VDPS Lines Horizontal Display Period Horizontal Non-Display Period HNDP1 HNDP2 Horizontal Non-Display Period HDPS Horizontal Non-Display Period (HDP HDPS)
VNDP1 VNDP2 HNDP
negative
HNDP1 HNDP2
negative negative
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FPFRAME FPLINE
FPLINE DRDY FPSHIFT
FPDAT[17:0] invalid invalid
Note: DRDY used indicate first pixel
Figure 6-29: A.C. Timing
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Table 6-23: A.C. Timing
Symbol Parameter FPFRAME cycle time FPFRAME pulse width FPFRAME falling edge FPLINE falling edge phase difference FPLINE cycle time FPLINE pulse width FPLINE Falling edge DRDY active DRDY pulse width DRDY falling edge FPLINE falling edge FPSHIFT period FPSHIFT pulse width high FPSHIFT pulse width FPLINE setup FPSHIFT falling edge DRDY FPSHIFT falling edge setup time DRDY hold from FPSHIFT falling edge Data setup FPSHIFT falling edge Data hold from FPSHIFT falling edge note note Units Lines Lines (note
t6min t8min
pixel clock period HDPS (HDP HDPS)
negative negative
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6.4.10 160x160 Sharp `Direct' HR-TFT Panel Timing (e.g. LQ031B1DDxx)
FPFRAME (SPS) FPLINE (LP) FPLINE (LP) FPSHIFT (CLK) FPDAT[17:0] GPIO3 (SPL) GPIO1 (CLS) GPIO0 (PS) D160
GPIO2 (REV)
Figure 6-30: 160x160 Sharp `Direct' HR-TFT Panel Horizontal Timing
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Table 6-24: 160x160 Sharp `Direct' HR-TFT Horizontal Timing
Symbol Parameter FPLINE start position Horizontal total period FPLINE width FPSHIFT period Data setup FPSHIFT rising edge Data hold from FPSHIFT rising edge Horizontal display start position Horizontal display period FPLINE rising edge GPIO3 rising edge GPIO3 pulse width GPIO1(GPIO0) pulse width GPIO1 rising edge (GPIO0 falling edge) FPLINE rise edge GPIO2 toggle edge FPLINE rise edge Units (note
t1typ t2typ t3typ t7typ t8typ
pixel clock period (REG[22h] bits 7-0) ((REG[12h] bits 6-0) (REG[20h] bits 6-0) ((REG[16h] bits 7-0) ((REG[22h] bits 7-0) ((REG[14h] bits 6-0)
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FPDAT[17:0] FPFRAME (SPS) GPIO1 (CLS) GPIO0 (PS) FPLINE (LP) FPSHIFT (CLK) GPIO1 (CLS) GPIO0 (PS)
LINE1 LINE2
LINE160
Figure 6-31: 160x160 Sharp `Direct' HR-TFT Panel Vertical Timing
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Table 6-25: 160x160 Sharp `Direct' HR-TFT Panel Vertical Timing
Symbol Parameter Vertical total period Vertical display start position Vertical display period Vertical sync pulse width FPFRAME falling edge GPIO1 alternate timing start GPIO1 alternate timing period FPFRAME falling edge GPIO0 alternate timing start GPIO0 alternate timing period GPIO1 first pulse rising edge FPLINE rising edge GPIO1 first pulse width GPIO1 first pulse falling edge second pulse rising edge GPIO1 second pulse width GPIO0 falling edge FPLINE rising edge GPIO0 pulse width Units Lines Lines Lines Lines Lines Lines Lines Lines (note
pixel clock period
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6.4.11 320x240 Sharp `Direct' HR-TFT Panel Timing (e.g. LQ039Q2DS01)
FPFRAME (SPS) FPLINE (LP) FPLINE (LP) FPSHIFT (CLK) FPDAT[17:0] GPIO3 (SPL) GPIO1 (CLS) GPIO0 (PS) D320
GPIO2 (REV)
Figure 6-32: 320x240 Sharp `Direct' HR-TFT Panel Horizontal Timing
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Table 6-26: 320x240 Sharp `Direct' HR-TFT Panel Horizontal Timing
Symbol Parameter FPLINE start position Horizontal total period FPLINE width FPSHIFT period Data setup FPSHIFT rising edge Data hold from FPSHIFT rising edge Horizontal display start position Horizontal display period FPLINE rising edge GPIO3 rising edge GPIO3 pulse width GPIO1(GPIO0) pulse width GPIO1 rising edge (GPIO0 falling edge) FPLINE rise edge GPIO2 toggle edge FPLINE rise edge Units (note
t1typ t2typ t3typ t7typ t8typ
pixel clock period (REG[22h] bits 7-0) ((REG[12h] bits 6-0) (REG[20h] bits 6-0) ((REG[16h] bits 7-0) ((REG[22h] bits 7-0) ((REG[14h] bits 6-0)
FPDAT[17:0] FPFRAME (SPS)
LINE1 LINE2
LINE240
Figure 6-33: 320x240 Sharp `Direct' HR-TFT Panel Vertical Timing
Table 6-27: 320x240 Sharp `Direct' HR-TFT Panel Vertical Timing
Symbol Parameter Vertical total period Vertical display start position Vertical display period Vertical sync pulse width Units Lines Lines Lines Lines
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6.4.12 160x240 Epson D-TFD Panel Timing (e.g. LF26SCR)
FPLINE (LP) FPSHIFT (XSCL) FPDAT[17:0] (R,G,B) GPIO4 (RES) GPIO1 (YSCL) GPIO0 (XINH) GPIO6 (YSCLD) GPIO2 (FR) GPIO3 (FRS) GPIO5 (DD_P1)
Figure 6-34: 160x240 Epson D-TFD Panel Horizontal Timing
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Table 6-28: 160x240 Epson D-TFD Panel Horizontal Timing
Symbol Parameter FPLINE pulse width FPLINE falling edge FPSHIFT start position FPSHIFT active period FPSHIFT start first data Horizontal display period Last data FPSHIFT inactive FPLINE falling edge GPIO4 first pulse falling edge Horizontal total period GPIO4 first pulse falling edge second pulse falling edge GPIO4 pulse width GPIO1 pulse width GPIO1 period GPIO0 pulse width GPIO6 pulse width GPIO6 rising edge GPIO0 falling edge GPIO2 toggle GPIO3 toggle GPIO5 pulse width 100) Units (note
pixel clock period
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GPIO4 (RES) DRDY (GCP)
Data Register (REG[2Ch])
bit7
bit0 bit7 Index
bit7
Index
Index
Figure 6-35: 160x240 Epson D-TFD Panel Horizontal Timing
Table 6-29: 160x240 Epson D-TFD Panel Horizontal Timing
Symbol Parameter Half horizontal total period clock period Units (note
pixel clock period
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Vertical Total 250HT FPFRAME (DY) GPIO1 (YSCL) GPIO0 (XINH) FPDAT[17:0] (R,G,B) line1 line2
GPIO2 (FR) (odd frame)
GPIO2 (FR) (even frame)
Figure 6-36: 160x240 Epson D-TFD Panel Vertical Timing Table 6-30: 160x240 Epson D-TFD Panel Vertical Timing
Symbol FPFRAME pulse width Horizontal total period Vertical display start Parameter Units (note
pixel clock period
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6.4.13 320x240 Epson D-TFD Panel Timing (e.g. LF37SQR)
FPLINE (LP) FPSHIFT (XSCL) FPDAT[17:0] (R,G,B) GPIO4 (RES) GPIO1 (YSCL) GPIO0 (XINH) GPIO6 (YSCLD) GPIO2 (FR) GPIO3 (FRS) GPIO5 (DD_P1)
Figure 6-37: 320x240 Epson D-TFD Panel Horizontal Timing
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Table 6-31: 320x240 Epson D-TFD Panel Horizontal Timing
Symbol Parameter FPLINE pulse width FPLINE falling edge FPSHIFT start position FPSHIFT active period FPSHIFT start first data Horizontal display period Last data FPSHIFT inactive FPLINE falling edge GPIO4 first pulse falling edge Horizontal total period GPIO4 first pulse falling edge second pulse falling edge GPIO4 pulse width GPIO1 pulse width GPIO1 period GPIO0 pulse width GPIO6 pulse width GPIO6 rising edge GPIO0 falling edge GPIO2 toggle GPIO3 toggle GPIO5 pulse width Units (note
pixel clock period
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GPIO4 (RES)
DRDY (GCP)
Data Register (REG[2Ch])
bit7
bit0 bit7 Index
Index
bit7
Index
Figure 6-38: 320x240 Epson D-TFD Panel Horizontal Timing
Table 6-32: 320x240 Epson D-TFD Panel Horizontal Timing
Symbol Parameter Half horizontal total period clock period Units (note
pixel clock period
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Vertical Total 250HT FPFRAME (DY) GPIO1 (YSCL) GPIO0 (XINH) FPDAT[17:0] (R,G,B) line1 line2
GPIO2 (FR) (odd frame)
GPIO2 (FR) (even frame)
Figure 6-39: 320x240 Epson D-TFD Panel Vertical Timing Table 6-33: 320x240 Epson D-TFD Panel Vertical Timing
Symbol FPFRAME pulse width Horizontal total period Vertical display start Parameter Units (note
pixel clock period
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Clocks
Clock Descriptions
7.1.1 BCLK
BCLK internal clock derived from CLKI. BCLK divided version (÷1, CLKI. CLKI typically derived from host clock. source clock options BCLK selected following table. Table 7-1: BCLK Clock Selection
Source Clock Options CLKI CLKI CLKI CLKI BCLK Selection CNF[7:6] CNF[7:6] CNF[7:6] CNF[7:6]
Note
synchronous interfaces, recommended that BCLK same clock (not divided version CLKI) e.g. SH-3, SH-4.
Note
CLKI CLKI options work properly with interfaces with short back-to-back cycle timing.
7.1.2 MCLK
MCLK provides internal clock required access embedded SRAM. S1D13706 designed with efficient power saving control clocks (clocks turned when used); reducing frequency MCLK does necessarily save more power. Furthermore, reducing MCLK frequency relative BCLK frequency increases cycle latency reduces screen update performance. balance power saving performance, MCLK should configured have high enough frequency setting provide sufficient screen refresh well acceptable cycle latency. source clock options MCLK selected following table. Table 7-2: MCLK Clock Selection
Source Clock Options BCLK BCLK BCLK BCLK
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MCLK Selection REG[04h] REG[04h] REG[04h] REG[04h]
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7.1.3 PCLK
PCLK internal clock used control panel. PCLK should chosen match optimum frame rate panel. Section "Frame Rate Calculation" page details relationship between PCLK frame rate. Some flexibility possible selection PCLK. Firstly, panels typically have range permissible frame rates. Secondly, possible choose higher PCLK frequency tailor horizontal vertical non-display periods lower frame-rate optimal value. source clock options PCLK selected following table. Table 7-3: PCLK Clock Selection
Source Clock Options MCLK MCLK MCLK MCLK MCLK BCLK BCLK BCLK BCLK BCLK CLKI CLKI CLKI CLKI CLKI CLKI2 CLKI2 CLKI2 CLKI2 CLKI2 PCLK Selection REG[05h] REG[05h] REG[05h] REG[05h] REG[05h] REG[05h] REG[05h] REG[05h] REG[05h] REG[05h] REG[05h] REG[05h] REG[05h] REG[05h] REG[05h] REG[05h] REG[05h] REG[05h] REG[05h] REG[05h]
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There relationship between frequency MCLK PCLK that must maintained. Table 7-4: Relationship between MCLK PCLK
SwivelView Orientation Color Depth (bpp) SwivelView 180° SwivelView 270° 16/8/4/2/1 MCLK PCLK Relationship fMCLK fPCLK fMCLK fPCLK fMCLK fPCLK fMCLK fPCLK fMCLK fPCLK fMCLK 1.25fPCLK
7.1.4 PWMCLK
PWMCLK internal clock used Pulse Width Modulator output panel. source clock options PWMCLK selected following table. Table 7-5: PWMCLK Clock Selection
Source Clock Options CLKI CLKI2 PWMCLK Selection REG[B1h] REG[B1h]
further information controlling PWMCLK, Section 8.3.9, "Pulse Width Modulation (PWM) Clock Contrast Voltage (CV) Pulse Configuration Registers" page 126.
Note
S1D13706 provides Pulse Width Modulation output PWMOUT. PWMOUT used control panels which support control backlight inverter.
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Clock Selection
following diagram provides logical representation S1D13706 internal clocks.
CLKI
BCLK
CNF[7:6]1
REG[04h] bits
MCLK
CLKI2 PCLK
REG[05h] bits
REG[05h] bits PWMCLK
REG[B1h]
Figure 7-1: Clock Selection
Note
CNF[7:6] must RESET#.
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Clocks versus Functions
Table 7-6: "S1D13706 Internal Clock Requirements", lists internal clocks required following S1D13706 functions. Table 7-6: S1D13706 Internal Clock Requirements
Function Register Read/Write Memory Read/Write Look-Up Table Register Read/Write Software Power Save Output Clock (BCLK) Required Required Required Required Required Memory Clock (MCLK) Required Required Required Required Required Pixel Clock (PCLK) Required Required Required Required Required Clock (PWMCLK) Required1 Required1 Required1 Required1 Required1
Note
PWMCLK optional clock (see Section 7.1.4, "PWMCLK" page 92).
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Registers
This section discusses where access S1D13706 registers. also provides detailed information about layout usage each register.
Register Mapping
S1D13706 registers memory-mapped. When system decodes input pins M/R# registers accessed. register space decoded A[16:0].
Register
S1D13706 register follows. Table 8-1: S1D13706 Register
Register
REG[00h] Revision Code Register REG[02h] Configuration Readback Register
Read-Only Configuration Registers
Register
REG[01h] Display Buffer Size Register
Clock Configuration Registers
REG[04h] Memory Clock Configuration Register REG[05h] Pixel Clock Configuration Register
Look-Up Table Registers
REG[08h] Look-Up Table Blue Write Data Register REG[0Ah] Look-Up Table Write Data Register REG[0Ch] Look-Up Table Blue Read Data Register REG[0Eh] Look-Up Table Read Data Register REG[09h] Look-Up Table Green Write Data Register REG[0Bh] Look-Up Table Write Address Register REG[0Dh] Look-Up Table Green Read Data Register REG[0Fh] Look-Up Table Read Address Register
Panel Configuration Registers
REG[10h] Panel Type Register REG[12h] Horizontal Total Register REG[16h] Horizontal Display Period Start Position Register REG[18h] Vertical Total Register REG[1Ch] Vertical Display Period Register REG[1Eh] Vertical Display Period Start Position Register REG[20h] FPLINE Pulse Width Register REG[23h] FPLINE Pulse Start Position Register REG[26h] FPFRAME Pulse Start Position Register REG[28h] D-TFD Index Register REG[11h] Rate Register REG[14h] Horizontal Display Period Register REG[17h] Horizontal Display Period Start Position Register REG[19h] Vertical Total Register REG[1Dh] Vertical Display Period Register REG[1Fh] Vertical Display Period Start Position Register REG[22h] FPLINE Pulse Start Position Register REG[24h] FPFRAME Pulse Width Register REG[27h] FPFRAME Pulse Start Position Register REG[2Ch] D-TFD Data Register
Display Mode Registers
REG[70h] Display Mode Register REG[74h] Main Window Display Start Address Register REG[76h] Main Window Display Start Address Register REG[79h] Main Window Line Address Offset Register REG[71h] Special Effects Register REG[75h] Main Window Display Start Address Register REG[78h] Main Window Line Address Offset Register
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Table 8-1: S1D13706 Register
Register
REG[7Ch] PIP+
Picture-in-Picture Plus (PIP Registers
Register
REG[7Dh] PIP+ Window Display Start Address Register REG[80h] PIP+ Window Line Address Offset Register REG[84h] Window Start Position Register REG[88h] PIP+ Window Start Position Register REG[8Ch] Window Position Register REG[90h] PIP+ Window Position Register
Window Display Start Address Register
REG[7Eh] Window Display Start Address Register REG[81h] Window Line Address Offset Register REG[85h] PIP+ Window Start Position Register REG[89h] Window Start Position Register REG[8Dh] PIP+ Window Position Register REG[91h] PIP+ Window Position Register
Miscellaneous Registers
REG[A0h] Power Save Configuration Register REG[A2h] Reserved REG[A4h] Scratch Register REG[A1h] Reserved REG[A3h] Reserved REG[A5h] Scratch Register
General Purpose Pins Registers
REG[A8h] General Purpose Pins Configuration Register REG[A9h] General Purpose Pins Configuration Register REG[ACh] General Purpose Pins Status/Control Register REG[ADh] General Purpose Pins Status/Control Register
Clock Pulse Configuration Registers
REG[B0h] Clock Pulse Control Register REG[B2h] Pulse Burst Length Register REG[B1h] Clock Pulse Configuration Register REG[B3h] PWMOUT Duty Cycle Register
Register Descriptions
Unless specified otherwise, register bits during power-on.
8.3.1 Read-Only Configuration Registers
Revision Code Register REG[00h]
Product Code Bits
Read Only
Revision Code Bits
Note
S1D13706 returns value 28h. bits bits Product Code These read-only bits that indicates product code. product code 001010. Revision Code These read-only bits that indicates revision code. revision code
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Display Buffer Size Register REG[01h]
Display Buffer Size Bits
Read Only
bits
Display Buffer Size Bits [7:0] This read-only register that indicates size SRAM display buffer measured byte increments. S1D13706 display buffer bytes therefore this register returns value (14h). Value this register display buffer size bytes bytes bytes (14h)
Configuration Readback Register REG[02h]
CNF7 Status
Read Only
CNF4 Status
CNF6 Status CNF5 Status
CNF3 Status
CNF2 Status
CNF1 Status
CNF0 Status
bits
CNF[7:0] Status These read-only status bits return status configuration pins CNF[7:0]. CNF[7:0] latched rising edge RESET#.
8.3.2 Clock Configuration Registers
Memory Clock Configuration Register REG[04h]
Read/Write
MCLK Divide Select Bits
Reserved
bits
MCLK Divide Select Bits [1:0] These bits determine divide used generate Memory Clock (MCLK) from Clock (BCLK). Table 8-2: MCLK Divide Selection
MCLK Divide Select Bits BCLK MCLK Frequency Ratio
Reserved. This must remain
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Pixel Clock Configuration Register REG[05h]
Read/Write
PCLK Divide Select Bits
PCLK Source Select Bits
bits
PCLK Divide Select Bits [1:0] These bits determine divide used generate Pixel Clock (PCLK) from Pixel Clock Source. Table 8-3: PCLK Divide Selection
PCLK Divide Select Bits PCLK Source PCLK Frequency Ratio
bits
PCLK Source Select Bits [1:0] These bits determine source Pixel Clock (PCLK). Table 8-4: PCLK Source Selection
PCLK Source Select Bits PCLK Source MCLK BCLK CLKI CLKI2
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8.3.3 Look-Up Table Registers
Note
S1D13706 three 256-position, 6-bit wide LUTs, each red, green, blue (see Section "Look-Up Table Architecture" page 132).
Look-Up Table Blue Write Data Register REG[08h]
Blue Write Data Bits
Write Only
bits
Blue Write Data Bits [5:0] This register contains data written blue component Look-Up Table. data stored this register until write Write Address register (REG[0Bh]) moves data into Look-Up Table.
Note
entry updated only when Write Address Register (REG[0Bh]) written
Look-Up Table Green Write Data Register REG[09h]
Green Write Data Bits
Write Only
bits
Green Write Data Bits [5:0] This register contains data written green component Look-Up Table. data stored this register until write Write Address register (REG[0Bh]) moves data into Look-Up Table.
Note
entry updated only when Write Address Register (REG[0Bh]) written
Look-Up Table Write Data Register REG[0Ah]
Write Data Bits
Write Only
bits
Write Data Bits [5:0] This register contains data written component Look-Up Table. data stored this register until write Write Address register (REG[0Bh]) moves data into Look-Up Table.
Note
entry updated only when Write Address Register (REG[0Bh]) written
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Look-Up Table Write Address Register REG[0Bh]
Write Address Bits
Write Only
bits
Write Address Bits [7:0] This register forms pointer into Look-Up Table (LUT) which used write blue, green, data stored REG[08h], REG[09h], REG[0Ah]. data updated only with completion write this register. This writeonly register returns read.
Note
When value written Write Address register, same value automatically written Read Address register (REG[0Fh].
Look-Up Table Blue Read Data Register REG[0Ch]
Blue Read Data Bits
Read Only
bits
Blue Read Data Bits [5:0] This register contains data from blue component Look-Up Table. position controlled Read Address Register (REG[0Fh]). This read-only register.
Note
This register updated only when Read Address Register (REG[0Fh]) written
Look-Up Table Green Read Data Register REG[0Dh]
Green Read Data Bits
Read Only
bits
Green Read Data Bits [5:0] This register contains data from green component Look-Up Table. position controlled Read Address Register (REG[0Fh]). This read-only register.
Note
This register updated only when Read Address Register (REG[0Fh]) written
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Look-Up Table Read Data Register REG[0Eh]
Read Data Bits
Read Only
bits
Read Data Bits [5:0] This register contains data from component Look-Up Table. position controlled Read Address Register (REG[0Fh]). This read-only register.
Note
This register updated only when Read Address Register (REG[0Fh]) written
Look-Up Table Read Address Register REG[0Fh]
Read Address Bits
Write Only
bits
Read Address Bits [7:0] This register forms pointer into Look-Up Table (LUT) which used read blue, green, data. Blue data read from REG[0Ch], green data from REG[0Dh], data from REG[0Eh]. This write-only register returns read.
Note
write Write Address register (REG[0Bh]) made, Read Address register automatically updated with same value.
8.3.4 Panel Configuration Registers
Panel Type Register REG[10h]
Panel Data Format Select
Read/Write
Panel Data Width Bits
Color/Mono. Panel Select
Active Panel Resolution Select
Panel Type Bits
Panel Data Format Select When this 8-bit single color passive panel data format selected. timing Section 6.4.5, "Single Color 8-Bit Panel Timing (Format page When this 8-bit single color passive panel data format selected. timing Section 6.4.6, "Single Color 8-Bit Panel Timing (Format page Color/Mono Panel Select When this monochrome panel selected. When this color panel selected.
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bits
Panel Data Width Bits [1:0] These bits select data width size panel. Table 8-5: Panel Data Width Selection
Panel Data Width Bits [1:0] Passive Panel Data Width Size 4-bit 8-bit 16-bit Reserved Active Panel Data Width Size 9-bit 12-bit 18-bit Reserved
Active Panel Resolution Select This selects panel resolutions when HR-TFT D-TFD panel selected. This effect other panel types. Table 8-6: Active Panel Resolution Selection
Active Panel Resolution Select HR-TFT Resolution 160x160 320x240 D-TFD Resolution 160x240 320x240
Note
This sets some internal non-configurable timing values selected panel. However, panel configuration registers (REG[12h] REG[27h]) still require programming with appropriate values selected panel. panel timing, Section 6.4, "Display Interface" page bits Panel Type Bits[1:0] These bits select panel type. Table 8-7: Panel Type Selection
REG[10h] Bits[1:0] Panel Type HR-TFT D-TFD
S1D13706 X31B-A-001-09
Hardware Functional Specification Issue Date: 2004/02/09
Epson Research Development Vancouver Design Center
Page
Rate Register REG[11h]
Read/Write
Rate Bits
bits
Rate Bits [5:0] These bits passive panels only. When these bits output signal (DRDY) toggles every FPFRAME. non-zero value output signal (DRDY) toggles every FPLINE.
Horizontal Total Register REG[12h]
Read/Write
Horizontal Total Bits
bits
Horizontal Total Bits [6:0] These bits specify panel Horizontal Total period, pixel resolution. Horizontal Total Horizontal Display period Horizontal Non-Display period. Since maximum Horizontal Total 1024 pixels, maximum panel resolution supported 800x600. Horizontal Total number pixels ((REG[12h] bits 6:0)
Note
This register must programmed such that following formulas valid. HDPS panel timing timing parameter definitions, Section 6.4, "Display Interface" page
Horizontal Display Period Register REG[14h]
Read/Write
Horizontal Display Period Bits
bits
Horizontal Display Period Bits [6:0] These bits specify panel Horizontal Display Period (HDP), pixel resolution. Horizontal Display Period should less than Horizontal Total allow sufficient Horizontal Non-Display Period. Horizontal Display Period number pixels ((REG[14h] bits 6:0)
Note
passive panels, must minimum pixels increased multiples panels, must minimum pixels increased multiples panel timing timing parameter definitions, Section 6.4, "Display Interface" page
Hardware Functional Specification Issue Date: 2004/02/09 S1D13706 X31B-A-001-09
Page
Epson Research Development Vancouver Design Center
Horizontal Display Period Start Position Register REG[16h]
Horizontal Display Period Start Position Bits
Read/Write
Horizontal Display Period Start Position Register REG[17h]
Read/Write
Horizontal Display Period Start Position Bits
bits
Horizontal Display Period Start Position Bits [9:0] These bits specify value used calculation Horizontal Display Period Start Position pixel resolution) TFT, HR-TFT D-TFD panels. passive panels these bits must which will result HDPS HDPS (REG[17h] bits 1-0, REG[16h] bits 7-0) TFT/HR-TFT/D-TFD panels, HDPS calculated using following formula. HDPS (REG[17h] bits 1-0, REG[16h] bits 7-0) further information calculating HDPS, specific panel Timing Section 6.4, "Display Interface" page
Note
This register must programmed such that following formula valid. HDPS
S1D13706 X31B-A-001-09
Hardware Functional Specification Issue Date: 2004/02/09
Epson Research Development Vancouver Design Center
Page
Vertical Total Register REG[18h]
Vertical Total Bits
Read/Write
Vertical Total Register REG[19h]
Read/Write
Vertical Total Bits
bits
Vertical Total Bits [9:0] These bits specify panel Vertical Total period, line resolution. Vertical Total Vertical Display Period Vertical Non-Display Period. maximum Vertical Total 1024 lines. Vertical Total number lines (REG[18h] bits 7:0, REG[19h] bits 1:0)
Note
This register must programmed such that following formula valid. VDPS panel timing timing parameter definitions, Section 6.4, "Display Interface" page
Vertical Display Period Register REG[1Ch]
Vertical Display Period Bits
Read/Write
Vertical Display Period Register REG[1Dh]
Read/Write
Vertical Display Period Bits
bits
Vertical Display Period Bits [9:0] These bits specify panel Vertical Display period, line resolution. Vertical Display period should less than Vertical Total allow sufficient Vertical Non-Display period. Vertical Display Period number lines (REG[1Ch] bits 7:0, REG[1Dh] bits 1:0)
Note
panel timing timing parameter definitions, Section 6.4, "Display Interface" page
Hardware Functional Specification Issue Date: 2004/02/09
S1D13706 X31B-A-001-09
Page
Epson Research Development Vancouver Design Center
Vertical Display Period Start Position Register REG[1Eh]
Vertical Display Period Start Position Bits
Read/Write
Vertical Display Period Start Position Register REG[1Fh]
Read/Write
Vertical Display Period Start Position Bits
bits
Vertical Display Period Start Position Bits [9:0] These bits specify Vertical Display Period Start Position panels line resolution. passive panels these bits must 00h. panels, VDPS calculated using following formula. VDPS (REG[1Fh] bits 1-0, REG[1Eh] bits 7-0)
Note
This register must programmed such that following formula valid. VDPS panel timing timing parameter definitions, Section 6.4, "Display Interface" page
FPLINE Pulse Width Register REG[20h]
FPLINE Pulse Polarity
Read/Write
FPLINE Pulse Width Bits
FPLINE Pulse Polarity This selects polarity horizontal sync signal. passive panels, this must panels, this according horizontal sync signal panel (typically FPLINE LP). When this horizontal sync signal active low. When this horizontal sync signal active high. FPLINE Pulse Width Bits [6:0] These bits specify width panel horizontal sync signal, pixel resolution. horizontal sync signal typically FPLINE depending panel type. FPLINE Pulse Width number pixels (REG[20h] bits 6:0)
Note
bits
panel timing timing parameter definitions, Section 6.4, "Display Interface" page
S1D13706 X31B-A-001-09
Hardware Functional Specification Issue Date: 2004/02/09
Epson Research Development Vancouver Design Center
Page
FPLINE Pulse Start Position Register REG[22h]
FPLINE Pulse Start Position Bits
Read/Write
FPLINE Pulse Start Position Register REG[23h]
Read/Write
FPLINE Pulse Start Position Bits
bits
FPLINE Pulse Start Position Bits [9:0] These bits specify start position horizontal sync signal, pixel resolution. FPLINE Pulse Start Position pixels (REG[23h] bits 1-0, REG[22h] bits 7-0)
Note
passive panels, these bits must programmed such that following formula valid.
Note
panel timing timing parameter definitions, Section 6.4, "Display Interface" page
FPFRAME Pulse Width Register REG[24h]
FPFRAME Pulse Polarity
Read/Write
FPFRAME Pulse Width Bits<br
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