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VSC7166 Features OC-192 SONET Frame Transport Mechanisms Con


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VSC7166
Features
OC-192 SONET Frame Transport Mechanisms Converts LVDS Inputs 622Mb/s into 8B10B Encoded LVDS Outputs 1.244Gb/s Converts LVDS Inputs 1.244Gb/s into LVDS Outputs 622Mb/s Conforms OIF99.120 8b/10b Encoder/Decoder Channel Diagnostic Error Injection Insertion/Recognition Framing Patterns
OC-192 16:12 SerDes
Channel-to-Channel Deskewing Receiver Redundant Channel Fault Tolerance Patchcord Reversal Protection Channel Error Detection Loss Synchronization State Machine 1.8V 2.5V Supplies Power 256-pin, 27mm Package
General Description
VSC7166 used interface between OC-192 Framers Parallel Optical Modules. serializer, 16bit OC-192 data from Framer mapped encoded onto twelve 1.244Gb/s, 8b/10b outputs, with outputs being used protection another twelve EDC. deserializer, twelve 1.244Gb/s inputs decoded remapped 16-bit OC-192 data Framer. redundant channel permits data reconstructed deserializer even channel fails. These devices intended highspeed router-to-router DWDM/SONET terminal-to-router connections. VSC7166 conforms Optical Internetworking Forum's Proposal Very Short Reach (VSR) OC-192 Interface Based Parallel Optics OIF-99.120.
This document contains preliminary information about product during fabrication early sampling phase development subject change without notice.
September 2000
VITESSE SEMICONDUCTOR CORPORATION Calle Plano, Camarillo, 93012 805/388-3700 FAX: 805/987-5896
Page
OC-192 16:12 SerDes
VSC7166
VSC7166 Block Diagram
Delay Framer Byte Clock 8B/10B Encode 1.24 Gb/s Transceivers Transmit Optics ON/P(11:0) 1.24 Gb/s
DIP/N(15:0)
CLKIN/P
ECEN AZEN PROTEN NELOOP Byte DOP/N(15:0) Check Protection Switching output PRBS Check
Frame Delimiter Insertion Channels)
Transmitter Receiver
8B/10B Decode LOSyn 1.24 Gb/s 1.24 GB/s Transceiver IN/P(11:0)
Alignment Pointer Alignment Buffer Control
Polarity Control Polarity Control
CLKON/P
Control Alignment Buffer
8B/10B Decode LOSyn
1.24 GB/s Transceiver 1.24 Gb/s Processor Interface Block
CLKOBN/P
RFTI RTDI PDLI PILO ASEL
Alignment Pointer Clock from
CAP0
TRSTN JTAG Boundary Scan
Framer Delay 8B/10B
CAP1
Preliminary Specifications
Description
CLKI Frequency Total Output Jitter Correctible Skew I[0:11] Maximum Case Temperature
622.08 -200ppm
622.08 +200ppm
Units
Times
Conditions
IEEE 802.3z, Clause 38.68
Page
VITESSE SEMICONDUCTOR CORPORATION Calle Plano, Camarillo, 93012 805/388-3700 FAX: 805/987-5896
September 2000

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