74HC/HCT7404 5-Bit 64-word FIFO register; 3-state Product specifi

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74HC/HCT7404 5-Bit 64-word FIFO register; 3-state Product specifi

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IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications IC06 74HC/HCT/HCU/HCMOS Logic Package Information IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT7404 5-Bit 64-word FIFO register; 3-state
Product specification Supersedes data October 1990 File under Integrated Circuits, IC06 September 1993
Philips Semiconductors
Product specification
5-Bit 64-word FIFO register; 3-state
FEATURES Synchronous asynchronous operation 3-state outputs (typical) shift-in shift-out rates Readily expandable word dimensions Pinning arranged easy board layout: input pins directly opposite output pins Output capability: driver category: LSI. APPLICATIONS High-speed disc tape controller Communications buffer. GENERAL DESCRIPTION
74HC/HCT7404
74HC/HCT7404 high-speed Si-gate CMOS devices specified compliance with JEDEC standard no.7A. "7404" expandable, First-In First-Out (FIFO) memory organized words bits. guaranteed data-rate makes ideal high-speed applications. higher data-rate obtained applications where status flags used (burst-mode). With separate controls shift-in (SI) shift-out (SO), reading writing operations completely independent, allowing synchronous asynchronous data transfers. Additional controls include master-reset input (MR), output enable input (OE) flags. data-in-ready (DIR) data-out-ready (DOR) flags indicate status device.
QUICK REFERENCE DATA Tamb TYP. SYMBOL tPHL/tPLH fmax Note condition VCC. condition -1.5 ORDERING INFORMATION EXTENDED TYPE NUMBER 74HC/HCT7404N 74HC/HCT7404D PACKAGE PINS POSITION SO20 MATERIAL plastic plastic CODE SOT102 SOT163A PARAMETER propagation delay maximum clock frequency input capacitance power dissipation capacitance package note CONDITIONS UNIT
September 1993
Philips Semiconductors
Product specification
5-Bit 64-word FIFO register; 3-state
PINNING (SOT102) SYMBOL DESCRIPTION output enable input (active LOW) data-in-ready output shift-in input (active HIGH) ground asynchronous master-reset input (active LOW) data outputs data-out-ready output shift-out input (active LOW) positive supply voltage n.c. n.c. PINNING (SOT163A) SYMBOL n.c.
74HC/HCT7404
DESCRIPTION output enable input (active LOW) data-in-ready output shift-in input (active HIGH) connected ground asynchronous master-reset input (active LOW) data outputs connected data-out ready output connected positive supply voltage
parallel data inputs
parallel data inputs
handbook, halfpage handbook, halfpage
MGA670
n.c.
n.c.
7404
7404
MGA671
Fig.1 configuration (SOT102).
Fig.2 configuration (SOT163).
September 1993
Philips Semiconductors
Product specification
5-Bit 64-word FIFO register; 3-state
74HC/HCT7404
handbook, halfpage
handbook, halfpage
FIFO [IR] [OR] (18)
(11)
MGA673
(16) (15) (14) (13) (12) (11) (19)
/C2)
(19)
(18)
(16) (15) (14) (13) (12)
MGA675
numbers between parentheses refer package.
numbers between parentheses refer package.
Fig.3 Logic symbol.
Fig.4 logic symbol.
handbook, full pagewidth
INPUT STAGE BITS MAIN FIFO REGISTER BITS OUTPUT STAGE BITS
(16) (15) (14) (13) (12)
(11)
CONTROL LOGIC
MGA680
(18) (19)
numbers between parentheses refer package.
Fig.5 Functional diagram.
September 1993
full pagewidth
September 1993
Philips Semiconductors
FF64
5-Bit 64-word FIFO register; 3-state
FF63
LATCHES LATCHES LATCHES 3-STATE OUTPUT BUFFER position position position
MSB117
LATCHES
position
(See control flip-flops) input flip-flops will output HIGH independent state input. input FF64 will output independent state input.
74HC/HCT7404
Product specification
Fig.6 Logic diagram.
Philips Semiconductors
Product specification
5-Bit 64-word FIFO register; 3-state
FUNCTIONAL DESCRIPTION flag indicates input stage status, either empty ready receive data (DIR HIGH) full busy (DIR LOW). When HIGH, data present shifted into input stage; once complete goes LOW. When LOW, data automatically shifted output stage last empty location. FIFO which receive data indicated HIGH. flag indicates output stage status, either data available (DOR HIGH) busy (DOR LOW). When HIGH, data available CHARACTERISTICS 74HC characteristics "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: parallel outputs, driver; serial output, standard category: Output capability: driver category: Voltages referenced (ground CHARACTERISTICS 74HC Tamb SYMBOL PARAMETER HIGH level output voltage level output voltage 3.98 5.48 4.32 5.81 0.15 0.15 0.26 0.26 3.84 5.34 0.33 0.33 outputs Q4). When data shifted into output stage, once complete LOW. Expanded Format (see Fig.18) signals used allow `7404' cascaded. Both parallel serial expansion possible. Serial expansion only possible with typical devices. Parallel Expansion Parallel expansion accomplished logically ANDing signals form composite signal.
74HC/HCT7404
Serial Expansion Serial expansion accomplished tying data outputs first device data inputs second device connecting first device second device connecting first device second device.
TEST CONDITION +125 UNIT 3.70 5.20 OTHER
September 1993
Philips Semiconductors
Product specification
5-Bit 64-word FIFO register; 3-state
CHARACTERISTICS 74HC Tamb SYMBOL PARAMETER tPHL/tPLH propagation delay DIR, propagation delay propagation delay propagation delay propagation delay propagation delay propagation delay/ripple through delay 11.2 +125 10.5 13.5 UNIT
74HC/HCT7404
TEST CONDITION WAVEFORMS Fig.9
tPHL
Fig.9
tPHL/tPLH
Fig.7
tPHL/tPLH
Fig.10
tPHL/tPLH
Fig.11
tPHL/tPLH
Fig.15
tPLH
Fig.16
tPLH
propagation delay/bubble-up delay 3-state output enable 3-state output disable
Fig.8
tPZH/tPZL
Fig.17
tPHZ/tPLZ
Fig.17
tTHL/tTLH
output transition time pulse width HIGH pulse width HIGH
Fig.17
Fig.7
Fig.10
September 1993
Philips Semiconductors
Product specification
5-Bit 64-word FIFO register; 3-state
Tamb SYMBOL PARAMETER pulse width HIGH pulse width HIGH pulse width removal time set-up time hold time +125 UNIT
74HC/HCT7404
TEST CONDITION WAVEFORMS Fig.8
Fig.11
Fig.9
trem
Fig.16
Fig.14
Fig.14
fmax
maximum clock pulse frequency burst mode maximum clock pulse frequency using flags maximum clock pulse frequency cascaded
Fig.12 Fig.13
fmax
Fig.7 Fig.10
fmax
Fig.7 Fig.10
September 1993
Philips Semiconductors
Product specification
5-Bit 64-word FIFO register; 3-state
CHARACTERISTICS 74HCT
74HC/HCT7404
characteristics "74HC/HCT/HCU/HCMOS Logic Family Specifications", except that valid driver output. They replaced values given below. Output capability: driver category: LSI. Voltages referenced (ground CHARACTERISTICS 74HCT Tamb SYMBOL PARAMETER HIGH level output voltage level output voltage 3.98 4.32 3.84 +125 UNIT TEST CONDITION OTHER
0.15
0.26
0.33
0.40
Note types value additional quiescent supply current (ICC) unit load given family specifications. determine input, multiply this value unit load coefficient shown table below. UNIT LOAD COEFFICIENT INPUT UNIT LOAD COEFFICIENT 0.75
September 1993
Philips Semiconductors
Product specification
5-Bit 64-word FIFO register; 3-state
CHARACTERISTICS 74HCT Tamb SYMBOL PARAMETER tPHL/tPLH propagation delay DIR, propagation delay propagation delay propagation delay propagation delay propagation delay propagation delay/ripple through delay propagation delay/bubbleup delay 3-state output enable 3-state output disable output transition time pulse width HIGH pulse width HIGH +125 UNIT
74HC/HCT7404
TEST CONDITION WAVEFORMS Fig.9
tPHL
Fig.9
tPHL/tPLH
Fig.7
tPHL/tPLH
Fig.10
tPHL/tPLH
Fig.15
tPHL/tPLH
Fig.11
tPLH
1.75
Fig.11
tPLH
2.25
Fig.8
tPZH/tPZL
Fig.17
tPHZ/tPLZ
Fig.17
tTHL/tTLH
Fig.17 Fig.7 Fig.10 Fig.8
pulse width HIGH
September 1993
Philips Semiconductors
Product specification
5-Bit 64-word FIFO register; 3-state
Tamb SYMBOL PARAMETER trem fmax pulse width HIGH pulse width removal time set-up time hold time maximum clock pulse frequency burst mode maximum clock pulse frequency using flags maximum clock pulse frequency cascaded +125 UNIT
74HC/HCT7404
TEST CONDITION WAVEFORMS Fig.11 Fig.9 Fig.16 Fig.14 Fig.14 Fig.12 Fig.13
fmax
Fig.7 Fig.10
fmax
Fig.7 Fig.10
September 1993
Philips Semiconductors
Product specification
5-Bit 64-word FIFO register; 3-state
WAVEFORMS Shifting sequence FIFO empty FIFO full
74HC/HCT7404
handbook, full pagewidth
word
word
64th word
INPUT
OUTPUT
INPUT
MGA659
50%; VCC.
Fig.7
Waveforms showing input output propagation delay, pulse width maximum pulse frequency.
Notes Fig.7 initially HIGH; FIFO prepared valid data HIGH; data loaded into input stage goes LOW, input stage "busy" LOW; data from first location "ripple through" goes HIGH, status flag indicates FIFO prepared additional data Repeat process load word through 64th word into FIFO remains LOW; with attempt shift into full FIFO, data transfer occurs.
September 1993
Philips Semiconductors
Product specification
5-Bit 64-word FIFO register; 3-state
With FIFO full; held HIGH anticipation empty location
74HC/HCT7404
handbook, full pagewidth
INPUT
INPUT
bubble delay
OUTPUT
MGA660
50%; VCC.
Fig.8 Waveforms showing bubble-up delay, input output output pulse width.
Notes Fig.8 FIFO initially full, shift-in held HIGH pulse; data output stage unloaded, "bubble-up" process empty location begins HIGH; when empty location reaches input stage, flag indicates FIFO prepared data input returns LOW; data shift-in empty location complete, FIFO full again LOW; necessary complete shift-in process, remains LOW, because FIFO full.
September 1993
Philips Semiconductors
Product specification
5-Bit 64-word FIFO register; 3-state
Master reset applied with FIFO full
74HC/HCT7404
handbook, halfpage
INPUT
OUTPUT
OUTPUT
OUTPUT
MGA668
50%; VCC.
Fig.9 Waveforms showing input DIR, output propagation delays pulse width.
Notes Fig.9 LOW, output ready HIGH; assume FIFO full pulse LOW; clears FIFO goes HIGH; flag indicates input prepared valid data goes LOW; flag indicates FIFO empty outputs (only last will reset).
September 1993
Philips Semiconductors
Product specification
5-Bit 64-word FIFO register; 3-state
74HC/HCT7404
handbook, full pagewidth
pulse OUTPUT
pulse
64th pulse
INPUT
OUTPUT
word
word
64th word
MGA661
50%; VCC.
Fig.10 Waveforms showing input output propagation delay, pulse widths maximum pulse frequency.
Notes Fig.10 HIGH; data transfer progress, valid data present output stage HIGH; results going goes LOW; output stage "busy" LOW; data input stage unloaded, data replaces empty location "bubbles-up" input stage goes HIGH; transfer process completed, valid data present output after specified propagation delay Repeat process unload through 64th word from FIFO. remains LOW; FIFO empty.
September 1993
Philips Semiconductors
Product specification
5-Bit 64-word FIFO register; 3-state
With FIFO empty; held HIGH anticipation
74HC/HCT7404
handbook, full pagewidth
INPUT
INPUT
ripple through delay
OUTPUT
OUTPUT
MGA669
50%; VCC.
Fig.11 Waveforms showing ripple through delay input output, output pulse width propagation delay from pulse output.
Notes Fig.11 FIFO initially empty, held HIGH pulse; loads data into FIFO initiates ripple through process flag signals arrival valid data output stage Output transition; data arrives output stage after specified propagation delay between rising edge pulse output goes LOW; data shift-out complete, FIFO empty again LOW; necessary complete shift-out process. remains LOW, because FIFO empty.
September 1993
Philips Semiconductors
Product specification
5-Bit 64-word FIFO register; 3-state
Shift-in operation; high-speed burst mode
74HC/HCT7404
handbook, full pagewidth
INPUT
INPUT
OUTPUT
MGA662
50%; VCC.
Fig.12 Waveforms showing minimum pulse width maximum pulse frequency, high-speed shift-in burst mode.
Note Fig.12 high-speed mode, burst-in rate determined minimum shift-in HIGH shift-in specifications. status flag don't care condition, shift-in pulse applied regardless flag. pulse which would overflow storage capacity FIFO ignored.
September 1993
Philips Semiconductors
Product specification
5-Bit 64-word FIFO register; 3-state
Shift-out operation; high-speed burst mode
74HC/HCT7404
handbook, full pagewidth
INPUT
OUTPUT
OUTPUT
MGA663
50%; VCC.
Fig.13 Waveforms showing minimum pulse width maximum pulse frequency, high-speed shift-out burst mode.
Note Fig.13 high-speed mode, burst-out rate determined minimum shift-out HIGH shift-out specifications. flag don't care condition pulse applied without regard flag.
September 1993
Philips Semiconductors
Product specification
5-Bit 64-word FIFO register; 3-state
74HC/HCT7404
handbook, full pagewidth
INPUT
INPUT
MGA657
50%; VCC.
shaded areas indicate when input permitted change predictable output performance.
Fig.14 Waveforms showing hold set-up times input input.
handbook, full pagewidth
INPUT
OUTPUT
MGA664
50%; VCC.
Fig.15 Waveforms showing input output propagation delays output transition time.
handbook, halfpage
INPUT
INPUT 50%; VCC.
MGA665
Fig.16 Waveform showing input input removal time.
September 1993
Philips Semiconductors
Product specification
5-Bit 64-word FIFO register; 3-state
74HC/HCT7404
handbook, full pagewidth
INPUT OUTPUT OUTPUT HIGH HIGH outputs enabled
outputs disabled outputs enabled
MGA656
50%; VCC.
Fig.17 Waveforms showing 3-state enable disable times input
September 1993
Philips Semiconductors
Product specification
5-Bit 64-word FIFO register; 3-state
APPLICATION INFORMATION
74HC/HCT7404
handbook, full pagewidth
7404
7404
10-bit data
10-bit data
7404
7404
MGA686
Fig.18 Expanded FIFO (parallel serial) increased word length; bits wide n-bits.
September 1993
Philips Semiconductors
Product specification
5-Bit 64-word FIFO register; 3-state
74HC/HCT7404
handbook, full pagewidth
DATA INPUT COMPOSITE FLAG
DATA OUTPUT COMPOSITE FLAG
7404
7404
DATA INPUT
MGA681
DATA OUTPUT
Fig.19 Expanded FIFO increased word length; words bits.
Note Fig.19 "7404" easily expanded increase word length. Composite flags formed with addition gate. basic operation timing identical single FIFO, with exception added gate delay flags.
September 1993
Philips Semiconductors
Product specification
5-Bit 64-word FIFO register; 3-state
74HC/HCT7404
handbook, full pagewidth
composite
7404
composite
7404
MGA685
Fig.20 Expanded FIFO increased word length.
Note Fig.20 This circuit only required input constantly held HIGH, when FIFO empty automatic shift-in cycles started output constantly held HIGH, when FIFO full automatic shift-out cycles started (see Fig.8 Fig.10). Expanded format Figure shows cascaded FIFOs providing capacity words bits. Figure shows signals nodes both FIFOs after application pulse, when both FIFOs initially empty. After ripple through delay, data arrives output FIFOA. being HIGH, DORA pulse generated. requirements satisfied DORA pulse width timing between rising edge DORA QnA. After second ripple through delay, data arrives output FIFOB. Figure shows signals nodes both FIFOs after application pulse, when both FIFOs initially full. After bubble-up delay DIRB pulse generated, which acts pulse FIFOA. word transferred from output FIFOA input FIFOB. requirements pulse FIFOA satisfied pulse width DORB. After second bubble-up delay empty space arrives DnA, which time DIRA goes HIGH. Figure shows waveforms external nodes both FIFOs during complete shift-in shift-out sequence.
September 1993
Philips Semiconductors
Product specification
5-Bit 64-word FIFO register; 3-state
74HC/HCT7404
handbook, full pagewidth
DATA OUTPUT
7404
FIFO
7404
FIFO
DATA INPUT
MGA682
Fig.21 Cascading increased word capacity; word bits.
Note Fig.21 "7404" easily cascaded increase word capacity without external circuitry. cascaded format, necessary communications handled FIFOs. Figures demonstrate intercommunication timing between FIFOA FIFOB. Figure provides overview pulses timing cascaded FIFOs, when shifted full shifted empty again.
September 1993
Philips Semiconductors
Product specification
5-Bit 64-word FIFO register; 3-state
74HC/HCT7404
handbook, full pagewidth
ripple through delay
ripple through delay
MGA666
Fig.22 FIFO FIFO communication; input timing under empty condition.
Notes Fig.22 FIFOA FIFOB initially empty, held HIGH anticipation data Load word into FIFOA; pulse applied, results pulse Data-out A/data-in transition; valid data arrives FIFOA output stage after specified delay flag, meeting data input set-up requirements FIFOB DORA pulse HIGH; (ripple through delay after LOW) data unloaded from FIFOA result data output ready pulse, data shifted into FIFOB DIRB LOW; flag indicates input stage FIFOB busy, shift-out FIFOA complete DIRB HIGH automatically; input stage FIFOB again able receive data, held HIGH anticipation additional data DORB goes HIGH; (ripple through delay after LOW) valid data present propagation delay later FIFOB output stage.
September 1993
Philips Semiconductors
Product specification
5-Bit 64-word FIFO register; 3-state
74HC/HCT7404
handbook, full pagewidth
bubble delay
bubble delay
MGA667
Fig.23 FIFO FIFO communication; output timing under full condition.
Notes Fig.23 FIFOA FIFOB initially full, held HIGH anticipation shifting data empty location bubbles-up Unload word from FIFOB; pulse applied, results pulse DIRB pulse HIGH; (bubble-up delay after LOW) data loaded into FIFOB result pulse, data shifted FIFOA DORA LOW; flag indicates output stage FIFOA busy, shift-in FIFOB complete DORA HIGH; flag indicates valid data again available FIFOA output stage, held HIGH, awaiting bubble-up empty location DIRA goes HIGH; (bubble-up delay after LOW) empty location present input stage FIFOA.
September 1993
Philips Semiconductors
Product specification
5-Bit 64-word FIFO register; 3-state
74HC/HCT7404
handbook, full pagewidth
sequence
sequence
sequence
sequence
sequence
sequence
INPUT DORB OUTPUT
(14)
OUTPUT
DIRB OUTPUT
(13)
DORA OUTPUT
(12)
OUTPUT (10) DIRA OUTPUT
INPUT
(11)
INPUT
INPUT
MGA687
Fig.24 Waveforms showing functionality intercommunication between FIFOs (refer Fig.19).
Note Fig.24 Sequence (both FIFOS empty, starting SHIFT-IN process) After pulse been applied FIFOA FIFOB empty. flags FIFOA FIFOB valid data being present outputs. flags HIGH FIFOs being ready accept data. held HIGH pulses applied (1). These pulses allow data words ripple through output stage FIFOA input stage FIFOB (2). When data arrives output FIFOB, DORB pulse generated (3). When goes LOW, first shifted second ripples through output after which DORB goes HIGH (4).
September 1993
Philips Semiconductors
Product specification
5-Bit 64-word FIFO register; 3-state
Sequence (FIFOB runs full) After pulse, series pulses applied. When words shifted DIRB remains FIFOB being full (5). DORA goes FIFOA being empty. Sequence (FIFOA runs full) When words shifted DORA remains HIGH valid data remaining output FIFOA. remains HIGH, being polarity 65th data word (6). After 128th pulse, remains both FIFOs full (7). Additional pulses have effect. Sequence (both FIFOs full, starting SHIFT-OUT process) held HIGH pulses applied (8). These pulses shift words thus allow empty locations bubble-up input stage FIFOB, proceed FIFOA (9). When first empty location arrives input FIFOA, DIRA pulse generated (10) word shifted into FIFOA. made second empty location reaches input stage FIFOA, after which DIRA remains HIGH (11).
74HC/HCT7404
Sequence (FIFOA runs empty) start sequence FIFOA contains valid words words being shifted word being shifted sequence additional series pulses applied. After pulses, words from FIFOA shifted into FIFOB. DORA remains (12). Sequence (FIFOB runs empty) After next pulse, DIRB remains HIGH input stage FIFOB being empty. After another pulses, DORB remains both FIFOs being empty (14). Additional pulses have effect. last word remains available output PACKAGE OUTLINES "74HC/HCT/HCU/HCMOS Logic Package Outlines".
September 1993

74HC/HCT7404 5-Bit 64-word FIFO register; 3-state Product specifi

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