R1100 R1100 16-Bit RISC Microcontroller User's Manual R
|
|
|
Top Searches for this datasheet
RISC Controller
R1100
R1100
16-Bit RISC Microcontroller User's Manual
RISC Controller
Semiconductor Co., http:\\www.rdc.com.tw Tel. 886-3-666-2866 886-3-563-1498
Semiconductor Subject change without notice
Contents
RISC Controller
R1100
page Features Block Diagram Configuration Description Basic Application System Block Oscillator Characteristics Read/Write timing Diagram Execution Unit General Register Segment Register Instruction Pointer Status Flags Register Address Generation- Peripheral Control Block Register System Clock Reset Interface Unit 12.1 Memory Interface 12.2 Data 12.3 Wait States 12.4 Hold Chip Select Unit- 13.1 13.2 13.3 MCSx 13.4 PCSx Interrupt Controller Unit 14.1 Master Mode Slave Mode 14.2 Interrupt Vector, Type Priority 14.3 Interrupt Request 14.4 Interrupt Acknowledge 14.5 Programming Register Unit
Semiconductor Subject change without notice
RISC Controller
R1100
15.1 Operation 15.2 External Requests Timer Control Unit- 16.1 Timer/Counter Unit Output Mode- Asynchronous Serial Port- Synchronous Serial Port Unit 19.1 Multi-Function list Table Instruction Opcodes Clock Cycle- 20.1 R1100 Execution Timings Characteristica each DC/AC Characteristics Package Information-100 Revision History -102 Appendix -103
Semiconductor Subject change without notice
RISC Controller
R1100
High Speed 16-Bit Microcontroller
Features
Five-stages pipeline RISC architecture Integrated PLL(*1~*8) Maximum frequency MHz; External bus, Internal core same clock base interface Multiplexed address Data Supports direct address [A19 8-bit 16-bit external dynamic access byte memory address space byte space Software compatible with generic 80C186 microprocessor Support Asynchronous serial channels with hardware handshaking signals. External bus, Internal core Supports pins Three independent 16-bit timers independent programmable watchdog timer Interrupt controller with seven maskable external interrupts non-maskable external interrupt(NMI) independent channels Programmable chip-select logic Memory cycle decoder Programmable wait-state generator output volt level input volt volt tolerance. 3.3V operation voltage Support same clock base
Semiconductor Subject change without notice
RISC Controller
R1100
2.Block Diagram
INT2/INTA0 INT1/SELECT CLKOUTA INT3/INTA1/IRQ INT4 CLKOUTB INT0 TMROUT0 TMROUT1 TMRIN0 TMRIN1 DRQ0 DRQ1
Clock Power Management
Interrupt Control Unit
Timer Control Unit
Unit
LCS/ONCE0 MCS3/RFSH MCS2-MCS0 UCS/ONCE1 PCS3-PCS0 PCS5/A1 PCS6/A2
Chip Select Unit PSRAM Control Unit
Instruction Queue (64bits) Instruction Decoder
Control Signal
Micro
Unit
ARDY SRDY S2~S0 DT/R
Refresh Control Unit
Register File General, Segment, Eflag Register
Address Asynchronous Serial Port
HOLD HLDA S6/CLKDIV2
Interface Unit
(Special, Logic, Adder, BSF)
Execution Unit
Synchronous Serial Interface
SCLK A19~A0 AD15~AD0
SDATA SDEN0 SDEN1
BHE/ADEN
Semiconductor Subject change without notice
RISC Controller
R1100
3.Pin Configuration (PQFP)
S6/CLKDIV2/PIO29
SDATA/PIO21
RXD/PIO28
TXD/PIO27
UZI/PIO26
AD15
AD14
AD13
AD12
AD11
AD10
SDEN1/PIO23 SDEN0/PIO22 SCLK/PIO20
BHE/ADEN/TRST
DRQ0/PIO12 DRQ1/PIO13 TMRIN0/PIO11 TMROUT0/PIO10 TMROUT1/PIO1 TMRIN1/PIO0 MCS3/RFSH/PIO25 MCS2/PIO24 PCS0/PIO16 PCS1/PIO17 PCS2/PIO18 PCS3/PIO19 PCS5/A1/PIO3 PCS6/A2/PIO2 LCS/ONCE0 UCS/ONCE1 INT0 INT1/SELECT INT2/INTA0/PIO31 INT3/INTA1/IRQ INT4/PIO30 MCS1/PIO15
ARDY CLKOUTA CLKOUTB A19/PIO9 A18/PIO8 A17/PIO7
R1100
Microcontroller
SRDY/PIO6
DT/R/PIO4
DEN/PIO5
MCS0/PIO14
HOLD
HLDA
Semiconductor Subject change without notice
(LQFP)
S6/CLKDIV2/PIO29
SDEN0/PIO22 RXD/PIO28 AD15 AD14 AD13 AD12 AD11 AD10
SDEN1/PIO23 TXD/PIO27 UZI/PIO26
SDATA/PIO21
Semiconductor Subject change without notice
RISC Controller
SCLK/PIO20 ARDY CLKOUTA CLKOUTB A19/PIO9 A18/PIO8 A17/PIO7
DRQ0/PIO12 DRQ1/PIO13 TMRIN0/PIO11 TMROUT0/PIO10 TMROUT1/PIO1 TMRIN1/PIO0 MCS3/RFSH/PIO25 MCS2/PIO24 PCS0/PIO16 PCS1/PIO17 PCS2/PIO18 PCS3/PIO19 PCS5/A1/PIO3 PCS6/A2/PIO2 LCS/ONCE0 UCS/ONCE1 INT0 INT1/SELECT INT2/INTA0/PIO31 INT3/INTA1/IRQ
BHE/ADEN/TRST
R1100
SRDY/PIO6 HLDA HOLD
INT4/PIO30
DEN/PIO5
DT/R/PIO4
MCS0/PIO14
MCS1/PIO15
R1100
name AD10 AD11 AD12 AD13 AD14 AD15 /PIO29
RISC Controller
R1100
R1100 PQFP LQFP Pin-Out table
PQFP name LQFP PQFP
LQFP
HLDA HOLD SRDY/PIO6 /PIO4 /PIO5
/PIO26
TXD/PIO27 RXD/PIO28 SDATA/PIO21 SDEN1/PIO23 SDEN0/PIO22 SCLK/PIO20
MCS0 /PIO14 /PIO15
NT4/ PIO30 NT3/ INTA1 NT2/ INTA0 /PIO31 NT1/ SELECT
CNCE1 LCS/ CNCE0
ADEN TRST
ARDY
CLKOUTA CLKOUTB A19/PIO9 A18/PIO8 A17/PIO7
PCS6 /A2/PIO2 PCS5 /A1/PIO3
PCS3 /PIO19 PCS2 /PIO18 PCS1 /PIO17 PCS0 /PIO16 MCS2
MCS3 RFSH /PIO25
TMRI N1/PIO0 TMROUT1/PIO1 TMROUT0/PIO10 TMRI N0/PIO11 DRQ1/PIO13 DRQ0/PIO12
Semiconductor Subject change without notice
RISC Controller
R1100
Type
Input Input Input* Input Output Output System ground. Reset input. When asserted, immediately terminates operations, clears internal registers logic, address transfers reset address FFFF0h. Input oscillator amplifier. Output from inverted oscillator amplifier. Clock output CLKOUTA operation same crystal input frequency (X1). CLKOUTA remains active during reset hold conditions. Clock output CLKOUTB operation same crystal input frequency (X1). CLKOUTB remains active during reset hold conditions. When enable JTAG interface,this active TDI.
Description No.(PQFP)
Symbol
Description
System power: +3.3 volt power supply.
CLKOUTA
CLKOUTB
Output
Synchronous Serial Port Interface
SDEN1/PIO23 SDEN0/PIO22 SCLK/PIO20 SDATA/PIO21 Serial data enables. Active-high. These pins enable data Output/Input transfers synchronous serial interface. SDEN1 port1, SDEN0 port0. Synchronous serial data clock. This provides shift clock Output/Input external device. SCLK=X1/2, depending register setting. This held high during UART inactive. Synchronous serial data. This provides shift data Input/Output receives serial data from external device. Output/Input Input Transmit data. This transmits asynchronous serial data from UART microcontroller. Receive data. This receives asynchronous serial data. high enable/address enable. During memory access, (AD0 encodings indicate what type cycle. asserted during keeps asserted This floating during hold reset. (AD0 Encodings Type Cycle Word transfer High byte transfer (D15-D8) byte transfer (D7-D0) Refresh Output/Input ADEN TRST address portion enabled disabled LMCS UMCS register during cycle access, ADEN held high during power-on reset. ADEN with internal weak pull-up register, external pull-up register required. always drives both address data during cycle access, ADEN with external pull-low resister during reset. This active TRST when JTAG interface enabled. Write strobe. This indicates that data
Asynchronous Serial Port Interface
TXD/PIO27
Interface
Semiconductor Subject change without notice
Output
RISC Controller
R1100
written into memory device. active during write cycle, floats during hold reset. Read Strobe. Active signal which indicates that microcontroller performing memory read cycle. floats during hold reset. Address latch enable. Active high. This indicates that address output bus. Address guaranteed valid trailing edge ALE. This tri-stated during ONCE mode never floating during hold reset. Asynchronous ready. This performs microcontroller that address memory space device will complete data transfer. ARDY accepts rising edge that asynchronous CLKOUTA active high. falling edge ARDY must synchronized CLKOUTA. ARDY high, microcontroller always asserted ready condition. ARDY used, this yield control SRDY. Both SRDY ARDY should tied high system need assert wait state externality. cycle status. These pins encoded indicate status. used memory indicator. used indicator. These pins floating during hold reset. Cycle Encoding Description Cycle Interrupt acknowledge Read data from Write data Halt Instruction fetch Read data from memory Write data memory Passive
Output
Output
ARDY
Input
Output
23-37
A19/PIO9 A18/PIO8 A17/PIO7 A16-A2
Address bus. Non-multiplexed memory address. one-half CLKOUTA period earlier than bus. Output/Input These pins high-impedance during hold reset.
78,80,82,84,86,88 91,94 79,81,83,85,87,90 93,95
AD0-AD7 AD8-AD15
multiplexed address data memory accessing. address present during clock phase, data phase t2-t4 cycle. address phase disabled when Input/Output ADEN with external pull-low resister during reset. high-impedance state during hold reset condition this also used load system configuration information (with pull-up pull-Low resister) into register when reset input from high. Write high byte. This indicates high byte data (AD15-AD8) written memory Output device. This floating during reset hold.
Semiconductor Subject change without notice
RISC Controller
R1100
Output Write byte. This indicates byte data (AD7-AD0) written memory device. This floating during reset hold. hold acknowledge. Active high. microcontroller will issue HLDA response HOLD request external master When microcontroller hold status (HLDA high), AD15-AD0, A19-A0, floating, PCS6 PCS5 MCS3 MCS0 PCS3 PCS0 will driven high. After HOLD detected being low, microcontroller will lower HLDA. Hold request. Active high. This indicates that another Input master requesting local bus. Synchronous ready. This performs microcontroller that address memory space device will complete data transfer. SRDY accepts falling edge that asynchronous CLKOUTA active high. SRDY accomplished elimination one-half clock period Input/Output required internally synchronize ARDY. SRDY high microcontroller always asserted ready condition. SRDY used, this yield control ARDY.
HLDA
Output
HOLD
SRDY/PIO6
Both SRDY ARDY should tied high system doesn't need assert wait state externality.
Data transmit receive. This indicates direction Output/Input data flow through external data-bus transceiver. low, /PIO4 microcontroller receives data. When DT/R asserted high, microcontroller writes data data bus. Data enable. This provided data transceiver output enable. asserted during memory access. Output/Input /PIO5 driven high when changes state. floating during hold reset condition. cycle status bit6/clock divided feature, this indicate microcontroller-initiated cycle high indicate DMA-initiated cycle during CLKDIV2 feature. internal clock CLKDIV2 /PIO29 Output/Input microcontroller external clock which divided (CLKOUTA, CLKOUTB=X1/2), this held during power-on reset. sampled rising edge Upper zero indicate. This logical inverted Output/Input /PIO26 A19-A16. asserts held throughout cycle.
Chip Select Unit Interface
MCS0 /PIO14 MCS1 /PIO15 MCS2 /PIO24 MCS3 RFSH /PIO25 ONCE1 Midrange memory chip selects. feature, these pins active when enable MMCS(A6h) register access memory. address ranges programmable. Output/Input MCS3 MCS0 held high during hold. When programming LMCS(A6h) register, pin69 RFSH auto refresh PSRAM. Output/Input Upper memory chip select/ONCE request
Semiconductor Subject change without notice
RISC Controller
R1100
feature, this acts when system accesses defined portion memory block upper 512K bytes (80000h-FFFFFh) memory region. default acted address region from F0000h FFFFFh after power-on reset. address range acting programmed software. Lower memory chip select/ONCE mode request feature, this acts when microcontroller accesses Output/Input defined portion memory block lower 512K (00000h-7FFFFh) memory region. address range acting programmed software. Peripheral chip selects/latched address bit. feature, these pins when microcontroller accesses fifth sixth region peripheral memory (I/O memory space). base address programmable. These pins assert with address floated during Output/Input hold. latched address feature. These pins output latched address when cleared auxiliary register. retains previous latched data during hold. Peripheral chip selects. These pins when microcontroller accesses defined memory area peripheral memory block (I/O memory address). accessed, base address programmed region Output/Input 00000h 0FFFFh. memory address access, base address located byte memory address region. These pins assert with multiplexed address floated during hold.
ONCE0
PCS6 /A2/PIO2 PCS5 /A1/PIO3
PCS3 /PIO19 PCS2 /PIO18 PCS1 /PIO17 PCS0 /PIO16
Interrupt Control Unit Interface
Nonmaskable Interrupt. highest priority hardware interrupt nonmaskable. When this asserted (NMI transition from high), microcontroller Input always transfers address location specified nonmaskable interrupt vector microcontroller interrupt vector table. must asserted least CLKOUTA period guarantee that interrupt recognized. Maskable interrupt request high. This indicates that interrupt request occurred. microcontroller will jump INT4 address vector execute service routine INT4/PIO30 Input/Output INT4 enable. interrupt input configured either edge- level-triggered. requesting device must hold INT4 until request acknowledged guarantee interrupt recognition. Maskable interrupt requests 3/interrupt acknowledge 1/slave interrupt request. INT3 feature, except difference interrupt line interrupt address vector, function INT3 same INT4. INT3/ INTA1 /IRQ Input/Output INTA1 feature, cascade mode special fully-nested mode, this corresponds INT1. feature, when microcontroller slave device, this issues interrupt request master interrupt controller.
Semiconductor Subject change without notice
RISC Controller
R1100
Maskable interrupt requests 2/interrupt acknowledge INT2 feature, except difference interrupt line interrupt INT2/ INTA /PIO31 Input/Output address vector, function INT2 same INT4. INTA feature, cascade mode special fully-nested mode, this corresponds INT0. Maskable interrupt requests 1/slave select. INT1 feature, except difference interrupt line interrupt address vector, function INT1 same INT4. SELECT feature, when microcontroller slave Input/Output device, this driven from master interrupt controller INT1/ SELECT decoding. This acts indicate that interrupt appears address data bus. INT0 must before SELECT acts when interrupt type appears bus. Maskable interrupt request Except interrupt line INT0 Input interrupt address vector, function INT0 same INT4.
Timer Control Unit Interface
Timer input. These pins clock control signal input, which depend upon programmed timer mode. After TMRIN1/PIO0 Input/Output internally synchronizing high transitions TMRIN, TMRIN0/PIO11 timer controller increments. These pins must pull-up being used. Timer output. Depending timer mode select these pins provide single pulse continuous waveform. duty cycle TMROUT1/PIO1 Output/Input waveform programmable. These pins floated TMROUT0/PIO10 during hold reset.
Unit Interface
DRQ1/PIO13 DRQ0/PIO12 request. These pins asserted high external device when device ready channel channel Input/Output perform transfer. These pins level-triggered internally synchronized. signals must remain until finish serviced latched.
Notes:
1.When enable Data register, there definition pins (pin76) PIO13 when enable Data register. PIO1, PIO10, PIO22, PIO23 inputted with pull-down, PIO4 PIO9 pin. example, DRD1/PIO13
2.The status during Power-On reset
normal operation others inputted with pull-up.
Semiconductor Subject change without notice
RISC Controller
R1100
Basic Application System Block
Flash
AD15-AD0 A19-A1 Data(16) Address
SRAM
RS232 Level Converter
Serial port0
Data(16) Address
R1100
Timer0-1 INTx
Peripheral
Data Address
100K
PCSx
BASIC APPLICATION SYSTEM BLOCK
Flash High Byte AD15-AD0 SRAM High Byte
RS232 Level Converter
Byte D7-D0 Address
D15-D8 Address
A19-A1
Byte D7-D0 Address
Serial port0
D15-D8
R1100
Timer0-1 INTx
Address
Peripheral Data
100K PCSx
Address
BASIC APPLICATION SYSTEM BLOCK
Semiconductor Subject change without notice
RISC Controller
R1100
Flash
DT/R AD15-AD0 D15-D0 Data(16) Address
Transciver
SRAM
RS232 Level Converter
Serial port0
Data(16) A19-A16 A19-A1 Address
R1100
Timer0-1 INTx
Latch
Peripheral
Data Address
100K
PCSx
BASIC APPLICATION SYSTEM BLOCK
Oscillator Characteristics
R1100
fundamental -mode crystal: 10pF 20pF 10pF 20pF Don't care; Don't care
third-overtone mode crystal: 200pf mega-ohm 8.2uH (25MHz) 12uH (20MHZ)
Semiconductor Subject change without notice
RISC Controller
R1100
Read/Write timing Diagram
CLKOUTA
A19:A0
ADDRESS
AD15:AD0
ADDRESS
DATA
UCS,LCS
PCSx,MCSX
DT/R
S2:S0
STATUS
READ CYCLE
Semiconductor Subject change without notice
RISC Controller
R1100
CLKOUTA AD15:AD0 A19:A0
Addr. Address
Data
UCS, MCS,
with wait state (Read Cycle)
Semiconductor Subject change without notice
RISC Controller
R1100
CLKOUTA
A19:A0
ADDRESS
AD15:AD0
ADDRESS
DATA
WHB,WLB
UCS,LCS
PCSx,MCSX
DT/R
S2:S0
STATUS
WRITE CYCLE
Semiconductor Subject change without notice
RISC Controller
R1100
CLKOUTA AD15:AD0 A19:A0
Addr. Address
Data
UCS, MCS,
with wait State (Write Cycle)
Semiconductor Subject change without notice
RISC Controller
R1100
Execution Unit
General Register R1100 eight 16-bit general registers. AX,BX,CX,DX subdivided into 8-bit register (AH,AL,BH, BL,CH,CL,DH,DL). Functions these registers described follows.
Word Divide Word Multiply, Word operation. Byte Divide Byte Multiply, Byte Decimal Arithmetic, Translate operation. Byte Divide Byte Multiply operation. Translate operation. Loops, String operation Variable Shift Rotate operation. Word Divide Word Multiply, Indirect operation Stack operations (POP, POPA, POPF, PUSH, PUSHA, PUSHF) General-purpose register which used determine offset address operands Memory. String operations String operations
High
Data Group
Accumulator Base Register Count/Loop/Repeat/Shift Data Stack Pointer Base Pointer Source Index Destination Index
Index Group Pointer
GENERAL REGISTERS
Segment Register R1100 four 16-bit segment registers, segment registers contain base addresses (starting location) these memory segments, they immediately addressable code (CS), data ES), stack (SS) memory. (Code Segment) register points current code segment, which contains instruction fetched. default location memory space instruction 64K. initial value register 0FFFFh.
Semiconductor Subject change without notice
RISC Controller
R1100
(Data Segment) register points current data segment, which generally contains program variables. register initialize 0000H. (Stack Segment register points current stack segment, which stack operations, such pushes pops. stack segment used temporary space. register initialize 0000H. (Extra Segment) register points current extra segment which typically data storage, such large string operations large data structures. register initialize 0000H.
Code Segment Data Segment Stack Segment Extra Segment
SEGMENT REGISTERS
Instruction Pointer Status Flags Register (Instruction Pointer) 16-bit register contains offset next instruction fetched. Software direct access register. Itis updated Interface Unit. changed, saved restored result
program execution. register initialize 0000H CS:IP starting execution address 0FFFF0H.
Processor Status Flags Registers
FLAGS Reset Value 0000h
Reserved
These flags reflect status after Execution Unit executed. 15-12 Reserved Overflow Flag. arithmetic overflow occurred, this flag will set. Direction Flag. this flag set, string instructions increment address process. cleared, string instructions decrement address process. Refer instructions clear flag. Interrupt-Enable Flag. Refer instructions clear flag. enables maskable interrupt request. disables maskable interrupt request.
Semiconductor Subject change without notice
RISC Controller
R1100
Trace Flag. enable single-step mode debugging; Clear disable single-step mode. application program sets flag using POPF IRET instruction, debug exception generated after instruction (The automatically generates interrupt after each instruction) that follows POPF IRET instruction. Sign Flag. this flag set, high-order result operation 1,indicating negative. Zero Flag. result operation zero, this flag set. Reserved Auxiliary Flag. this flag set, there been carry from nibble high borrow from high nibble nibble general-purpose register. Used operation. Reserved. Parity Flag. result low-order bits operation even parity; this flag set. Reserved Carry Flag. set, there been carry borrow into high-order instruction result.
Address generation
Execution Unit generates 20-bit physical address Interface Unit Address Generation. Memory organized sets segments. Each segment contains bits value. Memory addressed using two-component address that consists 16-bit segment 16-bit offset. Physical Address Generation figure describes logical address transfers physical address.
Shift left bits
Segment Base Logical Address Offset
Physical Address
Memory
Physical Address Generation
Semiconductor Subject change without notice
RISC Controller
R1100
program register. starts
Peripheral Control Block Register
peripheral control block mapped into either memory space FF00h space when reset microprocessor. following table definition peripheral Control Block Register, detail description will arrange relation Block Unit.
Offset (HEX)
Register Name Peripheral Control Block Relocation Register Reset Configuration Register Processor Release Level Register PDCON Register Control Register Transfer Count Register Destination Address High Register Destination Address Register Source Address High Register Source Address Register Control Register Transfer Count Register Destination Address High Register Destination Address Register Source Address High Register Source Address Register Auxiliary Register Midrange Memory Chip Select Register Peripheral Chip Select Register Memory Chip Select Register Upper Memory Chip Select Register Serial Port Baud Rate Divisor Register Serial Port Receive Register Serial Port Transmit Register Serial Port Status Register Serial Port Control Register Data Register Direction Register Mode Register Data Register Direction Register Mode Register Timer Mode Control Register Timer Maxcount Compare Register Timer Count Register
Page
Offset (HEX)
Register Name Timer Mode Control Register Timer Maxcount Compare Register Timer Maxcount Compare Register Timer Count Register Timer Mode Control Register Timer Maxcount Compare Register Timer Maxcount Compare Register Timer Count Register Serial Port Interrupt Control Register Watchdog Timer Control Register INT4 Control Register INT3 Control Register INT2 Control Register INT1 Control Register INT0 Control Register Interrupt Control Register Interrupt Control Register Timer Interrupt Control Register Interrupt Status Register Interrupt Request Register In-service Register Priority Mask Register Interrupt Mask Register Poll Status Register Poll Register End-of-Interrupt Interrupt Vector Register Synchronous Serial Receive Register Synchronous Serial Transmit Register Synchronous Serial Transmit Register Synchronous Serial Enable Register Synchronous Serial Status Register PLLCON Register
Page
Semiconductor Subject change without notice
RISC Controller
R1100
Peripheral Control Block Relocation Register:
M/IO
Offset Reset Value 20FFh
peripheral control block mapped into either memory space programming this register. When other chip selects PCSx MCSx programmed zero wait states ignore external ready, PCSx MCSx overlap control block. Reserved Slave/Master Configures interrupt controller Master mode, Slaved mode Reserved Memory/IO space. reset, this start FF00h space. peripheral control block (PCB) located memory space. located space. 11-0 R19-R8 Relocation Address Bits upper address bits base address. lower eight bits default 00h. When mapped space, R19-R16 must programmed 0000b.
Processor Release Level Register
Offset Reset Value
Read only register that specifies processor release version identify number 15-0: C5D9h
Semiconductor Subject change without notice
RISC Controller
R1100
System Clock Block
PSEN(F0h.15) PWD(46h.15)
enable/disable enable/disable
Microprocessor Internal Clock
CLKIN
CLKIN CLKIN/2
CLOCK Divisior (CLK/2-CLK/128)
CAD(F0h.8)
CLKOUTA
CLKIN/2 Select
Divisor Select
CAF(F0h.9)
F2-F0(F0h.2-F0h.0) S6/CLKDIV2 CBD(F0h.10) CBF(F0h.11) CLKOUTB
System Clock
Configuration Register
Reserve
Offset Reset Value 05Fh
Reserve
PRS1 PRS0 POS1 POS0
FBS4 FBS3 FBS2
FBS1 FBS0
initial factor 1(CLKIN=Crystal freguency). factctor adjusted changing value 15-12 Reserved 11-10 Pre-Divider (PRS) Programming signals pre-divider. Post-Divider (POS) Programming signals post-divider. Reserved Feedback Divider (FBS) Programming signals feedback divider. 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111
Semiconductor Subject change without notice
RISC Controller
R1100
CLKOUT FREF
FREF input frequency), 2MHz FREF 24MHz 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111
CKOUT Internal/output frequency, 00000 00001 00010 00011 00100 00101 00110 00111 Note1 Note2 N=3-32
FREF 280MHz FREF MHz, FREF MHz, FREF
Note3 frequency working range crystal MHz.
Power-Save Control Register
PSEN SALEn
Offset Reset Value 0000h
PSEN Enable Power-save Mode. This cleared hardware when external interrupt occurs. This notchanged when software interrupts (INT instruction) exceptions occurs. enable power-save mode divides internal operating clock value F2-F0. Bit14-12: Reserved CBF, CLKOUTB Output Frequency selection. CLKOUTB output frequency same crystal input frequency. CLKOUTB output frequency from clock divisor, which frequency same that microprocessor
Semiconductor Subject change without notice
RISC Controller
R1100
internal clock. CBD, CLKOUTB Drive Disable Disable CLKOUTB. This will three-state. Enable CLKOUTB. CAF, CLKOUTA Output Frequency selection. CLKOUTA output frequency same crystal input frequency. CLKOUTB output frequency from clock divisor, which frequency same that microprocessor internal clock CAD, CLKOUTA Drive Disable. Disable CLKOUTA. This will three-state. Enable CLKOUTA. Insert delay. more added,the should cycle. Normal cycle.ALE without delay. 7,6,5,3 Reserved 2-0: Clock Divisor Select. -Divider Factor Divide Divide Divide Divide Divide Divide Divide Divide
Semiconductor Subject change without notice
Reset
RISC Controller
R1100
Processor initialization accomplished with activation pin. reset processor, this should held least seven oscillator periods. Reset Status Figure shows status others relation pins. When goes from high state input (with weakly pull-up pull-down) will latched each will perform individual function. AD15-AD0 will latched into register F6h. ONCE1 ONCE will enter ONCE mode (All pins will floating except when with pull-low resisters. input clock will divided when CLKDIV2 with pull-low resister. AD15-AD0 will drive address phase during cycle ADEN with pull-low resister
Semiconductor Subject change without notice
CLKOUTA
RISC Controller
R1100
A19-A0 (float)
ffff0
(input)
AD15-AD0
(input)
fff0
(float) (float)
(input)
(input)
(float)
DT/R (float)
S2-S0
(float)
Reset Status
Reset Configuration Register
Offset Reset Value AD15-AD0
,Reset Configuration AD15 AD0. AD15 must with weakly pull-up pull-down resistors correspond contents when AD15-AD0 latched into this register during goes from high. value reset configuration register provides system information when software read this register. This register read only contents remain valid until next processor reset.
Semiconductor Subject change without notice
RISC Controller
R1100
Interface Unit
interface unit drives address, data, status control information define cycle. A19-A0 non-multiplex memory address. AD15-AD0 multiplexed address data memory accessing. encoded indicate status, which described Description table page Basic Application System Block (page Read/Write Timing Diagram (page describe basic operation.
12.1 Memory interface memory space consists bytes (512k 16-bit port) space consists bytes (32k 16-bit port). Memory devices exchange information with during memory read, memory write instruction fetch cycles. read write cycles separate address space. Only IN/OUT instruction access address space, information must transferred between peripheral device register. first bytes space accessed directly instructions. entire bytes address space accessed indirectly, through register. instructions always force address A19-A16 level.
FFFFFH
Memory Space
Bytes 0FFFFH
Space
Bytes
Memory Space
512K Bytes FFFFF FFFFD
512K Bytes FFFFE FFFFC
A19:1
D15:8
D7:0
Physical Data Models
12.2 Data memory address space data physically implemented dividing address space into banks 512k
Semiconductor Subject change without notice
RISC Controller
R1100
bytes. Each bank connects lower half data contains even-addressed bytes (A0=0). other bank connects upper half data contains odd-addressed bytes (A0=1). determine whether bank both banks participate data transfer.
12.3 Wait States
SRDY
control registers
ARDY CLKOUTA CLKOUTA
Rising Edge
Wait State Counter
Ready
Falling Edge
CLKOUTA
Wait-state block Diagram
Ready active High UMCS default is"0", required external ready power-on reset. wait state counter value located control registers chip select unit.
Wait states extend data phase cycle. ARDY SRDY input with level will insert wait states. bit=0, user also insert wait state programming internal chip select registers. UMCS offset 0A0h) default low, each ARDY SRDY should ready state (with pull high resistor) when it's power reset external reset. wait state counter value decided R3,R1,R0 bits each chip select register. There five group R3,R1,R0 bits registers offset A0h, A2h, A4h, A6h, A8h. Each group independent.
12.4 Hold When hold requested HOLD active high) another master, microprocessor will issue HLDA
Semiconductor Subject change without notice
RISC Controller
R1100
response HOLD request When microprocessor hold status (HLDA high), AD15-AD0, A19-A0, floating, PCS6 PCS5 MCS3 MCS0 PCS3 PCS0 will drive high. After HOLD detected being low, microprocessor will lower HLDA.
Case Case
CLKOUTA
HOLD
HLDA
AD15:AD0
Floating Floating Floating
A19:A0
Floating
Floating
Floating
DT/R
Floating
S2:S0
Floating Floating
HOLD ENTER WAVEFORM
Semiconductor Subject change without notice
RISC Controller
R1100
Case Case
CLKOUTA
HOLD
HLDA
AD15:AD0
Floating Floating Floating
DATA
A19:A0
ADDRESS
Floating
Floating
Floating
DT/R
Floating
S2:S0
Floating Floating
HOLD LEAVE WAVEFORM
Semiconductor Subject change without notice
RISC Controller
R1100
Chip Select Unit
Chip Select Unit provides programmable chip select pins access specific memory peripheral device. chip selects programmed through five peripheral control registers (A0h, A2h, A4h, A6h, A8h). chip selects insert wait states programming peripheral control register.
13.1 default active reset program code access. memory active range upper 512k (80000h FFFFFh), which programmable. default memory active range F0000h FFFFFh). actives drive four CLKOUTA oscillators wait state inserts. There three wait-states insert active cycle reset.
Upper Memory Chip Select Register
Offset Reset Value :F03Bh
Reserved 14-12 LB2-LB0, Memory block size selection chip select pin. chip select active region configured LB2-LB0. default memory block size from F0000h FFFFFh. LB2, LB1, Memory Block size Start address, Address 11-8 Reserved Disable Address. ADEN held high rising edge then valid enable/disable address phase bus. ADEN held rising edge always drives address data. Disable address phase AD15 cycle when asserted. Enable address phase AD15 cycle when asserted. 6-4: Reserved Ready Mode. This used configure ready mode chip select. external ready ignored. external ready required. 3,1,0 R3,R1,R0, Wait-State value. When inserted wait-state into access memory Semiconductor Subject change without notice -64k 128k 256k 512k F0000h E0000h C0000h 80000h FFFFFh FFFFFh FFFFFh FFFFFh
area.
RISC Controller
R1100
Wait States
13.2 lower 512k bytes (00000h-9FFFFh) memory region chip selects. memory active range programmable, which default size reset. register must programmed first before access target memory range. active reset, read write access register activates this pin.
Memory Chip Select Register
Offset Reset Value
Reserved 14-12 UB2-UB0, Memory block size selection chip select chip select active region configured UB2-UB0. active reset, read write access (LMCS) register activates this pin. UB2, UB1, Memory Block size Start address, Address -64k 128k 256k 512k 00000h 00000h 00000h 00000h 0FFFFh 1FFFFh 3FFFFh 7FFFFh
11-8 Reserved Disable Address. ADEN held high rising edge then valid enable/disable address phase bus. ADEN held high rising edge always drives address data. Disable address phase AD15 cycle when asserted. Enable address phase AD15 cycle when asserted. PSE, PSRAM Mode Enable. This used enable PSRAM support chip select memory space. refresh control unit registers E0h,E2h,E4h must configured auto refresh before PSRAM support enabled. Semiconductor Subject change without notice
5-3: Reserved
RISC Controller
R1100
PSRAM support enable PSRAM support disable
Ready Mode. This used configure ready mode chip select. external ready ignored. external ready required. R1-R0, Wait-State value. When insert wait-state into access memory area. (R1,R0) (0,0) (R1,R0) (1,0) wait-state wait-state (R1,R0) (0,1) (R1,R0) (1,1) wait-state wait-state
13.3 MCSx memory block MCS4 MCS0 located anywhere within bytes memory space, exclusive areas associated with chip selects. maximum MCSx active memory range 512k bytes. chip selects programmed through registers A8h, these select pins active reset. Both registers must accessed with read write activate MCS4 MCS0 There aren't default value registers, must programmed first before MCS4 MCS0 active.
Midranage Memory Chip Select Register
Offset Reset Value
BA19 BA13
15-7 BA19-BA13, Base Address. BA19-BA13 correspond bits 19-13 bytes (20-bits) programmable base address chip select block. bits base address always base address integer multiple size memory block size selected these bits. example, midrange block 32Kbytes, only bits BA19 BA15 programmed. block address could located 20000h 38000h 22000h. base address chip select 00000h only chip select active. chip select address range allowed overlap chip select address range. chip select address range Reserved Ready Mode. This configured enable/disable wait states inserted chip selects. R1,R0 bits this register determine number wait state insert. external ready ignored external ready required R1-R0, Wait-State value. R1,R0 determines number wait states inserted into access. Semiconductor Subject change without notice allowed overlap chip select address range, either.
RISC Controller
R1100
(R1,R0) (1,1) wait states (1,0) wait states, (0,1) wait states (0,0) wait states
Auxiliary Register
Offset Reset Value
Reserved 14-8: M6-M0, Block Size. These bits determines total block size MCS3 MCS0 chip selects. Each individual chip select active quarter total block size. example, block size bytes base address located 20000h. individual active memory address range MCS3 MCS0 MCS0 20000h 21FFF, MCS1 -22000 23FFFh, MCS2- 24000h 25FFFh, MCS3- 26000h 27FFFh. total block size defined M6-M0, M6-M0 0000001b 0000010b 0000100b 0001000b 0010000b 0100000b 1000000b Total block size, MCSx address active range 128k 256k 512k 128k
Selector. This configures multiplex output which PCS6 PCS5 pins chip selects A2-A1. PCS6 PCS5 configured peripheral chip select pins. PCS6 configured address PCS5 configured Memory space Selector. PCSx pins active memory cycle. PCSx pins active cycle. Reserved Ready Mode. This configured enable/disable wait states inserted PCS5,PCS6 chip selects. R1,R0 bits this register determines number wait state insert. external ready ignored external ready required R1-R0, Wait-State value. R1,R0 determines number wait states inserted into PCS5 PCS6 access. (R1,R0) (1,1) wait states (1,0) wait states, (0,1) wait states (0,0) wait states
Semiconductor Subject change without notice
13.4 PCSx
RISC Controller
R1100
peripheral memory chip selects which programmed through register define these pins. base address memory block located anywhere within bytes memory space, exclusive areas associated with MCS4 chip elects. chip selects mapped space, access range bytes. PCS6 PCS5 configured from wait-state wait-states. PCS3 PCS0 configured from wait-state wait-states.
Peripheral Chip Select Register
Offset Reset Value
BA19 BA11
15-7 BA19-BA11, Base Address. BA19-BA11 correspond 19-11 bytes (20-bits) programmable base address chip select block. When chip selects mapped space, BA19-BA16 must written 0000b because address only bytes (16-bits) wide. PCSx address range: PCS0 PCS1 PCS2 PCS3
PCS5
PCS6
Base Address Base Address 100h Base Address 200h Base Address 300h Base Address 500h Base Address 600h
Base Address Base Address 1FFh Base Address 2FFh Base Address 3FFh Base Address 5FFh Base Address 6FFh
6-4: Reserved 1-0: R1,R0 ,Wait-State Value. R3,R1,R0 determines number wait-states inserted into PCS3 PCS0 access. Wait States
Ready Mode. This configured enable/disable wait states inserted PCS3 PCS0 chip selects. Semiconductor Subject change without notice
RISC Controller
R1100
R3,R1,R0 bits determines number wait state insert. external ready ignored external ready required
Semiconductor Subject change without notice
RISC Controller
R1100
Interrupt Controller Unit
There twelve interrupt requests source connect controller: five maskable interrupt pins INT0 INT4); non-maskable interrupt (NMI) internal unit request source Timer ;DMA Asynchronous serial unit).
Master/Slave Mode Select (FEH.14)
Timer0/1/2 Interrupt REQ. Timer0 REQ.
Interrupt Type
INT0 Timer1 REQ.
Interrupt Control Logic
Interrupt REQ.
Execation Unit
Timer2 REQ. DMA0 Interrupt REQ. DMA1 Interrupt REQ. INT2 INT3 INT4 Asynchronous Serial Port
Register
Acknowledge
In-Service Register
Acknowledge DMA, Timer,Serial port Unit
Internal Address/Data
Interrupt Control Unit Block Diagram
14.1 Master Mode Slave Mode interrupt controller programmed master slave mode. (program 14). master mode connections Fully Nested Mode connection Cascade Mode connection.
INT0 INT1 INT2 INT3 INT4
Interrupt Interrupt Interrupt Interrupt Interrupt
Source Source Source Source Source
R1100 Fully Nested Mode Connections
Semiconductor Subject change without notice
RISC Controller
R1100
Interrupt Sources
INT4
INT0
8259 8259
INTA0
CAS3-CAS0
INTA
CAS3-CAS0
Interrupt Sources
R1100
INT1 Interrupt Sources
8259
INTA1
CAS3-CAS0
8259
INTA
CAS3-CAS0
Interrupt Sources
Cascade Mode Connection
INT0
8259
INTA0
R1100
Select Cascade Address Dccode
Slave Mode Connection
14.2 Interrupt Vector, Type Priority following table shows interrupt vector addresses, type priority. maskable interrupt priority changed programmed priority register. Vector addresses each interrupt fixed. Interrupt Type Divide Error Exception Trace interrupt Breakpoint Interrupt INTO Detected Over Flow Exception Semiconductor Subject change without notice Interrupt source Vector Address Type Priority Note
RISC Controller
R1100
15h-1Fh
Array Bounds Exception Undefined Opcode Exception Opcode Exception Timer Reserved INT0 INT1 INT2 INT3 INT4 Watchdog Timer Timer Timer Asynchronous Serial port Reserved
*/**
*/** */**
Note When interrupt occurs same time, priority (1-1 1-2) (2-1> 2-3) Note interrupt types these sources programmable slave mode.
14.3 Interrupt Request When interrupt requested, internal interrupt controller verifies interrupt enable (The flag enable, there higher priority interrupt requests being serviced pending. interrupt granted interrupt controller uses interrupt type access vector from interrupt vector table. external active (level-trigger) request interrupt controller service, pins must hold till microcontroller enter interrupt service routine. There interrupt-acknowledge output when running fully nested mode, should simulate interrupt-acknowledge necessary.
14.4 Interrupt Acknowledge processor requires interrupt type index into interrupt table. internal interrupt provide interrupt type external controller provide interrupt type. internal interrupt controller provides interrupt type processor without external cycles generation. When external interrupt controller supplying interrupt type, processor generates acknowledge cycles, interrupt type written AD7-AD0 lines external interrupt controller. Semiconductor Subject change without notice
RISC Controller
R1100
CLKOUTA
ADDRESS[19:0]
ADDRESS
AD15:AD0
Interrupt TYPE
INTA0,INTA1
DT/R
S2:S0
INTR
INTR
INTERRUPT ACKNOWLEDGE CYCLE (CASECADE SLAVE MODE)
14.5 Programming Registers Software programmed through registers Master mode: 44h, 42h, 40h, 3Eh, 3Ch, 3Ah, 38h, 36h, 34h, 32h, 30h, 2Eh, 2Ch, 2Ah, 28h, 26h, 24h, 22h; interrupt controller operation. Slave Mode: 3Ah, 38h, 36h, 34h, 32h, 30h, 2Eh, 2Ch, 2Ah, 28h,22h, define
Serial Port Interrupt Control Register
Reserved
Offset Reset Value 001Fh
(Master Mode) 15-4 Reserved MSK, Mask. Mask interrupt source asynchronous serial port. Enable serial port interrupt.
Semiconductor Subject change without notice
RISC Controller
R1100
PR2-PR0, Priority. These bits determine priority serial port relative other interrupt signals.
priority selection: PR2, PR1, Priority High)
INT4 Control Register
L
Offset Reset Value 000Fh
Reserved
(Master Mode) Reserved ETM, Edge trigger mode enable. When this Interrupt triggered high edge. high edge will latched level till this interrupt been serviced. LTM, Level-Triggered Mode. Interrupt triggered high active level Interrupt triggered high edge. MSK, Mask. Mask interrupt source INT4 Enable INT4 interrupt. 2-0: Interrupt Priority These bits setting priority selection same
INT3 Control Register
L
Offset Reset Value 000Fh
Reserved
Semiconductor Subject change without notice
(Master Mode)
RISC Controller
R1100
Reserved 7:ETM, Edge trigger mode enable. When this Interrupt triggered high edge high edge will latched level till this interrupt been serviced. LTM, Level-Triggered Mode. Interrupt triggered high active level Interrupt triggered high edge. MSK, Mask. Mask interrupt source INT3 Enable INT3 interrupt. 2-0: Interrupt Priority These bits setting priority selection same
INT2 Control Register
L
Offset Reset Value 000Fh
Reserved
(Master Mode) 15-8, Reserved ETM, Edge trigger mode enable. When this Interrupt triggered high edge. high edge will latched level till this interrupt been serviced. LTM, Level-Triggered Mode. Interrupt triggered high active level Interrupt triggered high edge. MSK, Mask. Mask interrupt source INT2 Enable INT2 interrupt. 2-0: Interrupt Priority These bits setting priority selection same register
INT1 Control Register
L
Offset Reset Value 000Fh
Reserved
ESFNM
Semiconductor Subject change without notice
(Master Mode) 15-8 Reserved
RISC Controller
R1100
ETM, Edge trigger mode enable. When this Interrupt triggered high edge. high edge will latched level till this interrupt been serviced. SFNM, Special Fully Nested Mode. Enable special fully nested mode INT1 Cascade Mode, this enable cascade mode. LTM, Level-Triggered Mode. Interrupt triggered high active level Interrupt triggered high edge. MSK, Mask. Mask interrupt source INT1 Enable INT1 interrupt. 2-0: Interrupt Priority These bits setting priority selection same register
(Slave Mode), Timer interrupt control register reset value 0000h Reserved MSK, Mask. Mask interrupt source Timer Enable Timer interrupt. 2-0: Interrupt Priority These bits setting priority selection same register
INT0 Control Register
L
Offset Reset Value 000Fh
Reserved
ESFNM
(Master Mode) 15-8 Reserved ETM, Edge trigger mode enable. When this Interrupt triggered high edge. high edge will latched level till this interrupt been serviced. SFNM, Special Fully Nested Mode. Enable special fully nested mode INT0. Cascade Mode, this enable cascade mode. Semiconductor Subject change without notice
MSK, Mask.
RISC Controller
R1100
LTM, Level-Triggered Mode. Interrupt triggered high active level Interrupt triggered high edge.
Mask interrupt source INT0 Enable INT0 interrupt. 2-0: Interrupt Priority These bits setting priority selection same register
(Slave Mode), Timer interrupt control register reset value 0000h 15-4 Reserved Mask. Mask interrupt source timer Enable timer interrupt. 2-0: Interrupt Priority These bits setting priority selection same register
Interrupt Control Register
Offset Reset Value 000Fh
(Master Mode) 15-4 Reserved Mask. Mask interrupt source controller Enable controller interrupt. 2-0: Interrupt Priority These bits setting priority selection same register
(Slave Mode), interrupt control register reset value 0000h 15-4 Reserved Mask. Mask interrupt source controller Enable controller interrupt. 2-0: Interrupt Priority Semiconductor Subject change without notice
RISC Controller
R1100
These bits setting priority selection same register
Interrupt Control Register
Offset Reset Value 000Fh
(Master Mode) 15-4 Reserved Mask. Mask interrupt source controller Enable controller interrupt. 2-0: Interrupt Priority These bits setting priority selection same register
(Slave Mode), reset value 0000h 15-4 Reserved Mask. Mask interrupt source controller Enable controller interrupt. 2-0: Interrupt Priority These bits setting priority selection same register
Timer Interrupt Control Register
Offset Reset Value 000Fh
(Master Mode) 15-4 Reserved Mask. Mask interrupt source Timer controller Enable Timer controller interrupt. 2-0: Interrupt Priority These bits setting priority selection same register
Semiconductor Subject change without notice
15-4 Reserved Mask.
RISC Controller
R1100
(Slave Mode), Timer interrupt control register reset value 0000h
Mask interrupt source Timer controller Enable Timer controller interrupt. 2-0: Interrupt Priority These bits setting priority selection same register
Interrupt Status Register
DHLT
Offset Reset Value
Reserved
TMR2 TMR1 TMR0
(Master Mode),
Reset value undifine
DHLT, Halt. halts activity. When non-maskable interrupts occur. When IRET instruction executed. 14-3 Reserved. TMR2-TMR0, indicates corresponding timer interrupt request pending.
(Slave Mode), Reset value 0000h DHLT, Halt. halts activity. When non-maskable interrupts occur. When IRET instruction executed. 14-3 Reserved. TMR2-TMR0, indicates corresponding timer interrupt request pending.
Interrupt Request Register
Reserved
Offset Reset Value
Semiconductor Subject change without notice
(Master Mode)
RISC Controller
R1100
Interrupt Request register read-only register. internal interrupts (SPI, TMR), corresponding when device requests interrupt. reset during internally generated interrupt acknowledge. INT4-INT0 external interrupts, corresponding (I4-I0) reflects current value external signal. 15-11 Reserved. SPI, Serial Port Interrupt Request. Indicates interrupt state serial port. Watchdog Timer Interrupt Request. Watchdog Timer interrupt pending. I4-I0, Interrupt Requests. corresponding interrupt pending. D1-D0, Channel Interrupt Request. corresponding channel interrupt pending. Reserved. TMR, Timer Interrupt Request. timer control unit interrupt pending.
Interrupt Service Register
Reserved
Offset Reset Value 0000h
(Slave Mode) Interrupt Request register read-only register. internal interrupts (D1, TMR2, TMR1, TMR0), corresponding when device requests interrupt. reset during internally generated interrupt acknowledge. 15-6 Reserved. TMR2/TMR1, Timer2/Timer1 Interrupt Request. Indicates state interrupt requests form associated timer. D1-D0, Channel Interrupt Request. Indicates corresponding channel interrupt pending. Reserved. TMR0, Timer Interrupt Request. Indicates state interrupt request from Timer
Semiconductor Subject change without notice
Reserved
RISC Controller
R1100
Service Register
Offset Reset Value 0000h
(Master Mode) bits INSERV register interrupt controller when interrupt taken. Each register cleared writing corresponding interrupt type register. 15-11 Reserved. SPI, Serial Port Interrupt In-Service. serial port interrupt currently being serviced. Watchdog Timer Interrupt In-Service. watchdog timer interrupt currently being serviced. I4-I0, Interrupt In-Service. corresponding interrupt currently being serviced. D1-D0, Channel Interrupt In-Service. corresponding channel interrupt currently being serviced. Reserved. TMR, Timer Interrupt In-Service. timer interrupt currently being serviced.
Service Register
Reserved
Offset Reset Value 0000h
(Slave Mode) bits In-Service register interrupt controller when interrupt taken. in-service bits cleared writing register. 15-6 Reserved. TMR2-TMR1, Timer2/Timer1 Interrupt In-Service. corresponding timer interrupt currently being serviced. D1-D0, Channel Interrupt In-Service. corresponding Channel currently being serviced. Reserved.
Semiconductor Subject change without notice
RISC Controller
R1100
TMR0, Timer Interrupt In-Service. Timer interrupt currently being serviced.
Priority Mask Register
Offset Reset Value 0007h
PRM2 PRM1 PRM0
(Master Mode) Determining minimum priority level which maskable interrupts generate interrupt. 15-3 Reserved. PRM2-PRM0, Priority Field Mask. Determining minimum priority that required order maskable interrupt source generate interrupt. Priority (High) (Low) PR2-PR0
(Slave Mode) Determining minimum priority level which maskable interrupts generate interrupt. 15-3 Reserved. PRM2-PRM0, Priority Field Mask. Determining minimum priority that required order maskable interrupt source generate interrupt. Priority PR2-PR0 (High) (Low)
Semiconductor Subject change without notice
Reserved
RISC Controller
R1100
Interrupt Mask Register
Offset Reset Value 07FDh
(Master Mode) 15-11 Reserved. SPI, Serial Port Interrupt Mask. state mask asynchronous serial port interrupt. Virtual Watchdog Timer Interrupt Mask. state mask Watchdog Timer interrupt. I4-I0, Interrupt Masks. Indicates state mask corresponding interrupt. D1-D0, Channel Interrupt Masks. Indicates state mask corresponding Channel interrupt. Reserved. TMR, Timer Interrupt Mask. state mask timer control unit
Interrupt Request Register
Offset Reset Value 003Dh
TMR0
Reserved
TMR2 TMR1
(Slave Mode) 15-6 Reserved. TMR2-TMR1, Timer 2/Timer1 Interrupt Mask. state mask Timer Interrupt Control register. Timer2 Time1 interrupt requests masked D1-D0, Channel Interrupt Mask. state mask bits corresponding control register. Reserved. TMR0, Timer Interrupt Mask. state mask Timer Interrupt Control Register
Poll Status Register
IREQ
Offset Reset Value
Reserved
(Master mode) Poll Status (POLLST) register mirrors current state Poll register. POLLST register read without affecting current interrupt request.
Semiconductor Subject change without notice
14-5 Reserved.
RISC Controller
R1100
IREQ, Interrupt Request. interrupt pending. S4-S0 field contains valid data.
S4-S0, Poll Status. Indicates interrupt type highest priority pending interrupt.
Poll Register
IREQ
Offset Reset Value
Reserved
(Master mode) When Poll register read, current interrupt acknowledged next interrupt takes place Poll register. IREQ, Interrupt Request. interrupt pending. S4-S0 field contains valid data. 14-5 Reserved. S4-S0, Poll Status. Indicates interrupt type highest priority pending interrupt.
Interrupt
NSPEC
Offset Reset Value
(Master Mode) NSPEC, Non-Specific EOI. indicates non-specific EOI. indicates specific interrupt type S4-S0. 14-5 Reserved. 4-0: S4-S0, Source Type. Specifies type interrupt that currently being processed.
Specific
Offset Reset Value 0000h
(Slave Mode)
Semiconductor Subject change without notice
15-3 Reserved.
RISC Controller
R1100
L2-L0, Interrupt Type. Encoded value indicating priority IS(interrupt service) reset. Writes these bits cause issued interrupt type slave mode.
Interrupt Vector Register
Offset Reset Value
(Slave Mode)
15-8 Reserved T4-T0, Interrupt Type. following interrupt type slave mode programmed. Timer interrupt controller Timer interrupt controller interrupt controller interrupt controller Timer interrupt controller :Reserved (T4,T3,T2,T1,T0, (T4,T3,T2,T1,T0, (T4,T3,T2,T1,T0, (T4,T3,T2,T1,T0, (T4,T3,T2,T1,T0,
Semiconductor Subject change without notice
Unit
RISC Controller
R1100
controller provides data transfer between memory peripherals without intervention CPU. There channels unit. Each channel accept request from source external (DRQ0 channel DRQ1 channel Timer overflow. data transfer from source destination memory memory memory, I/O, I/O, memory. Either bytes words transferred from even addresses cycles necessary (read from source write destination) each data transfer.
20-bit Adder/Subtractor
Adder Control Logic CAH.4-Channel TDRQ DAH.4-Channel
C8h-Transfer Counter Channel C2h,C0h-Source Address Channel C6h,C4h-Destination Address Channel D8h-Transfer Counter Channel D2h,D0h-Source Address Channel D6h,D4h-Destination Address Channel CAh.8-Channel CAh.8-Channel Control Logic Request Arbitration Logic Timer Request DRQ0 DRQ1 Interrupt Request
Channel Control Register0,CAh
Channel Control Register1,DAh
Internal Address/Data
Unit Block
15.1 Operation Every transfer consists cycles (figure Typical Transfer) cycles separated hold request, refresh request another request. registers CAh, C8h, C6h, C4h, C2h, C0h, DAh, D8h, D6h, D4h, D2h, D0h) used configure operate channels.
Semiconductor Subject change without notice
RISC Controller
R1100
CLKOUTA A19-A0 AD15-AD0
Address
Address
Address
Data
Address
Data
Typical Trarsfer
Control Registers
Offset (DMA0) Reset Value FFF9h
DM/IO DDEC DINC SM/IO SDEC SINC
SYN1 SYN0
TDRQ
definition Bits 15-0 DMA0 same Bits 15-0 register DMA1.
Transfer Count Register
Offset (DMA0) Reset Value
TC15
15-0: TC15-TC0, transfer Count. value this register decremented after each transfer.
Destination Address High Register
Offset (DMA0) Reset Value
Reserved
DDA19 DDA16
15-4: Reserved Semiconductor Subject change without notice
RISC Controller
R1100
3-0: DDA19-DDA16, High Destination Address. These bits A19- during transfer when destination address memory space space. destination address space (64Kbytes), these bits must programmed 0000b.
Destination Address Register
Offset (DMA0) Reset Value
DDA15 DDA0
15-0: DDA15-DDA0, Destination Address. These bits mapped A15- during transfer. value (DDA19-DDA0)b will increment decrement after each transfer.
Source Address High Register
Offset (DMA0) Reset Value
DSA19 DSA16
15-4: Reserved 3-0: DSA19-DSA16, High Source Address. These bits mapped A19- during transfer when source address memory space space. source address space (64Kbytes), these bits must programmed 0000b.
Source Address Register
Offset (DMA0) Reset Value
DSA15 DSA0
15-0: DSA15-DSA0, Source Address. These bits mapped A15- during transfer. value (DSA19-DSA0)b will increment decrement after each transfer.
Control Registers
Offset (DMA1) Reset Value FFF9h
DM/IO DDEC DINC SM/IO SDEC SINC
SYN1 SYN0
TDRQ
Semiconductor Subject change without notice
RISC Controller
R1100
Destination Address Space Select. destination address memory space. destination address space. DDEC, Destination Decrement. destination address automatically decrement after each transfer. (bit determines decrement value which When both DDEC DINC bits address remains constant Disable decrement function. DINC, Destination Increment. destination address automatically incremented after each transfer. (bit determines increment value which Disable decrement function. Source Address Space Select. Source address memory space. Source address space SDEC, Source Decrement. Source address automatically decremented after each transfer. (bit determines decrement value which When both SDEC SINC bits address remains constant Disable decrement function. SINC, Source Increment. Source address automatically incremented after each transfer. (bit determines increment value which Disable decrement function Terminal Count. synchronized transfer terminated when transfer count register reaches synchronized transfer terminated when transfer count register reaches Unsynchronized transfer always terminated when transfer count register reaches regardless setting this bit. INT, Interrupt. unit generates interrupt request when complete transfer count must generate interrupt. 7-6: SYN1-SYN0, Synchronization Type Selection. SYN1 SYN0 -Synchronization Type Unsynchronized Source synchronized
Semiconductor Subject change without notice
Priority.
RISC Controller
R1100
Destination synchronized Reserved
selects high priority this channel when both transferred same time. TDRQ, Timer Enable/Disable Request Enable requests from timer Disable requests from timer Reserved CHG, Changed Start Bit. This must when Start/Stop channel. Start channel Stop channel Byte/Word Select. address incremented decremented after each transfer. :The address incremented decremented after each transfer. modifying bit.
Transfer Count Register
Offset (DMA1) Reset Value
TC15
15-0: TC15-TC0, transfer Count. value this register decremented after each transfer.
Destination Address High Register
Offset (DMA1) Reset Value
Reserved
DDA19 DDA16
15-4: Reserved 3-0: DDA19-DDA16, High Destination Address. These bits mapped A19- during transfer when destination address memory space space. destination address space (64Kbytes), these bits must programmed 0000b.
Semiconductor Subject change without notice
RISC Controller
R1100
Destination Address Register
Offset (DMA1) Reset Value
DDA15 DDA0
15-0: DDA15-DDA0, Destination Address. These bits mapped A15- during transfer. value (DDA19-DDA0)b will increment decrement after each transfer.
Source Address High Register
Offset (DMA1) Reset Value
Reserved
DSA19 DSA16
15-4: Reserved 3-0: DSA19-DSA16, High Source Address. These bits mapped A19- during transfer when source address memory space space. source address space (64Kbytes), these bits must programmed 0000b.
Source Address Register
Offset (DMA1) Reset Value
DSA15 DSA0
15-0: DSA15-DSA0, Source Address. These bits A15- during transfer. value (DSA19-DSA0)b will increment decrement after each transfer.
15.2 External Requests External requests asserted pins. pins sampled falling edge CLKOUTA. takes minimum four clocks before cycle initiated Interface. request cleared four clocks before cycle. acknowledge provided, since chip-selects (MCSx, PCSx) programmed active given block memory space, source destination address registers programmed point same given block. transfer either source destination synchronized, also unsynchronized. Source-Synchronized Transfer figure shows typical source-synchronized transfer which provides source device least three clock cycles from time acknowledged deassert line. Semiconductor Subject change without notice
RISC Controller
R1100
Fetch Cycle CLKOUTA
Fetch Cycle
DRQ(Case1) DRQ(Case2)
NOTES: Case1 Current source synchronized transfer will immediately followed another transfer. Case2 Current source synchronized transfer will immediately followed antoher transfer.
Source-Synchronized Transfers
Destination-Synchronized Transfer figure shows typical destination-synchronized transfer which differs from source-synchronized transfer that idle states added deposit cycle. idle states extend cycle allow destination device deassert four clocks before cycle. idle states were inserted, destination device would have time deassert signal.
Fetch Cycle CLKOUTA
Fetch Cycle
DRQ(Case1) DRQ(Case2) NETES: Case1 Current destination synchronized transfer will immediately followed another transfer. Case2 Current destination synchronized transfer will immediately followed another transfer.
Destination-Synchronized Transfers
Semiconductor Subject change without notice
RISC Controller
R1100
Timer Control Unit
TMRIN1 TMRIN0 Microprocessor Clock
50h,Timer Count Register TMROUT1 52h,54h,Timer0 Maxcount Compare Register 58h,Timer Compare Register 5Ah,5Ch,Timer Maxcount Compare Register 60h,Timer count Register 62h,Timer Count Register
Counter Element Control Logic
TMROUT2 (Timer2) (Timer0,1,2) Request Interrupt Request
56h,Timer Control Register
5Eh,Timer Control Register 66h,Timer Control Register
Internal Address/Data
Timer Counter Unit Block
There three 16-bit programmable timers R1100. timer operation independent CPU. three timers programmed timer element counter element. Timers each connected external pins (TMRIN0, TMROUT0, TMRIN1, TMROUT1) which used count time external events, they used generate variable-duty-cycle waveforms. Timer connected external pins. used prescale timer timer request source.
Timer Mode Control Register
Offset Reset Value 0000h
CONT
These bits definition timer same bits register timer
Semiconductor Subject change without notice
RISC Controller
R1100
Offset Reset Value
Timer Count Register
TC15
TC15-TC0, Timer Count Value. This register contains current count timer count incremented every four internal processor clocks prescaled timer every four external clock which configured external clock select refer TMRIN1 signal.
Timer Maxcount Compare Register
Offset Reset Value
TC15
15-0 TC15 TC0, Timer Compare Value.
Timer Maxcount Compare Register
Offset Reset Value
TC15
15-0 TC15 TC0, Timer Compare Value.
Timer Mode Control Register
Offset Reset Value 0000h
CONT
Enable Bit. timer enable. timer inhibited from counting. must during writing bit, must same write.
Semiconductor Subject change without notice
RISC Controller
R1100
Inhibit Bit. This allows selective updating bit. must during writing bit, both must same write. This stored always read INT, Interrupt Bit. interrupt request generated when count register equals maximum count. timer configured dual max-count mode, interrupt generated each time count reaches max-count max-count Timer will issue interrupt request. RIU, Register Bit. Maxcount Compare register timer being used Maxcount Compare register timer being used 11-6 Reserved. Maximum Count Bit. When timer reaches maximum count, will H/W. dual maxcount mode, this each time either Maxcount Compare Maxcount Compare register reached. This regardless (66h.15). RTG, Re-trigger Bit. This defines control function input signal TMRIN1 pin. When EXT=1 (5Eh.2), this ignored. Timer1 Count Register (58h) counts internal events; Reset counting every TMRIN1 input signal from high (rising edge trigger). input holds timer Count Register (58h) value; High input enables counting which counts internal events. definition setting (EXT Timer1 counts internal events. TMRIN1 remains high. Timer1 counts internal events; count register reset every rising transition TMRIN1 TMRIN1 input acts clock source timer1 count register increase every four external clock. Prescaler Bit. This EXT(5Eh.2) define timer clock source. definition setting (EXT
Semiconductor Subject change without notice
RISC Controller
R1100
Timer1 Count Register increase every four internal processor clock. Timer1 count register increase which prescal timer TMRIN1 input acts clock source Timer1 Count Register increase every four external clock. EXT, External Clock Bit. Timer clock source from external Timer clock source from internal ALT, Alternate Compare Bit. This controls whether timer runs single dual maximum count mode. Specify dual maximum count mode. this mode timer counts Maxcount Compare then resets count register Then timer counts Maxcount Compare then resets count register again, starts over with Maxcount Compare Specify single maximum count mode. this mode timer will count valve contained Maxcount Compare reset then timer counts Maxcount Compare again. Maxcount Compare used this mode. CONT, Continuous Mode Bit. timer continuously. timer will halt after each counting maximum count will cleared.
Semiconductor Subject change without notice
RISC Controller
R1100
Timer Count Register
Offset Reset Value
TC15
TC15-TC0, Timer Count Value. This register contains current count timer count incremented each four internal processor clocks prescaled timer each four external clock which configured external clock select refer TMRIN1 signal.
Timer Maxcount Compare Register
Offset Reset Value
TC15
15-0 TC15 TC0, Timer Compare Value.
Timer Maxcount Compare Register
Offset Reset Value
TC15
15-0 TC15 TC0, Timer Compare Value.
Timer Mode Control Register
Offset Reset Value 0000h
CONT
Enable Bit. timer enable. timer inhibited from counting. must during writing bit, must same write.
Semiconductor Subject change without notice
RISC Controller
R1100
Inhibit Bit. This allowed selective updating bit. must during writing bit, both must same write. This stored always read INT, Interrupt Bit. interrupt request generated when count register equals maximum count. Timer will issue interrupt request. 12-6 Reserved. Maximum Count Bit. When timer reaches maximum count, will H/W. This regardless (66h.15). 4-1: Reserved. COUNT, Continuous Mode Bit. Timer continuously running when timer reaches maximum count. (66h.15) cleared timer hold after each timer count reaches maximum count.
Timer Count Register
Offset Reset Value
TC15
TC15-TC0, Timer Count Value. This register contains current count timer count incremented each four internal processor clocks.
Timer Maxcount Compare Register
Offset Reset Value
TC15
15-0 TC15 TC0, Timer Compare Value.
Semiconductor Subject change without notice
RISC Controller
R1100
Watchdog Timer Timer also configured watchdog timer. Software must fist programmed Timer Mode/Control (5Eh), Count (58h), Count (5Ah, 5Ch) registers then program Watchdog Timer Interrupt Control Register 42h) enable watchdog timer interrupt Timer Count Register must reloaded intervals less than Timer Maxcount value assure watchdog interrupt occurred.
Watchdog Timer Interrupt Control Register
Offset Reset Value 000Fh
Reserved
(Master Mode) 15-4 Reserved Mask. Mask interrupt source watchdog timer Enable watchdog timer interrupt. Priority. priority selection: PR2, PR1, Priority (High) (Low
Semiconductor Subject change without notice
RISC Controller
R1100
16.1 Timer/Counter Unit Output Mode
Timers maximum count value maximum count values. Timer only maximum count value. Timer timer1 configured single dual Maximum Compare count mode, TMROUT0 TMROUT1 signals used generated waveform various duty cycle.
Maxcount Dual Maximum Count Mode Single Maximum Count Mode Maxcount Maxcount Maxcount Maxcount Maxcount Maxcount
1T:One Microprocessor clock
Timer/Counter Unit Output Modes
Semiconductor Subject change without notice
RISC Controller
R1100
Asynchronous Serial Port
R1100 asynchronous serial port provides TXD, pins full duplex bi-directional data transfer without handshaking signals. UART port supports 8-bit 7-bit data transfer; parity, even parity, parity; stop bits. transfers through serial port supported receive/transmit clock based microprocessor clock. serial port used power-saved mode, transfer rate must adjusted correctly reflect internal operating frequency. Software programmed through 80h, 82h, 84h, 86h, registers configure asynchronous serial port.
Internal Address/Data Receive Data Register(86h) Transmit Shift Regoster Transmit Hold Register Receive Buffer
Transmit Data Register(84h)
Receive Shift Register
Control Register(80h) Interrupt Request Control Logic Status Register(82h) Baud Rate Divisor Register(88h)
Serial Port Block Diagram
Serial Port Control Register
BRKVAL WLGN
Offset Reset Value 0000h
RMODE
Reserved
TXIE RXIE LOOP
PMODE
TMOD RSIE
15-12: Reserved TXIE, Transmit Holding Register Empty Interrupt Enable. This enable serial port generates interrupt request when transmit holding register empty. LOOP, Loopback. serial port loopback mode. this mode, transmit shift register connected transmit shift register internal output high. provides serial port testing this mode. BRK, Send Break.
Semiconductor Subject change without notice
RISC Controller
R1100
should check TEMT (82h.6) before setting bit. serial port send frame continues level output output level depends BRAVAL status, when data written transmit data register. BRKVAL, Break Value. continuous drive high level signal during send break operation. continuous drive level signal during send break operation. 6-5: PMODE, Parity Mode. Parity generation checking during transmission reception. Parity mode selection (Bit parity frame number frame. Even number frame. WLGN, Word Length. serial port sends receives bits data frame. serial port sends receives bits data frame. STP, Stop Bits. stop bits used signify frame. stop used signify frame. TMODE, Transmit Mode. Enable transmit section serial port. Disable transmit section serial port. RSIE, Receive Status interrupt Enable. Enable receive section serial port generate interrupt Disable receive section serial port generate interrupt RMODE, Receive Mode. Enable receive section serial port. Disable receive section serial port.
Serial Port Status Register
Reserved
Offset Reset Value
TEMT THRE BRK1
15-7 Reserved TEMT, Transmitter Empty. Read only bit. This when transmit shift register empty. disable transmit function when THRE, Transmit Holding Register Empty. Read only bit. When this transmit holding buffer contains invalid data transmit data register (84h) written data. When this indicates that transmit holding buffer contains valid data that been copied transmit shift register transmit data register (84h) Semiconductor Subject change without notice
RISC Controller
R1100
written data. When transmit interrupt enabled, serial port interrupt generated when this THRE automatically cleared during copy data transmit holding buffer. RDR, Receive Data Ready. Read only bit. When receive data register ready read, this When receive data register dose contain valid data. This will cleared when reading receive data register. BRKI, Break Interrupt. indicates that break been receive when this will generate serial interrupt request RISE (80h.1) enabled. This should cleared software. FER, Framing Error. This indicate that framing error occurred during reception data will generate serial interrupt request RISE (80h.1) enabled. This should cleared software. PER, Parity Error. This indicate that party error occurred during reception data will generate serial interrupt request RISE (80h.1) enabled. This should cleared software. OER, Overrun Error. This indicate that overrun error occurred during reception data will generate serial port interrupt request RISE (80h.1) enabled. This should cleared software.
Serial Port Transmit Data Register
Offset Reset Value
Reserved
TDATA
15-8: Reserved TDATA, Transmit Data. Software writes this register with data transmitted serial port. THRE (82h.5) should read before writing this register avoid overwriting data this register. When writing data this register, THRE will cleared same time.
Serial Port Receive Data Register
Offset Reset Value
Reserved
RDATA
15-8: Reserved 7-0: RDATA, Received DATA. (82h.4) should read before reading RDATA register avoid reading
Semiconductor Subject change without notice
RISC Controller
R1100
invalid data.
Serial Port Baud Rate Divisor Register
Offset Reset Value
BAUDDIV
15-0: BAUDDIV, Baud Rate Divisor. general formula baud rate divisor Baud Rate Microprocessor Clock (BAUDDIV+1)] example, Microprocessor clock 22.1184MHz BAUDDIV=5 (Decimal), baud rate serial port 115.2k.
Semiconductor Subject change without notice
RISC Controller
R1100
Synchronous Serial Port
There four pins synchronous serial port interface, which half duplex, bi-directional data transfer. synchronous serial interface operates master/slave configuration, synchronous serial port R1100 master mode. SCLK frequency affected reduced microprocessor clock frequency when it's power-save mode. Software programmed 10h, 12h, 14h,16h, configured synchronous serial port interface.
Synchronous Serial Status Register
Reserved
Offset Reset Value 0000h
RE/TE DR/DT
Read only register that indicates state port. 15-3 Reserved. RE/TE, Receive/Transmit Error Detect. Either read Synchronous Serial Receive register write transmit registers while busy (PB=1). SDEN output inactive. DR/TR, Data Receive/Transmit Complete. transfer data (SCLK rising edge) during transmit receive operation. When register read, when SSD0 SSD1 registers written, when register read, when both SDEN0 SDEN1 become inactive. port Busy. transmit receive operation progress. port ready transmit receive data.
Synchronous Serial Control Register
Offset Reset Value 0000h
Reserved
SCLKDIV
This read/write register controls operation SDEN0-SDEN1 outputs transfer rate port. 15-3 Reserved. SCLKDIV, SCLK Divide. SCLKDIV SCLK Frequency Divider Processor clock/2 Processor clock/4 Semiconductor Subject change without notice
RISC Controller
R1100
Processor clock/8 Processor clock/16
DE1, SDEN1 Enable.
SDEN1 held High. SDEN1 pint Low. DE0, SDEN0 Enable. SDEN0 held High. SDEN0 pint Low.
Synchronous Serial Transmit Register
Offset Reset Value
Reserved
Synchronous Serial Transmit Register. register contains data transferred from processor peripheral write operation. 15-8 Reserved. 7-0: Send Data. Data transmit over SDATA pin.
Synchronous Serial Transmit Register
Offset Reset Value
Reserved
Synchronous Serial Transmit Register. register contains data transferred from processor peripheral write operation. 15-8 Reserved. 7-0: Send Data. Data transmit over SDATA pin.
Synchronous Serial receive Register
Offset Reset Value
Reserved
Synchronous Serial Receive Register contains data transferred from peripheral processor read
Semiconductor Subject change without notice
operation. 15-8 Reserved.
RISC Controller
R1100
7-0: Receive Data. Data received over SDATA pin.
Synchronous serial port operation
following figures show data transmit data receive operation.
Write 12h.0 12h.1 (DE0=1 De1=1)
Write 12h.0 12h.1 (DE0=0 De1=0)
SDEN0 SDEN1 SDATA SCLK
PB=1 DR/DT=0
(Write 16h)
(Write 16h)
(Write 16h)
Bit0
Bit7
Bit0
Bit7
Bit0
Bit7
PB=0 DR/DT=1
PB=1 DR/DT=0
PB=0 DR/DT=1
PB=1 DR/DT=0
PB=0 DR/DT=1
Synchronous Serial Port Multiple Write
Write 12h.0 12h.1 (DE0=1 De1=1)
Write 12h.0 12h.1 (DE0=0 De1=0)
SDEN0 SDEN1 SDATA SCLK
PB=1 DR/DT=0
(Write 16h)
Read From (dummy)
Read From
Bit0
Bit7
Bit0
Bit7
Bit0
Bit7
PB=0 DR/DT=1
PB=1 DR/DT=0
PB=0 DR/DT=1
PB=1 DR/DT=0
PB=0 DR/DT=1
Synchronous Serial Port Multiple Read
Semiconductor Subject change without notice
RISC Controller
R1100
CLKOUTA SDEN SCLK SDATA(RX) SDATA(TX)
DATA DATA
Synchronous Serial Interface Waveforms
Semiconductor Subject change without notice
Unit
function.
RISC Controller
R1100
R1100 provides programmable signals, which multi-function pins with others normal function signals. Software programmed through registers 7Ah, 78h, 76h, 74h, 72h, 70h) configure multi-function pins normal
internal pull-up
Mode Direction
Normal Function
Data In/Out
Write PDATA
Read PDATA
Microprocessor Clock
internal pull-down
Normal Data "0":un-normal function
Operation Diagram
19.1 multi-function list table Multi Function TMRIN1 TMROUT1 PCS6 PCS5 SRDY TMROUT0 TMRIN0 DRQ0 DRQ1 MCS0 MCS1 PCS0 PCS1 Reset status/PIO internal resister Input with pull-up Input with pull-down Input with pull-up Input with pull-up Normal operation/ Input with pull-up Normal operation/ Input with pull-up Normal operation/ Input with pull-down Normal operation/ Input with pull-up Normal operation/ Input with pull-up Normal operation/ Input with pull-up Input with pull-down Input with pull-up Input with pull-up Input with pull-up Input with pull-up Input with pull-up Input with pull-up Input with pull-up
Semiconductor Subject change without notice
RISC Controller
R1100
PCS2 PCS3 SCLK SDATA SDEN0 SDEN1 MCS2 MCS3 RFSH CLKDIV2 INT4 INT2 Input with pull-up Input with pull-up Input with pull-up Input with pull-up Input with pull-down Input with pull-down Input with pull-up Input with pull-up Input with pull-up Input with pull-up Input with pull-up Input with pull-up Input with pull-up Input with pull-up
Data Register
Offset Reset Value
PDATA
PDATA31-PDATA16, Data Bits. These bits PDATA31- PDATA16 PIO31 -PIO16 which indicates driven level when output reflects external level when input
Direction Register
Offset Reset Value FFFFh
PDIR
15-0 PDIR PDIR16, Direction Register. Configure input. Configure output normal function.
Mode Register
Offset Reset Value 0000h
PMODE
Semiconductor Subject change without notice
RISC Controller
R1100
15-0: PMODE31-PMODE16, Mode Bit. definition pins configured combination Mode Direction. programmed individual. definition (PIO Mode, Direction) function: Normal operation output input with pullup/pulldown input without pullup/pulldown
Data Register
Offset Reset Value
PDATA
15-0 PDATA15- PDATA0 Data Bus. These bits PDATA15- PDATA0 PIO15 -PIO0 which indicates driven level when output reflects external level when input.
Direction Register
Offset Reset Value FC0Fh
PDIR
15-0 PDIR PDIR0, Direction Register. Configure input. Configure output normal function.
Mode Register
Offset Reset Value 0000h
PMODE
15-0: PMODE15-PMODE0, Mode Bit.
Semiconductor Subject change without notice
RISC Controller
R1100
Format Clocks Notes
INSTUCTION OPCODES CLOCK CYCLES
Function
DATA TRANSFER INSTRUCTIONS Move register register/memory register/memory register immediate register/memory immediate register memory accumulator accumulator memory register/memory segment register segment register register/memory PUSH Push memory register segment register immediate memory register segment register PUSHA Push POPA XCHG Exchange register/memory register with accumulator XTAL Translate byte Input from fixed port variable port Output from fixed port variable port Load register Load pointer Load pointer ENTER Build stack frame LEAVE Tear down stack frame LAHF Load with flags SAHF Store into flags PUSHF Push flags POPF flags
1000100w 1000101w 1100011w
1011w
1010000w 1010001w 10001110 10001100 11111111 01010 000reg110 011010s0
data
addr-low addr-low
data data addr-high addr-high
data
data
data
10001111 01011 (reg01) 01100000 01100001 1000011w 10010 11010111 1110010w 1110110w 1110010w 1110110w
10001101 11000101 11000100 11001000
port
port
data-low
(mod11) (mod11) data-high
11+10(L-1)
11001001 10011111 10011110 10011100 10011101
ARITHMETIC INSTRUCTIONS reg/memory with register either immediate register/memory immediate accumulator
000000dw 100000sw 0000010w
data
data data
data sw=01
Semiconductor Subject change without notice
RISC Controller
R1100
Format
000100dw 100000sw 0001010w 1111111w 01000 001010dw 100000sw 0001110w 000110dw 100000sw 0001110w 1111111w 01001 1111011w 0011101w 0011100w 100000sw 0011110w 1111011w data
Function
with carry reg/memory with register either immediate register/memory immediate accumulator Increment register/memory register Subtract reg/memory with register either immediate from register/memory immediate from accumulator Subtract with borrow reg/memory with register either immediate from register/memory immediate from accumulator Decrement register/memory register Change sign register/memory Compare register/memory with register register with register/memory immediate with register/memory immediate with accumulator multiply (unsigned) register-byte register-word memory-byte memory-word IMUL Integer multiply (signed) register-byte register-word memory-byte memory-word register/memory multiply immediate (signed) Divide (unsigned) register-byte register-word memory-byte memory-word IDIV Integer divide (signed) register-byte register-word memory-byte memory-word ASCII adjust subtraction Decimal adjust subtraction ASCII adjust addition Decimal adjust addition ASCII adjust divide ASCII adjust multiply Corrvert byte word Convert word double-word
Clocks
Notes
data data
data sw=01
data data
data data
data sw=01
data
data
data data
data sw=01
1111011w 23/28
011010s1 1111011W
data
data
1111011w 00111111 00101111 00110111 00100111 11010101 11010100 10011000 10011001
00001010 00001010
Semiconductor Subject change without notice
RISC Controller
R1100
Format
1111011w 001000dw 1000000w 0010010w 000010dw 1000000w 0000110w 001100dw 1000000w 0011010w 1000010w 1111011w 1010100w 1101000w 1101001w 1100000w data data data data
Function
MANIPULATION INSTRUCTUIONS Invert register/memory reg/memory register either immediate register/memory immediate accumulator reg/memory register either immediate register/memory immediate accumulator Exclusive reg/memory register either immediate register/memory immediate accumulator TEST function flags result register/memory register immediate data register/memory immediate data accumulator Sifts/Rotates register/memory register/memory register/memory Count STRING MANIPULATION INSTRUCTIONS MOVS Move byte/word Input byte/word from port OUTS Output byte/word port CMPS Compare byte/word SCAS Scan byte/word LODS Load byte/word AL/AX STOS Store byte/word from AL/AX
Repeated count
Clocks
Notes
data data
data
data data
data
data data
data
data data
data
count
1010010w 0110110w 0110111w 1010011w 101011w 1010110w 1010101w 11110010 11110010 11110010 1111011z 1111001z 11110010 11110100 1010010w 0110110w 0110111w 1010011w 1010111w 0101001w 0101001w
4+9n 5+9n 5+9n 4+18n 4+13n 3+9n 4+3n
MOVS Move byte/word Input byte/word from port OUTS Output byte/word port CMPS Compare byte/word SCAS Scan byte/word LODS Load byte/word AL/AX STOS Store byte/word from AL/AX PROGRAM TRANSFER INSTRUCTIONS Conditional Transfers jump JE/JZ equal/zero JL/JNGE less/not greater equal JLE/JNG less equal/not greater JC/JB/JNAE carry/below/not above equal JBE/JNA below equal/not above JP/JPE parity/parity even overflow sign JNE/JNZ equal/not zero JNL/JGE less/greater equal JNLE/JG less equal/greater JNC/JNB/JAE carry/not below /above equal JNBE/JA below equal/above JNP/JPO parity/parity
01110100 01111100 01111110 01110010 01110110 01111010 01110000 01111000 01110101 01111101 01111111 01110011 01110111 01111011
disp disp disp disp disp disp disp disp disp disp disp disp disp disp
Semiconductor Subject change without notice
overflow sign
RISC Controller
R1100
01110001 01111001 disp disp
Function
Unconditional Transfers
Format
11101000 11111111 11111111 10011010 disp-low segment offset selector disp-high (mod11)
Clocks
12/17
Notes
CALL Call procedure direct within segment reg/memory indirect within segment indirect intersegment direct intersegment
Retum from procedure within segment within segment adding immed intersegment instersegment adding immed Unconditional jump short/long direct within segment reg/memory indirect within segment indirect intersegment direct intersegment
11000011 11000010 11001011 1001010 11101011 11101001 11111111 11111111 11101010
data-low data-low disp-low disp-low segment offset selector
data-high data-high
11/16
disp-high (mod ?11)
Iteration Control LOOP Loop times LOOPZ/LOOPE Loop while zero/equal LOOPNZ/LOOPNE Loop while zero/equal JCXZ Jump zero Interrupt Interrupt Type specified Type INTO Interrupt overflow BOUND Detect value range IRET Interrupt return PROCESSOR CONTROL INSTRUCTIONS clear carry Complement carry carry Clear direction direction Clear interrupt interrupt Halt WAIT Wait LOCK lock prefix Math coprocessor escape operation SEGMENT OVERRIDE PREFIX
11100010 11100001 11100000 11100011
disp disp disp disp
7/16 7/16 7/16 7/15
11001101 11001100 11001110 01100010 11001111
type
43/4 21-60
11111000 11110101 11111001 11111100 11111101 11111010 11111011 11110100 10011011 11110000 11011MMM 10010000
00101110 00110110 00111110 00100110
Semiconductor Subject change without notice
RISC Controller
R1100
20.1 R1100 Execution Timings
above instruction timing represents minimum execution time clock cycles each instruction. timings given based following assumptions: opcode, along with data displacement required execution, been prefetched resides instruction queue time needed. wait states HOLDs occur. word -data located even-address boundaries. RISC micro operation(uOP) maps cycle(according pipeline stages described below) except following case: Pipeline Stages single micro operation(one cycle): Fetch Fetch Decode Decode op_r Access (For function uOP) (For Memory function uOP)
Memory read need cycles bus. Pipeline stages Memory read uOP(6 cycles): Fetch Decode Access Idle
Cycle Memory push need cycle previous Memory push uOP, cycles previous Memory push Memory Write uOP. Pipeline stages Memory push after Memory push (another cycles): Fetch Decode Decode
Access
Idle
Access
Access
Access
Access
Access
Idle
(1st Memory push uOP)
(2nd uOP) Fetch
pipeline stall function bits operation need both cycles, bits operation need both cycles. jumps, calls, loopXX instructions required fetch next instruction destination address(Unconditional Fetch uOP) will need cycles. Pipeline stages unconditional fetch: Fetch Decode
Decode
Access
Idle
Access
Access
Access
Access
Access
Fetch Idle
(Fetch uOP)
(next uOP) Fetch
will flushed These cycles caused branch penalty Fetch
Decode following stages.(New uOP)
Note: op_r: operand read stage, Calculate Effective Address stage, Idle: Idle stage, T0.T3: T0.T3 stage, Access: Access data from cache memory stage.
Semiconductor Subject change without notice
RISC Controller
R1100
Characteristics each
Name Characteristics
ARDY HOLD INT0 INT1/ SELECT CLKOUTA CLKOUTB/TDI
Schmitt Trigger 3.3V tolerant input, with internal pull-up resistor Schmitt Trigger 3.3V tolerant input, with internal pull-down resistor 3.3V tolerant CMOS input, with internal pull-down resistor Schmitt Trigger 3.3V tolerant input, with internal pull-down resistor 3-State CMOS output, 3.3V Bi-direction with internal pull-down resistor output, tolerant input Bi-direction with internal pull-up resistor 16mA output, tolerant input Bi-direction with internal pull-down resistor output, tolerant input 3-State CMOS output, 3.3V Bi-direction with enabled/disabled internal pull-up resistor when active PIO, normal function pull-up resistor disabled. 16mA output, tolerant input
/TDO /TCK /TMS
A19/PIO9 A18/PIO8 A17/PIO7
3-State CMOS output, 3.3V
Bi-direction 16mA output, tolerant input
Semiconductor Subject change without notice
RISC Controller
R1100
AD10 AD11 AD12 AD13 AD14 AD15
SRDY/PIO6 TMROUT0/PIO10 TMROUT1/PIO1 SDEN0/PIO22 SDEN1/PIO23
ADEN TRST
HLDA INT2/ INTA0 /PIO31 INT4/PIO30
INT3/ INTA /IRQ UCS/ ONCE ONCE0
Bi-direction with internal pull-down resistor output, tolerant input Bi-direction with enabled/disabled internal pull-down resistor when active PIO, normal function pull-down resistor disabled. output, tolerant input Bi-direction with internal pull-up resistor output, tolerant input Bi-direction with internal pull-up resistor 12mA output, tolerant input CMOS output, Bi-direction with enabled/disabled internal pull-up resistor when active PIO, normal function pull-up resistor disabled. output, tolerant Schmitt Trigger input Bi-direction with internal pull-down resistor output, tolerant Schmitt Trigger input Bi-direction with internal pull-up resistor output, tolerant Schmitt Trigger input
Semiconductor Subject change without notice
RISC Controller
R1100
/PIO5 /PIO4 PCS0 /PIO16 PCS1/PIO17 PCS2 /PIO18 PCS3 /PIO19 PCS5 /A1/PIO3 PCS6 /A1/PIO3 MCS0 /PIO14 /PIO15 MCS2 /PIO24 MCS3 RFSH/PIO25 /PIO26 CLKDIV /PIO29
TMRIN0/PIO11 TMRIN1/PIO0 DRQ0/PIO12 DRQ1/PIO13 TXD/PIO27 RXD/PIO28 SDATA/PIO21 SCLK/PIO20
Bi-direction with enabled/disabled internal pull-up resistor when active PIO, normal function pull-up resistor disabled. output, tolerant input
Semiconductor Subject change without notice
RISC Controller
R1100
22.DC/AC Characteristics R1100 Characteristics
Recommended Operating Conidtions Symbol Parameter Supply Voltage Ground Input High Voltage(1) Vih1 Input High Voltage(RES) Vih2 Input High Voltage(X1) Input Voltage Notes RES, pins included Elcetrical Characteristics Symbol Parameter Input Leakage Current Min. -0.5 Typ. Max. Vcc+0.5 Vcc+0.5 Vcc+0.5 Unit
Ili(with Input leakage Current with pull Pull_R enable Ili(with Input leakage Current with pull Pull_R enable Output Leakage Current
Output Voltage Output High Voltage Operating Current
Test Condition Vcc=Vmax Vin=GND Vmax Vcc=Vmax Vin=GND Vmax Vcc=Vmax Vin=GND Vmax Vcc=Vmax Vin=GND Vmax Iol=6mA, Vcc=Vmin Ioh=-6mA Vcc=Vmin 3.6V 80MHz (*2)
Min.
Max.
Unit
-300
-100
Note Vmax=3.6V Vmin=3V Note While Reset Cycle, external MHz, times.
Semiconductor Subject change without notice
RISC Controller
R1100
R1100 Character
CLKOUTA
A19:A0
ADDRESS
ADDRESS DATA
AD15:AD0
UCS,LCS
PCSx,MCSX
S2:S0
STATUS
READ CYCLE
Semiconductor Subject change without notice
RISC Controller
R1100
1.5T-8 T/2-5 2T-5 Unit
Read Cycle Description CLKOUTA high Address Valid address valid active delay inactive delay address Valid delay Adress Hold Data setup Data hold active delay inactive delay Address Valid after inactive width active delay Pulse width inactive delay CLKOUTA HIGH valid UCS, inactive delay PCS, active delay PCS, inactive delay active delay inactive delay active delay inactive delay Status active delay Status inactive delay active delay inactive delay
Semiconductor Subject change without notice
RISC Controller
R1100
CLKOUTA
A19:A0
ADDRESS
AD15:AD0
ADDRESS
DATA
WHB,WLB
UCS,LCS
PCSx,MCSX
DT/R
S2:S0
STATUS
WRITE CYCLE
Semiconductor Subject change without notice
RISC Controller
R1100
1.5t-8 T/2-5 2T-5 Unit
Write Cycle Description CLKOUTA high Address Valid address valid active delay inactive delay address Valid delay Adress Hold active delay width inactive delay Address Valid after inactive active delay Pulse width inactive delay WHB, active delay WHB, inactive delay active delay inactive delay CLKOUTA HIGH valid UCS, inactive delay PCS, active delay PCS, inactive delay active delay inactive delay active delay inactive delay Status active delay Status inactive delay active delay inactive delay
Semiconductor Subject change without notice
CLKOUTA
RISC Controller
R1100
A19:A0
d00C0
c0000
20000
101fc
AD15:AD0
2211
2211
DT/R
S2:S0
DRQ0
Semiconductor Subject change without notice
CLKOUTA
RISC Controller
R1100
A19:A0
c0000
20000 2211
C0002
20002
101fc 4433
AD15:AD0
2211
4433
DT/R
S2:S0
DRQ0
DMA(1)/(2) timing Description confirmed time
Unit
Semiconductor Subject change without notice
CLKOUTA
RISC Controller
R1100
A19:A0
ffff4
ffff6
zZZZZ
fff* fff6
f0000
AD15:AD0
fff6
DT/R
S2:S0
HOLD
HLDA
HOLD/HLDA Timing
Hold timing Description HOLD setup time HLDA valid delay HOLD hold time HLDA valid delay
Unit
Semiconductor Subject change without notice
RISC Controller
R1100
CLKOUTA
ARDY SRDY
SRDY Timing
SRDY timing Description SRDY transition setup time SRDY transition hold time
Unit
Semiconductor Subject change without notice
RISC Controller
R1100
Unit
DRAM Read Cycle Description CLKOUTA Address Valid Data setup time Data hold time CLKOUTA high address valid CLKOUTA Column address valid CLKOUTA active CLKOUTA high inactive CLKOUTA high active CLKOUTA inactive CLKOUTA active CLKOUTA inactive DRAM Write Cycle Description CLKOUTA Address Valid CLKOUTA Data Valid CLKOUTA high address valid CLKOUTA Column address valid CLKOUTA active CLKOUTA high inactive CLKOUTA high active CLKOUTA inactive CLKOUTA active CLKOUTA inactive DRAM Refresh Cycle Description CLKOUTA high Data drive FFFF CLKOUTA high address valid CLKOUTA Column address valid CLKOUTA high active CLKOUTA inactive CLKOUTA high active CLKOUTA inactive CLKOUTA active CLKOUTA inactive
Unit
Unit
Semiconductor Subject change without notice
(PQFP)
RISC Controller
R1100
PACKAGE INFORMATION
23.20 0.25 0.10
20.00
0.10 14.00 SEATING PLANE 0.65
17.20
0.25
0.089
0.22/0.38 0.13/0.23 WITH PLATING 0.13/0.17 0.22/0.30/0.33
BASE METAL
3.40
DETAIL
1.60 2.75 0.12 0.25 DETAIL
0.88 0.15
0.25
Semiconductor Subject change without notice
(LQFP)
RISC Controller
R1100
16.00 14.00
0.10 0.10
0.10 14.00
0.127(TYP)
0.50(TYP) Sealing Plane
0.22
0.05
0.076(MAX)
1.60(MAX)
0.05
0.05
0.60 1.00(REF)
0.10
0.2S(TYP) GAUGE PLANE
1.40
0.15
UNIT:mm
16.00
0.10
Semiconductor Subject change without notice
Rev.
RISC Controller
R1100
24.Revision History
Date 2001/12/19 2002/05/06 2002/07/11 History Formal release Modify JTAG Wait State Description DC/AC Characteristics
Semiconductor Subject change without notice
RISC Controller
R1100
Appendix Application note using R11xx Ver.B
R11xx high speed with volt power supply. maximum internal clock 80MHz, includes PLL. default time factor. Please note following description items when using this high speed CPU: pins definition R11xx same R88xx. There extra register PLLCON offset F8h) R11xx. value Processor Release Level Register (offset 00F4h) number. Adding (bit3) register (offset inserts more wait states. Adding SALEn (bit register (offset F0h) inserts wait state. release number (value F4h) Type Type R1100 C5D9h R1130 05D9h R1110 45D9h R1122 B5D9h R1120 85D9h output volt level input volt volt tolerance. need pure stable volt power supply CPU. need bypass 0.1uF 10uF capacitor near each pin. select factor programming register PLLCON (offset 0F8h). input clock range frequency Example configuration:
Semiconductor Subject change without notice
RISC Controller
R1100
Factor (default) Factor (default) Internal/Output clock 10MHz 20MHz 30MHz 40MHz 50MHz 60MHz 70MHz 80MHz Internal/Output clock 20MHz 40MHz 60MHz 80MHz
Input Clock 10MHz 10MHz 10MHz 10MHz 10MHz 10MHz 10MHz 10MHz Input Clock 20MHz 20MHz 20MHz 20MHz
Value 0F8h 0203h 0207h 020Bh 050Fh 0213h 040Bh 040Dh 051Fh Value 0F8h 0203h 0103h 0105h 0107h
PLLCON register (Offset F8h, reset value 050Fh definition:
15-12 Reserved 11-10 Pre-Divider (PRS) Programming signals pre-divider. Post-Divider (POS) Programming signals post-divider. Reserved Feedback Divider (FBS) Programming signals feedback divider.
CLKOUT FREF
FREF input frequency)
CKOUT Internal/output frequency,
Semiconductor Subject change without notice
RISC Controller
R1100
01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111
00000 00001 00010 00011 00100 00101 00110 00111 Note1 Note2
FREF 280MHz N=3-32 FREF MHz, FREF MHz, FREF
Note3 frequency working range crystal MHz.
UMCS Register (Offset A0h,reset value F033h definition. Reserved
14-12: LB2-LB0 11-8 :Reserved Reserved
R1-R0
Semiconductor Subject change without notice
RISC Controller
R1100
PSEN
PSCON Register Offset F0h, reset value 0000h) definition.
14-12: Reserved
:CAF
:Reserved SALEn, inserts wait state. without wait state more added, should cycle F2-F0.
UCS_ Wait-State Encoding Wait States (Default)
Semiconductor Subject change without notice
Difference Item Operating Vottage Maximum Speed
RISC Controller
R1100
Appendix
series series comparison table
3.3V W/TPLL 80MHz R1100 C5D9h, R1130 O5D9h R1110 45D9h, R1122 B5D9 R1120 85D9h
40MHz R8800C 02D9h, R8810C 02D9h R8820C 02D9h, R8830C 02D9h R8821C 02D9h, R8800D 84D9h R8810D 84D9h, R8820D 04D9h R8830D 04D9h, R8822D 64D9h only this register wait state from option Without bit4
Output/Input Level *Register PLLCON (offset F8h) *Register UMCS (offset A0h) *Register System (offset F0h)
Output 3.3V Input 3.3V/5V tolerance configuration wait state from option Extra SALEn (bit4) inserts wait state
Semiconductor Subject change without notice
Other recent searches
TMS320C6211 - TMS320C6211 TMS320C6211 Datasheet
NL17SZ126 - NL17SZ126 NL17SZ126 Datasheet
IRF3704ZCSPbF - IRF3704ZCSPbF IRF3704ZCSPbF Datasheet
IRF3704ZCLPbF - IRF3704ZCLPbF IRF3704ZCLPbF Datasheet
ENN7129 - ENN7129 ENN7129 Datasheet
MCH3109 - MCH3109 MCH3109 Datasheet
MCH3209 - MCH3209 MCH3209 Datasheet
EM08MR32UM - EM08MR32UM EM08MR32UM Datasheet
M68EM08MR32 - M68EM08MR32 M68EM08MR32 Datasheet
2SK1905 - 2SK1905 2SK1905 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
