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Multi-Endpoint Peripheral Controller with Integrated Port High Pe


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USB97C102
Multi-Endpoint Peripheral Controller with Integrated Port
High Performance Peripheral Controller Engine Integrated Transceiver Serial Interface Engine (SIE) 8051 Microcontroller (MCU) Patented Memory Management Unit (MMU) Channel 8237 Controller (ISADMA) Byte Board Packet Buffer Quasi-ISA Peripheral Interface Snooping Capabilities GPIOs Compatible with SMSC USB97C100 Complete Specification Compatibility Isochronous, Bulk, Interrupt, Control Data Independently Configurable Endpoint Dynamic Hardware Allocation -Packet Buffer Virtual Endpoints Multiple Virtual Endpoints Simultaneously) Multiple Alternate Address Filters Dynamic Endpoint Buffer Length Allocation (01280 Byte Packets) Full (12Mbps) Speed Capability SRAM Buffer Allow Buffer Optimization Maximum Utilization Bandwidth Byte Page Size Pages Maximum Packet Deep Receive Packet Queue Deep Transmit Packet Queue, Endpoint Hardware Generated Packet Header Records Each Packet Status Automatically Simultaneous Arbitration Between MCU, SIE, Accesses Extended Power Management Standard 8051 "Stop Clock" Modes Additional Suspend Resume Events Internal 8MHz Ring Oscillator Immediate Power Code Execution Taps Clock Switching Independent Clock/Power Management SIE, MMU, Capability with Memory Four Independent Channels Transfer Between Internal External Memory Transfer Between Internal Memory External Master Capable Scatter Gather Four Independent Channels Transfers Programmed Occur Consecutively Without InterventionExternal Memory Interface Byte Code Data Storage Windows Flash, SRAM, EPROM Downloadable USB, Serial Port, Peripheral Quasi-ISA Interface Allows Interface "Legacy" Peripheral Devices Memory Space Window Space Byte Window External Interrupt Inputs Channels Variable Cycle Timing Data Path Volt, Power Operation Volt Tolerant Operation Signal Pins Board Crystal Driver Circuit Package
GENERAL DESCRIPTION
USB97C102 flexible, general purpose peripheral interface controller ideally suited multiple endpoint applications. USB97C102 provides ISA-like interface, which will allow virtually peripheral placed connection. unique dynamic buffer architecture overcomes throughput disadvantages existing fixed FIFO buffer schemes allowing maximum utilization connection's overall bandwidth. This architecture minimizes integrated microcontroller's participation data flow, allowing back-to-back packet transfers block oriented devices. efficiency this architecture allows floppy drives coexist with other peripherals such serial parallel ports single link.
SMSC USB97C102
Rev. 03/23/2000
USB97C102 allows external program code downloaded over allow easy implementation varied peripheral Device Classes combinations. This also provides method convenient field upgrades modifications.
2000 STANDARD MICROSYSTEMS CORPORATION (SMSC)
Arkay Drive Hauppauge, 11788 (631) 435-6000 (631) 273-3123
Standard Microsystems registered trademark Standard Microsystems Corporation, SMSC trademark Standard Microsystems Corporation. Product names company names trademarks their respective holders. Circuit diagrams utilizing SMSC products included means illustrating typical applications; consequently complete information sufficient construction purposes necessarily given. Although information been checked believed accurate, responsibility assumed inaccuracies. SMSC reserves right make changes specifications product descriptions time without notice. Contact your local SMSC sales office obtain latest specifications before placing your product order. provision this information does convey purchaser semiconductor devices described licenses under patent rights SMSC others. sales expressly conditional your agreement terms conditions most recently dated version SMSC's standard Terms Sale Agreement dated before date your order (the "Terms Sale Agreement"). product contain design defects errors known anomalies which cause product's functions deviate from published specifications. Anomaly sheets available upon request. SMSC products designed, intended, authorized warranted life support other application where product failure could cause contribute personal injury severe property damage. such uses without prior written approval Officer SMSC further testing and/or modification will fully risk customer. Copies this document other SMSC literature, well Terms Sale Agreement, obtained visiting SMSC's website http://www.smsc.com. SMSC DISCLAIMS EXCLUDES WARRANTIES, INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES MERCHANTABILITY, FITNESS PARTICULAR PURPOSE, TITLE, AGAINST INFRINGEMENT, WARRANTIES ARISING FROM COURSE DEALING USAGE TRADE. EVENT SHALL SMSC LIABLE DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, CONSEQUENTIAL DAMAGES; LOST DATA, PROFITS, SAVINGS REVENUES KIND; REGARDLESS FORM ACTION, WHETHER BASED CONTRACT; TORT; NEGLIGENCE SMSC OTHERS; STRICT LIABILITY; BREACH WARRANTY; OTHERWISE; WHETHER REMEDY HELD HAVE FAILED ESSENTIAL PURPOSE, WHETHER SMSC BEEN ADVISED POSSIBILITY SUCH DAMAGES.
SMSC USB97C102
Page
Rev. 03/23/2000
TABLE CONTENTS
FEATURES GENERAL DESCRIPTION CONFIGURATION DESCRIPTION FUNCTIONS. BUFFER TYPE DESCRIPTIONS. CODE DEBUGGER INTERFACE. FUNCTIONAL DESCRIPTION. Serial Interface Engine (SIE) Micro Controller Unit (MCU) SIEDMA Memory Management Unit (MMU) Register Description ISADMA Applications Code Space. Data Space. ISADMA Memory Map. Block Register Summary SGDMA Block Register Summary Block Register Summary Block Register Summary REGISTER DESCRIPTION Runtime Registers. FIFO Status Registers Interface Registers 8237 (ISADMA) REGISTER DESCRIPTION Memory Runtime Registers MEMORY MANAGEMENT UNIT (MMU) REGISTER DESCRIPTION Interface Registers. Free Pages Register. BYTE DEEP COMPLETION FIFO REGISTER FIFO Register SERIAL INTERFACE ENGINE (SIE) REGISTER DESCRIPTION Packet Header Definition. Interface Registers. ALTERNATE ADDRESS ENDPOINT MAPPING. Multiple Endpoint Mapping BLOCK System Interface Unit Interface Unit Block Register Summary. Disconnecting from function USB97C100 Compatibility Mode PARAMETERS MAXIMUM GUARANTEED RATINGS PARAMETERS PARAMETERS PARAMETERS MECHANICAL OUTLINE
SMSC USB97C102
Page
Rev. 03/23/2000
CONFIGURATION
nMEMW nMEMR nDAK1 nDAK3 nDAK0 nDAK2 DRQ0 DRQ1 DRQ2 DRQ3 nIOW SA11 SA12 nIOR
SA10 SA13 SA14 SA15 SA16 SA17 SA18 SA19 IRQ3 IRQ2 IRQ1 IRQ0 nTEST PWRGD RESET_IN TST_OUT XTAL1 XTAL2 CLKOUT GPIO0 GPIO1 GPIO2 GPIO3 GPIO4
nMASTER READY EXTCLK FALE nPWREN5 nPWROK5 nPWREN4 nPWROK4 nPWREN3 nPWROK3 nPWREN2 nPWROK2 USBD+ USBDPD+5 PD-5 PD+4 PD-4 PD+3 PD+2 PD-3 PD-2 AVDD FA19 FA18 FA11 FA13 FA14 FA17 nFWR FA16
USB97C102
GPIO5
GPIO6
GPIO7
nFCE
FA10
FA12
nFRD
FIGURE CONFIGURATION
SMSC USB97C102
Page
FA15
Rev. 03/23/2000
DESCRIPTION FUNCTIONS
Table USB97C102 Configuration NUMBER SYMBOL READY DESCRIPTION INTERFACE Channel ready when high. memory slave devices this signal lengthen cycle from default time. Extending length cycle only done when cycles derived from Internal controller core. 8051 generated Memory accesses cannot will extended even READY asserted external slave device. external slave device negates this signal after decoding valid address sampling command signals (nIOW, nIOR, nMEMW, nMEMR). When slave's access completed, this signal should allowed float high. Request channels 3-0; active high. These signals used request service from controller. requesting device must hold request signal until controller drives appropriate acknowledge signal (nDACK[3:0]). Acknowledge channels 3-0; active low. These signals used indicate requesting device that been granted bus. Terminal Count; active high. This signal used indicate that transfer completed. System Address These signals address memory devices bus. System Data These signals used transfer data between system devices. Address Enable This signal indicates address validation devices. When this signal indicates that slave respond addresses commands bus. This signal high during cycles prevent slaves from interpreting cycles valid cycles. Write; active low. This signal indicates addressed slave latch data from bus. Read; active low. This signal indicates addressed slave drive data bus. Memory read; active This signal indicates addressed memory slave drive data bus. Memory write; active This signal indicates addressed memory slave latch data from bus. External master, active This signal forces USB97C102 immediately tri-state external bus, even internal transactions complete. shared signals tri-stated, except 8237 nDACKs, which used gang mode provide external bus-master handshaking. This must used with some handshake mechanism avoid data corruption. Interrupt Request 3-0; active high These signals driven devices interrupt 8051. BUFFER TYPE
104, 106, 108,
DRQ[3:0]
105, 107, 109, 19-13, 127-7, 9-12 112-115, 117120
nDACK [3:0] SA[19:0] SD[7:0]
I/O8
nIOW
nIOR
nMEMR
nMEMW
nMASTER
21-24
IRQ[3:0]
SMSC USB97C102
Page
Rev. 03/23/2000
NUMBER
SYMBOL XTAL1/ Clock XTAL2 EXTCLK
DESCRIPTION 24MHz Crystal clock input. This connected terminal crystal connected external clock when crystal used. 24MHz Crystal This other terminal crystal. Alternate clock 8237 external clock used internal 8237. This clock used synchronize 8237 other devices. Clock output. This clock frequency same 8051 running clock. This clock stopped when 8051 stopped. Peripherals should this clock when they expected when 8051 stopped. This clock used synchronize other devices 8051. INTERFACE Upstream Connection signals These point-to-point signals driven differentially. Power Enable signal this applies power associated port (port through #2). This output signal active low. Over-Current Sense Input indicate over-current condition powered device external downstream port (port through #2). Downstream Connection Signals These point-to-point signals driven differentially. They used standard "Walk Port Connections FLASH INTERFACE Flash Data These signals used transfer data between 8051 external FLASH. Flash Address These signals address memory locations within FLASH.
BUFFER TYPE ICLKx
OCLKx ICLK
CLKOUT
45-52
USBDUSBD+ nPWREN[5:2]
IOUSB
nPWROK[5:2]
nPD+[5:2], -[5:2]
IOUSB
FD[7:0]
62-58, 56-54 25,57,76, 101,121 41-34
FA[19:0]
NFRD NFWR nFCE FALE
Flash Read; active Flash Write; active Flash Chip Select; active Flash address latch enable POWER SIGNALS +3.3 Volt Power Ground Reference
MISCELLANEOUS GPIO[7:0] General Purpose I/O. These pins configured inputs outputs under software control. Active high input. This signal used indicate that chip that good power level been reached. When inactive/low, pins Tri-stated except TST_OUT generated.
Page
I/O24
PWRGD
SMSC USB97C102
Rev. 03/23/2000
NUMBER
SYMBOL RESET_IN
DESCRIPTION Power reset; active high This signal used system reset chip. also generates internal POR. XNOR Chain output This signal used testing chip internal XNOR Chain. Test input This signal manufacturing test pin. User pull high leave unconnected.
BUFFER TYPE
TST_OUT nTEST
BUFFER TYPE DESCRIPTIONS
BUFFER I/O8 I/O16 I/ODP24 ICLKx OCLKx ICLK IOUSB Table USB97C102 Buffer Type Description DESCRIPTION Input pull-up) Input 90µA with internal pull-up Output with drive Input/output with drive Input/output with 16mA drive Output, 24mA sink, 12mA source. Input/Output drain 24mA sink, 12mA source with 90µA pull-up XTAL clock input XTAL clock output Clock input (TTL levels) Defined specification V1.1
CODE DEBUGGER INTERFACE This interface made available driving NTEST=0 TSTOUT=0 this mode, TSTOUT input chip). this mode, functions defined follows: NUMBER 6258, 56-54 112-115, 117-120 BUFFER TYPE
SYMBOL FA[15:0]
DESCRIPTION 8051 Address
NFRD NFWR FD[7:0] nFCE FA19 FA18 FA17 FA16
Data Read Strobe; active Data Write; active Data 8051 T1IN timer signal 8051 T0IN timer signal 8051 WAKE interrupt signal 8051 INT1 interrupt signal 8051 INT0 interrupt signal
I/O8
SMSC USB97C102
Page
Rev. 03/23/2000
USB97C102 BLOCK DIAGRAM
Upstream Device
Walk-up Ports
Dual Speed XCVR
Upstream Device
Dual Speed XCVR
Dual Speed XCVR
Dual Speed XCVR
Serial Interface Engine
Point Control
Dual Speed XCVR
Internal
Memory Management Unit
Queue
FD[7:0]
Arbiter
Data Buffer
Flash/ SRAM Interface
nFRD nFWR nFCE
8051 SGDMA Control
SGDMA WRAPPER
Start Queue Ctrl
8051
General Purpose
GPIO[7:0]
GPIO
8237
Done Queue Ctrl
97C102 Block Diagram
IRQ[3:0]
SD[7:0], SA[19:0]
NIOW, nIOR, nMEMW, nMEMR
DRQ[3:0], nDACK[3:0], TC,AEN
SMSC USB97C102
Page
Rev. 03/23/2000
FUNCTIONAL DESCRIPTION
USB97C102 incorporates Serial Interface Engine (SIE), 8051 Microcontroller Unit (MCU), Serial Interface Engine (SIEDMA), programmable 8237 controller (ISADMA), bytes SRAM data stream buffering, patented (Memory Management Unit) dynamically manage buffer allocation. semiautomatic nature SIEDMA, ISADMA, blocks frees provide enumeration, protocol power management. arbiter integrated into assures that transparent access between SIEDMA, ISADMA, SRAM occurs. Serial Interface Engine (SIE) low-level protocol interpreter. controls protocol, packet generation/extraction, conversion, coding/decoding, stuffing, NRZI coding/decoding. dynamically configured having combination 0-16 transmit, 0-16 receive endpoints, independent addresses. There alternate local address. alternate addresses, example, used addresses. also "Receive Addresses" snooping. Micro Controller Unit (MCU) 8051 embedded controller static CMOS which fully software compatible with industry standard Intel 80C51 micro-controller. internal registers USB97C102 blocks mapped into external memory space MCU. detailed description microcontroller's internal registers instruction found "USB97C102 Programmer's Reference Guide". SIEDMA This simplified controller, which automatically transfers data between SRAM control. SIEDMA appends status header containing frame number, endpoint, byte count each incoming packet before notifying arrival. This block's operation transparent firmware. Memory Management Unit (MMU) Register Description This patented consists buffer which allocated pages bytes. Packets allocated with pages each (1280 bytes). buffer therefore concurrently hold packets with byte payload. isochronous pipes, hold packets with 1023 byte payload each, still have room more byte packets. This block supports independent transmit FIFO queues (one each endpoint), single receive queue. Each endpoint have five transmit packets queued. receive queue accept packets size combination before forcing host back off. arbiter makes single-ported buffer appear simultaneously available MCU, four channels ISADMA, SIEDMA receiving transmitting packets. ISADMA This industry standard 8237 controller transfer data between SRAM under control. This contains status control registers which accessed programmed 8051 controller. 8237 internally, external clock synchronize with another source. SGDMA four channel Scatter-Gather will 8237 controller once indicates which packets transfer. SGDMA performs scattering/gathering operations from to/from external memory. also allows device to/from transfer. Applications USB97C102 enables entirely applications, well form factors existing Legacy applications. PC98 compliance encourages elimination ofDMA, addressing conflicts total on-board elimination. With USB97C102, eliminated from motherboards without sacrificing huge infrastructure Legacy ports. moving these devices flexible bus, form factors such monitor peripheral clusters also possible (mouse, keyboard, serial, parallel ports connected monitor). system designers longer constrained physical borders motherboard. USB97C102 ideal peripherals which require considerable bandwidth, such floppy drives, audio, etc. following block diagrams illustrate these applications.
SMSC USB97C102
Page
Rev. 03/23/2000
TYPICAL MOTHERBOARD APPLICATION
Upstream
South Bridge
97C102
37C67X
Floppy PS/2 Serial Parallel
AUDIO
SPKR
Downstream Walkup Ports
FIGURE USB97C102 CONFIGURED MOTHERBOARD
TYPICAL MONITOR APPLICATION
FLOPPY Upstream
37C67X
PS/2
97C102 CODEC
SERIAL/FIR
PARALLEL Downstream Walkup Ports
FIGURE USB97C102 CONFIGURED MONITOR, HUB, PERIPHAL CONSTELLATION
SMSC USB97C102
Page
Rev. 03/23/2000
TYPICAL FLOPPY DRIVE APPLICATION
Upstream 37C78
97C102
Downstream Walkup Ports
FIGURE USB97C102 CONFIGURED FLOPPY DRIVE APPLICATION WALKUP PORTS
TYPICAL SIGNAL CONNECTIONS
SRAM UPSTREAM
SD[7.0]
SA[10.0]
UART
nDACK[3.0]
USB97C102
DRQ[3.0] nIOR nIOW
24MHz
FLASH
FIGURE USB97C102 CONFIGURED WITH CONTROLLER WALKUP PORTS
SMSC USB97C102
Page
FA[19.0]
FD[7.0]
nFRD nFWR nFCE
DOWNSTREAM WALKUP PORTS
FDC37C669FR
IRQ[3.0]
nMEMW nMEMR
Rev. 03/23/2000
Memory memory follows from 8051's viewpoint: Code Space 8051 ADDRESS 0xC000-0xFFFF Table Code Memory CODE SPACE Movable FLASH page pages External FLASH (0x0000-0xFFFF) selected MEM_BANK Register Default: 0x40000x7FFF FLASH Movable FLASH page pages External FLASH (0x0000-0xFFFF) selected MEM_BANK2 Register Default: 0x0000-0x3FFF FLASH Movable FLASH page pages External FLASH (0x0000-0xFFFF) selected MEM_BANK Register Default: 0x40000x7FFFLASH Fixed FLASH Page 0x0000-0x3FFF FLASH ACCESS External FLASH
0x8000-0xBFFF
External FLASH
0x4000-0x7FFF
External FLASH
0x0000-0x3FFF
External FLASH
FLASH Address
8051 External Data Address Space
0xFFFF -16K Flash Page 0xC000 Flash Page 0x8000 Flash pages 0x4000 Fixed Flash Page
ister
EMBAN ister
Selecte
External Code Space Diagram
SMSC USB97C102
Page
Rev. 03/23/2000
Data Space Table Data Memory DATA SPACE Movable FLASH page pages External FLASH (0x00000-0xFFFFF) selected MEM_BANK Register Default: 0x040000x07FFF FLASH Movable FLASH page pages External FLASH (0x00000-0xFFFFF) selected MEM_BANK2 Register Default: 0x0040000x037FFF FLASH 0x7F80-0x7F9F 0x7F70-0x7F7F 0x7F50-0x7F6F 0x7F20-0x7F2F Power 0x7F10-0x7F1F Configuration 0x7F00-0x7F0F Runtime Note 0x6000 Data Register 0x5000-0x5FFF MEMORY Window 0x4000-0x40FF Window
8051 ADDRESS 0xC000-0xFFFF
ACCESS External FLASH
0x8000-0xBFFF
External FLASH
0x7000-0x7FFF
Internal
0x6000-0x6FFF 0x5000-0x5FFF 0x4000-0x4FFF 0x3000-0x3FFF 0x2000-0x2FFF 0x1000-0x1FFF 0x0000-0x00FF
Internal used used used Internal
Registers SFR's
Note MCU, MMU, block registers external 8051, internal USB97C102. These addresses will appear FLASH bus, read write strobes will inhibited.
SMSC USB97C102
Page
Rev. 03/23/2000
Address
(0x800) Total Space 0xFFFF
FLASH Address
8051 External Data Address Space
Flash Page 0xC000 Flash Page
Sele cted
iste
Selected MBANK2" gister
0x8000
0x5000 0x4000
0x100h
0x0000
External Data Memory Diagram
SMSC USB97C102
Page
Rev. 03/23/2000
ISADMA Memory Internal Memory buffer virtualized into 8237's address independent blocks. After allocated given packet size specific PNR, will make that packet appear 8237 contiguous block data address ranges depicted table Table ISADMA Memory 8237 MEMORY ADDRESS DESCRIPTION 0x8000-0xFFFF blocks Window Packet
0x0000-0x7FFF
Window External
Block Register Summary Table Block Register Summary DESCRIPTION RUNTIME REGISTERS ISR_0 INT0 Source Register IMR_0 INT0 Mask Register ISR_1 INT1 Source Register IMR_1 INT1 Mask Register DEV_REV Device Revision Register DEV_ID Device Register UTILITY REGISTERS GPIOA_DIR GPIO Configuration Register GPIOA_OUT GPIO Data Output Register GPIOA_IN GPIO Data Input Register UTIL_CONFI Miscellaneous Configuration Register POWER MANAGEMENT REGISTERS CLOCK_SEL 8051 8237 Clock Select Register MEM_BANK2 Flash Bank Select MEM_BANK Flash Bank Select WU_SRC_1 Wakeup Source WU_MSK_1 Wakeup Mask WU_SRC_2 Wakeup Source WU_MSK_2 Wakeup Mask CONTROL REGISTERS GP1Data FIFO Data Port GP1Status FIFO status Port GP2Data FIFO Data Port GP2Status FIFO status Port GP3Data FIFO Data Port GP3Status FIFO status Port GP4Data FIFO Data Port GP4Status FIFO status Port BUS_REQ Request Register IOBASE 8051 Window Base Register MEMBASE 8051 Memory Window Base Register BUS_STAT ISADMA Request Status BUS_MASK ISADMA Request Interrupt Mask MCU_TEST2 Reserved Test MCU_TEST1 Reserved Test NAME
ADDRESS 7F00 7F01 7F02 7F03 7F06 7F07 7F18 7F19 7F1A 7F1B
PAGE
7F27 7F28 7F29 7F2A 7F2B 7F2C 7F2D 7F10 7F11 7F12 7F13 7F14 7F15 7F16 7F17 7F70 7F71 7F72 7F73 7F74 7F7E 7F7F
SMSC USB97C102
Page
Rev. 03/23/2000
SGDMA Block Register Summary Table SGDMA Block Register Summary NAME DESCRIPTION CHANNEL REGISTERS SGDMA_START_FIFO0 Packet Number Start FIFO Register SGDMA_DONE_FIFO0 Packet Number Done FIFO Register SGDMA_ADHI0 Address High Byte Register SGDMA_ADLO0 Address Byte Register SGDMA_SIZEHI0 Transfer Size High Register SGDMA_SIZELO0 Transfer Size Register SGDMA_TOTAL_PKTS0 Total Packets Channel Register SGDMA_DONE_PKTS0 Total Packets Done FIFO Register SGDMA_STS0 Status Register SGDMA_CMD0 Command Register CHANNEL REGISTERS SGDMA_START_FIFO1 Packet Number Start FIFO Register SGDMA_DONE_FIFO1 Packet Number Done FIFO Register SGDMA_ADHI1 Address High Byte Register SGDMA_ADLO1 Address Byte Register SGDMA_SIZEHI1 Transfer Size High Register SGDMA_SIZELO1 Transfer Size Register SGDMA_TOTAL_PKTS1 Total Packets Channel Register SGDMA_DONE_PKTS1 Total Packets Done FIFO Register SGDMA_STS1 Status Register SGDMA_CMD1 Command Register CHANNEL REGISTERS SGDMA_START_FIFO2 Packet Number Start FIFO Register SGDMA_DONE_FIFO2 Packet Number Done FIFO Register SGDMA_ADHI2 Address High Byte Register SGDMA_ADLO2 Address Byte Register SGDMA_SIZEHI2 Transfer Size High Register SGDMA_SIZELO2 Transfer Size Register SGDMA_TOTAL_PKTS2 Total Packets Channel Register SGDMA_DONE_PKTS2 Total Packets Done FIFO Register SGDMA_STS2 Status Register SGDMA_CMD2 Command Register CHANNEL REGISTERS SGDMA_START_FIFO3 Packet Number Start FIFO Register SGDMA_DONE_FIFO3 Packet Number Done FIFO Register SGDMA_ADHI3 Address High Byte Register SGDMA_ADLO3 Address Byte Register SGDMA_SIZEHI3 Transfer Size High Register SGDMA_SIZELO3 Transfer Size Register SGDMA_TOTAL_PKTS3 Total Packets Channel Register SGDMA_DONE_PKTS3 Total Packets Done FIFO Register SGDMA_STS3 Status Register SGDMA_CMD3 Command Register REGISTERS PIO_ADHI Upper Byte Address PIO_ADMID Middle Byte Address PIO_ADLO Lower Byte Address PIO_DATA Data Register PIO_CSR Command Register
ADDRESS 7FB0 7FB1 7FB2 7FB3 7FB4 7FB5 7FB6 7FB7 7FB8 7FB9 7FBA 7FBB 7FBC 7FBD 7FBE 7FBF 7FC0 7FC1 7FC2 7FC3 7FC4 7FC5 7FC6 7FC7 7FC8 7FC9 7FCA 7FCB 7FCC 7FCD 7FCE 7FCF 7FD0 7FD1 7FD2 7FD3 7FD4 7FD5 7FD6 7FD7 7FD8 7FD9 7FDA 7FDB 7FDC
PAGE
SMSC USB97C102
Page
Rev. 03/23/2000
Block Register Summary Table Block Register Summary DESCRIPTION REGISTERS MMU_DATA 8051-MMU Data Window Register FIFO TX_FIFO0 TX_FIFO Counter TX_FIFO1 TX_FIFO Counter TX_FIFO2 TX_FIFO Counter TX_FIFO3 TX_FIFO Counter TX_FIFO4 TX_FIFO Counter TX_FIFO5 TX_FIFO Counter TX_FIFO6 TX_FIFO Counter TX_FIFO7 TX_FIFO Counter TX_FIFO8 TX_FIFO Counter TX_FIFO9 TX_FIFO Counter TX_FIFOA TX_FIFO Counter TX_FIFOB TX_FIFO Counter TX_FIFOC TX_FIFO Counter TX_FIFOD TX_FIFO Counter TX_FIFOE TX_FIFO Counter TX_FIFOF TX_FIFO Counter 8051-MMU Pointer Register (Low) 8051-MMU Pointer Register (High) MMUTX_SEL 8051-MMU FIFO Select Commands MMUCR 8051-MMU Command Register 8051-MMU Allocation Result Register 8051-MMU Packet Number Register PAGS_FREE Pages Free TX_MGMT Management Register RXFIFO Packet FIFO Register (All EPs) POP_TX FIFO TXSTAT_A Packet FIFO Status Register (EP0-3) TXSTAT_B Packet FIFO Status Register (EP4-7) TXSTAT_C Packet FIFO Status Register (EP8-11) TXSTAT_D Packet FIFO Status Register (EP12-15) MMU_TESTx Reserved Test MMU_TESTx Reserved Test MMU_TESTx Reserved Test TX_MGMT Management Register MMU_TESTx Reserved Test MMU_TESTx Reserved Test NAME
ADDRESS 6000 7F40 7F41 7F42 7F43 7F44 7F45 7F46 7F47 7F48 7F49 7F4A 7F4B 7F4C 7F4D 7F4E 7F4F 7F50 7F51 7F52 7F53 7F54 7F55 7F56 7F57 7F58 7F59 7F60 7F61 7F62 7F63 7F64 7F65 7F66 7F67 7F6E 7F6F
PAGE
Block Register Summary Table Block Register Summary DESCRIPTION Control Registers EP_CTRL0 Endpoint Control Register EP_CTRL1 Endpoint Control Register EP_CTRL2 Endpoint Control Register EP_CTRL3 Endpoint Control Register EP_CTRL4 Endpoint Control Register EP_CTRL5 Endpoint Control Register EP_CTRL6 Endpoint Control Register EP_CTRL7 Endpoint Control Register EP_CTRL8 Endpoint Control Register EP_CTRL9 Endpoint Control Register EP_CTRL10 Endpoint Control Register NAME
ADDRESS 7F80 7F81 7F82 7F83 7F84 7F85 7F86 7F87 7F88 7F89 7F8A
PAGE
SMSC USB97C102
Page
Rev. 03/23/2000
ADDRESS 7F8B 7F8C 7F8D 7F8E 7F8F 7F90 7F91 7F92 7F93 7F94 7F95 7F96 7F97 7F98 7F99 7F9A 7F9B 7F9C 7F9D 7F9E 7F9F 7FA9 7FAA 7FAB 7FAC 7FAD 7FAE 7FAF 7FEC 7FED 7FEE 7FEF
NAME EP_CTRL11 EP_CTRL12 EP_CTRL13 EP_CTRL14 EP_CTRL15 FRAMEL FRAMEH SIE_ADDR SIE_STAT SIE_CTRL1 SIE_TST1 SIE_TST2 SIE_EP_TEST SIE_CONFIG ALT_ADDR1 SIE_TST3 SIE_TST4 SIE_TST5 SIE_TST6 ALT_ADDR2 ALT_ADDR3 SIE_CTRL2 EPCMD NONCTRL_EP1 NONCTRL_EP2 Reserved MMPCMD MMPSTATE IN_NAKLO IN_NAKHI OUT_NAKLO OUT_NAKHI
DESCRIPTION Endpoint Control Register Endpoint Control Register Endpoint Control Register Endpoint Control Register Endpoint Control Register Frame Count Frame Count High Local Address Register Status Register Control Register Reserved Test Register Reserved Test Register Reserved Test Register Configuration Register Secondary Local Address Register Reserved Test Register Reserved Test Register Reserved Test Register Reserved Test Register Secondary Local Address Register Secondary Local Address Register Control Register Endpoint Command Register Non-Control Endpoint Register (High) Non-Control Endpoint Register (Low) Reserved Mem-Management Command Register Mem-Management State Register Register Register High Register Register High
PAGE
ADDRESS 7FA0 7FA1 7FA2
7FA3
7FA4
Table Block Register Summary NAME DESCRIPTION REGISTERS IdVendor-Low byte Vendor little endian format Byte (Bit LSB) IdVendor-High High byte Vendor little endian Byte format (Bit LSB) IdProduct-Low byte Product value little endian Byte format (Bit LSB). This value initialized firmware upon initialization/power This value must initialized prior device participating enumeration transactions. IdProduct-High High byte Product value little endian Byte format (Bit LSB). This value initialized firmware upon initialization/power This value must initialized prior device participating enumeration transactions. BcdDevice This 8-bit value defines device Byte release number, which assigned system manufacture.
PAGE
SMSC USB97C102
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Rev. 03/23/2000
ADDRESS 7FA5
NAME BcdDevice High Byte HubControl1
7FA6
DESCRIPTION REGISTERS This 8-bit value defines device release number, which assigned system manufacture. Control register
PAGE
REGISTER DESCRIPTION Runtime Registers Table Interrupt Source Register ISR_0 (0x7F00 RESET=0x00) INTERRUPT SOURCE REGISTER NAME DESCRIPTION IRQ3 External interrupt input. Inactive Active IRQ2 External interrupt input. Inactive Active IRQ1 External interrupt input. Inactive Active IRQ0 External interrupt input. Inactive Active RX_PKT Packet Number (PNR) been successfully queued RXFIFO. TX_EMPTY Whenever enabled Endpoint's FIFO becomes empty. This will occur when last queued packet queues successfully transferred Host. TX_PKT Packet successfully transmitted. ISADMA When selected 8237 channels BUS_STAT/BUS_MASK register pair either reached Terminal Count have Request Pending. bits this register cleared writing corresponding bit. Note TX_EMPTY useful warning performance degradation. This interrupt indicates that next time Host polls affected endpoint, will receive that endpoint, thus reducing effective overall bandwidth retries. Firmware must TX_STAT determine which endpoint queue empty. Note When ISADMA causes interrupt, 8237 CH_STAT register should also read serviced when causing interrupt rearmed. When ISR_0 read ISADMA cleared, other lowto-high transitions BUS_STAT register bits that masked will still cause interrupt. Note expected token (when isochronous mode) does arrive, packet number will removed from TX_FIFO saved TX_COMPLETION_FIFO TX_PKT interrupt will sent MCU. responsibility remove pages assigned that packet. (Note masks TX_PKT interrupt, will notified).
SMSC USB97C102
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Table Interrupt Mask IMR_0 (0x7F01- RESET=0xFF) INTERRUPT MASK REGISTER NAME DESCRIPTION IRQ3 External interrupt input mask Enable Interrupt Mask Interrupt IRQ2 External interrupt input mask Enable Interrupt Mask Interrupt IRQ1 External interrupt input mask Enable Interrupt Mask Interrupt IRQ0 External interrupt input mask Enable Interrupt Mask Interrupt RX_PKT Received Packet Interrupt Mask Enable Interrupt Mask Interrupt TX_EMPTY Transmit Queue Empty Interrupt Enable Interrupt Mask Interrupt TX_PKT Transmit Packet Interrupt Mask Enable Interrupt Mask Interrupt ISADMA ISADMA Status Change Interrupt Mask Enable Interrupt Mask Interrupt Table Interrupt Source Register ISR_1 (0x7F02- RESET=0x00) INTERRUPT SOURCE REGISTER NAME DESCRIPTION [7:5] Reserved Reserved returned Idle State. Marks each transaction. When Start Frame token correctly decoded. Generated write strobe Frame Count register. ALLOC Software Allocation Request complete interrupt. This interrupt generated hardware (SIEDMA) allocation requests. RX_OVRN receive condition occurred that will stop current receive buffer processed. automatically recovers from this condition after cause been alleviated (e.g. partially allocated packets will released. Note PWR_MNG wakeup power management event WU_SRC_1 WU_SRC_2 registers gone active. Note bits this register cleared writing corresponding bit. Note RX_OVRN interrupt should considered firmware general Receive Overrun SIE, meaning that packet destined buffer could received acknowledged back Host. firmware should check Packet Number FIFO Register (RXFIFO) full. empty, then there many transmit packets queued device receive anything, last packet have been corrupted wire. empty, then more receive packets must dequeued before device continue receive packets. normal course operation, should respond RX_PKT interrupt often possible buffering logic job. Note RX_OVRN Interrupt also triggered non-isochronous packet exceeds bytes isochronous packet exceeds programmed limit (SIE_CTRL2 Page 58). When packet that long detected, packet will discarded from memory Overrun Interrupt will triggered. non-isochronous packets, hardware will stall Endpoint handshake after reception.
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Note RX_OVRN Interrupt also triggered Enpoint receives packet while stalled. packet will discarded from memory. Table Interrupt Mask IMR_1 (0x7F03- RESET=0xFF) INTERRUPT MASK REGISTER NAME DESCRIPTION [7:5] Reserved Reserved interrupt mask Enable Interrupt Mask Interrupt Start Frame Interrupt Mask Enable Interrupt Mask Interrupt ALLOC Software Allocation Complete Interrupt Mask Enable Interrupt Mask Interrupt RX_OVRN Receive Overrun Interrupt Mask Enable Interrupt Mask Interrupt PWR_MNG Power Management Wakeup Interrupt Mask Enable Interrupt Mask Interrupt Table Device Revision Register DEV_REV (0x7F06- RESET=0x00) DEVICE REVISION REGISTER NAME DESCRIPTION [7:0] `00' This register defines additional revision information 0x00 used internally SMSC. value silicon revision dependent. Table Device Identification Register DEV_ID (0x7F07- RESET=0x26) DEVICE IDENTIFICATION REGISTER NAME DESCRIPTION [7:0] '26' This register defines additional revision information 0x26 used internally SMSC Table 8051 FIFO1 GP_FIFO1 (0x7F10- RESET=0xXX) NAME [7:0] GP_FIFO1 8051 FIFO1 DESCRIPTION byte deep FIFO. This data FIFOs must read unless associated status indicates that FIFO empty. Table 8051 FIFO2 GP_FIFO2 (0x7F12 RESET=0xXX) NAME [7:0] GP_FIFO2 8051 FIFO2 DESCRIPTION byte deep FIFO. This data FIFOs must read unless associated status indicates that FIFO empty. Table 8051 FIFO3 GP_FIFO3 (0x7F14 RESET=0xXX) NAME [7:0] GP_FIFO3 8051 FIFO3 DESCRIPTION byte deep FIFO. This data FIFOs must read unless associated status indicates that FIFO empty.
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Table 8051 FIFO4 GP_FIFO4 (0x7F16 RESET=0xXX) NAME [7:0] GP_FIFO4 8051 FIFO4 DESCRIPTION byte deep FIFO. This data FIFOs must read unless associated status indicates that FIFO empty.
FIFO Status Registers Table 8051 FIFO STATUS GPFIFO1_STS (0x7F11 RESET=0x01) 8051 FIFO STATUS NAME DESCRIPTION Reserved Reserved GPFIFO1_FULL FIFO full status FULL FULL GPFIFO1_EMPTY FIFO empty status more packet Empty Table 8051 FIFO STATUS GPFIFO2_STS (0x7F13 RESET=0x01) 8051 FIFO STATUS NAME DESCRIPTION Reserved Reserved GPFIFO2_FULL FIFO full status FULL FULL GPFIFO2_EMPTY FIFO empty status more packet Empty Table 8051 FIFO STATUS GPFIFO3_STS (0x7F15 RESET=0x01) 8051 FIFO STATUS NAME DESCRIPTION Reserved Reserved GPFIFO3_FULL FIFO full status FULL FULL GPFIFO3_EMPTY FIFO empty status more packet Empty Table 8051 FIFO STATUS GPFIFO4_STS (0x7F17 RESET=0x01) 8051 FIFO STATUS NAME DESCRIPTION Reserved Reserved GPFIFO4_FULL FIFO full status FULL FULL GPFIFO4_EMPTY FIFO empty status more packet Empty
[7:2]
[7:2]
[7:2]
[7:2]
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Table GPIO Direction Register GPIOA_DIR (0x7F18- RESET=0x00) UTILITY REGISTERS NAME DESCRIPTION GPIO7 GPIO7 Direction GPIO6 GPIO6 Direction GPIO5 GPIO5 Direction GPIO4/SOF GPIO4 Direction GPIO3/T1 GPIO3 Direction GPIO2/T0 GPIO2 Direction GPIO1/TXD GPIO1 Direction GPIO0/RXD GPIO0 Direction
Note: Timer inputs T[1:0] configured outputs left unconnected that software write bits trigger timer. Otherwise, Timer inputs used count external events internal receptions. Table GPIO Output Register GPIO DATA OUTPUT GPIOA_OUT (0x7F19- RESET=0x00) REGISTER NAME DESCRIPTION GPIO7 GPIO7 Output Buffer Data GPIO6 GPIO6 Output Buffer Data GPIO5 GPIO5 Output Buffer Data GPIO4/SOF GPIO4 Output Buffer Data GPIO3/T1 GPIO3 Output Buffer Data GPIO2/T0 GPIO2 Output Buffer Data GPIO1/TXD GPIO1 Output Buffer Data GPIO0/RXD GPIO0 Output Buffer Data
Table GPIO Input Register GPIOA_IN (0x7F1A- RESET=0xXX) GPIO INPUT REGISTER NAME DESCRIPTION GPIO7 GPIO7 Input Buffer Data GPIO6 GPIO6 Input Buffer Data GPIO5 GPIO5 Input Buffer Data GPIO4/SOF GPIO4 Input Buffer Data GPIO3/T1 GPIO3 Input Buffer Data GPIO2/T0 GPIO2 Input Buffer Data GPIO1/TXD GPIO1 Input Buffer Data GPIO0/RXD GPIO0 Input Buffer Data
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Table Utility Configuration Register UTIL_CONFIG (0x7F1B- RESET=0x00) UTILITY CONFIGURATION REGISTER NAME DESCRIPTION [7:5] Reserved Reserved GPIO4/SOF GPIO4/SOF Output Select GPIO4 port GPIO3/T1 P3.5 Timer input trigger source GPIO3 FRAME write strobe GPIO2/T0 P3.4 Timer input trigger source GPIO2 FRAME write strobe GPIO1/TXD GPIO1/TXD Output Select GPIO1 P3.1 GPIO0/RXD P3.0 RXD/GPIO0 Input Select RXD<=GPIO0 RXD<='0' Note Counter mode, 8051 must sample T[1:0] instruction cycle, then next. 12MHz, Pulse must active least 1us. Note Missing packets reconstructed using Timer mode count number 8051 instruction cycles since last valid Frame received. Note GPIO used output nSOF pulses. This done configuring GPIO output writing GPIO register generate pulses each time packet received.
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GPIO data (0x7F19[7:3]) GPIO Direction (0x7F18[7:3]) GPIO data (0x7F1A[7:3]) GPIO[7:3]
GPIO2 data (0x7F19[2]) GPIO2 (0x7F18[2]) 8051 timer P3.4"
GPIO2 data (0x7F1A[2]) Internal 0X7F1B[2] GPIO3 data (0x7F19[3]) GPIO3 (0x7F18[3])
8051 timer P3.5"
GPIO3 data (0x7F1A[3]) Internal
0X7F1B[3]
GPIO0 data (0x7F19[0]) GPIO0 (0x7F18[0]) GPIO0 data (0x7F1A[0]) Uart P3.0"
0X7F1B[0]
GPIO1 data (0x7F19[1]) Uart P3.1" 0X7F1B[1]
GPIO1 (0x7F18[1])
GPIO1 data (0x7F1A[1])
GPIO4 data (0x7F19[4]) port 0X7F1B[4]
GPIO4 (0x7F18[4])
GPIO4 data (0x7F1A[4])
FIGURE GPIO MUXING BLOCK DIAGRAM
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POWER MANAGEMENT REGISTERS
Table MCU/ISADMA Clock Source Select CLOCK_SEL (0x7F27 RESET=0x40) MCU/ISADMA CLOCK SOURCE SELECT NAME DESCRIPTION SLEEP When PCON. SLEEP been ring oscillator will gated off, then oscillators will turned maximum power savings. (These signals used generate nFCE) ROSC_EN Ring Oscillator Disable. Ring Oscillator Enable. ROSC_EN must before switched internal Ring Oscillator Clock source. MCUCLK_SRC MCUCLK_SRC overrides MCUCLK_x clock select switches Ring Oscillator. Ring Oscillator. ROSC_EN must enabled first. clock specified MCU_CLK_[1:0] MCU_CLK[1:0] [4:3] 8MHz [4:3] 12MHz [4:3] 16MHz [4:3] 24MHz ISADMACLK_EXT Selects external clock source 8237 ISADMA controller synchronizing with another block. NOTE: This will initially external input, eventually used within block optimize performance, some other internal clock source. ISADMACLK[1.0] select EXT_IN clock source 8237 ISADMACLK[1:0] [1:0] Stopped [1:0] 2MHz [1:0] 4MHz [1:0] 8MHz
[4:3]
[1:0]
Note 8051 program itself internal Ring Oscillator having frequency range between 12MHz. This precise clock, meant provide 8051 with clock source, without running 24MHz crystal oscillator Note Switching between fast slow clocks recommended save power. Note Clock switching done long both clocks running. When switching, takes total clocks clocks original clock plus clocks switching clock) guarantee switching. Note Time required from ROSC_EN=1 MCUCLK_SRC=0.
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Table FLASH Bank Select Register MEM_BANK2 (0x7F28 RESET=0x00) NAME [7:6] Reserved [5:0] A[19:14] FLASH BANK SELECT REGISTER DESCRIPTION Reserved This register selects which page resides 0x8000-0xBFFF Code Space 0x8000-0xBFFF Data Space. Table FLASH Bank Select Register MEM_BANK (0x7F29 RESET=0x01) NAME [7:6] Reserved [5:0] A[19:14] FLASH BANK SELECT REGISTER DESCRIPTION Reserved This register selects which page resides 0x4000-0x7FFF Code Space 0xC000-0xFFFF Data Space. 0x00000x3FFF page will always reflect FLASH page (0x000000x03FFF). Table Wakeup Source Register WU_SRC_1 (0x7F2A RESET=0x00) NAME [7:3] Reserved USB_Reset WAKEUP SOURCE DESCRIPTION Reserved This when detects simultaneous logic lows (Single-Ended full speed times, speed times 2.5<t<5.5us). USB_Reset signal long 10ms. SETUP tokens NAK'd 10ms after Reset signal released. This detection Global Resume state (when there transition from state while Global Suspend). Suspend IDLE state detected hardware, then this will set.
Resume Suspend
Note Only high transitions associated inputs sets these bits. Note bits this register cleared writing corresponding bit. Note Unmasked Wakeup Source bits generate INT1 PWR_MNG interrupt, restart 8051 when clock stopped. This restarts Ring Oscillator crystal oscillator resume from <500µA operation. Note initiate Remote Wakeup, SIE_Resume should used SIE_CONFIG register.
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Table Wakeup Mask Register WU_MSK_1 (Note (0x7F2B RESET=0x07 WAKEUP MASK NAME DESCRIPTION [7:3] Reserved Reserved USB_Reset External wakeup event. Enabled Masked Resume External wakeup event. Enabled Masked Suspend Internal wakeup event. Enabled Masked Suspend IDLE state detected hardware, then this bit, when will cause interrupt Note Interrupt events enabled these bits routed PWR_MNG ISR_1 register. Table Wakeup Source Register WU_SRC_2 (0x7F2C RESET=0x00) WAKEUP SOURCE NAME DESCRIPTION [7:4] Reserved IRQ3 External Interrupt state since WU_SRC_2 last read. Unchanged Changed IRQ2 External Interrupt state since WU_SRC_2 last read. Unchanged Changed IRQ1 External Interrupt state since WU_SRC_2 last read. Unchanged Changed IRQ0 External Interrupt state since WU_SRC_2 last read. Unchanged Changed Note transition from high low, high associated input sets these bits. Note bits this register cleared writing corresponding bit. Note Since this register will report status change, when devices powered down while monitored, appropriate bits must masked until device armed correctly.
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Table Wakeup Mask Register WU_MSK_2 (0x7F2D RESET=0x0F) WAKEUP MASK NAME DESCRIPTION Reserved IRQ3 External wakeup event enable. Enabled Masked IRQ2 External wakeup event enable. Enabled Masked IRQ1 External wakeup event enable. Enabled Masked IRQ0 External wakeup event enable. Enabled Masked Note: Interrupt events enabled these bits routed PWR_MNG ISR_1 register. Interface Registers Table Request Register BUS_REQ (0x7F70 RESET=0x00) NAME INH_TC3 REQUEST REGISTER DESCRIPTION This inhibits channel TC.**See Note Below driven onto before. forced inactive. This inhibits channel TC.** Note Below driven onto before. forced inactive. This inhibits channel TC.** Note Below driven onto before. forced inactive. This inhibits channel TC.** Note Below driven onto before. forced inactive. Writing holds 8237 hardware reset input active. Writing releases normal operation. used clock switching power management functions. This reflects status 8237's pin. This does generate interrupt 8051 grant when ready HLDA. This should tri-state common signals between 8051 8237 bus. This reflects status 8237's HREQ request pin. This does generate interrupt.
INH_TC2
INH_TC1
INH_TC0
RESET_8237
HLDA
HREQ
Note:
HLDA Example: When 8051 running 24MHz, 8237 running 2MHz, 8237 take 1.5us complete transfer after deasserting HLDA When running 8051 24MHz, wait states must added when 8237 running MHz. When running 8051 12MHz, wait states must added when 8237 running MHz.
Note**: "Inhibit" function valid Memory-to-Memory cycles
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Table Status Register BUS_STAT (0x7F73 RESET=0xXX) STATUS REGISTER NAME DESCRIPTION CH3RQ Channel Request Request Pending Request Pending CH2RQ Channel Request Request Pending Request Pending CH1RQ Channel Request Request Pending Request Pending CH0RQ Channel Request Request Pending Request Pending CH3TC Channel Terminal Count Reached CH2TC Channel Terminal Count Reached CH1TC Channel Terminal Count Reached CH0TC Channel Terminal Count Reached Note Each this register reflects current value corresponding 8237 CH_STAT status register. Note 8237 clears bits CH_STAT status register when 8051 reads through Window. Note Reading BUS_STAT register does clear otherwise affect BUS_STAT register. Note ISADMA ISR_0 latched high whenever BUS_STAT that enabled BUS_MASK transitions from high. Note This register intended provide view into status 8237 without having assume control during transfers, provide means generating ISADMA interrupt ISR_0 which indicates that transfer completed that 8051 should take control setup 8237 next transfer. Bits used generate additional interrupt requests from DREQ pins, simply monitor channel request status masking them.
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Table Status Mask Register BUS_MASK (0x7F74 RESET=0xFF) STATUS MASK REGISTER NAME DESCRIPTION CH3RQ_MASK Channel Request ISADMA Interrupt Mask Enable Interrupt Mask Interrupt CH2RQ_MASK Channel Request ISADMA Interrupt Mask Enable Interrupt Mask Interrupt CH1RQ_MASK Channel Request ISADMA Interrupt Mask Enable Interrupt Mask Interrupt CH0RQ_MASK Channel Request ISADMA Interrupt Mask Enable Interrupt Mask Interrupt CH3TC_MASK Channel Terminal Count ISADMA Interrupt Mask Enable Interrupt Mask Interrupt CH2TC_MASK Channel Terminal Count ISADMA Interrupt Mask Enable Interrupt Mask Interrupt CH1TC_MASK Channel Terminal Count ISADMA Interrupt Mask Enable Interrupt Mask Interrupt CH0TC_MASK Channel Terminal Count ISADMA Interrupt Mask Enable Interrupt Mask Interrupt Table Window Base Register IOBASE (0x7F71 RESET=0x00) WINDOW BASE REGISTER NAME DESCRIPTION SA[15:8] When 8051 reads writes Window, this register combined with offset byte window presented Space address during 8051-ISA cycle Table Memory Window Base Register MEMBASE (0x7F72 RESET=0x00) MEMORY WINDOW BASE REGISTER NAME DESCRIPTION SA[19:12] When 8051 reads writes Memory Window, this register combined with offset byte window presented 1Mbyte Memory address during 8051-ISA MEMR MEMW cycle.
[7:0]
[7:0]
8237 (ISADMA) REGISTER DESCRIPTION Memory Table ISADMA Memory 8237 MEMORY ADDRESS DESCRIPTION 0xFC00-0xFFFF Window Packet with PNR=0x1F 0xF800-0xFBFF Window Packet with PNR=0x1E 0xF400-0xF7FF Window Packet with PNR=0x1D 0xF000-0xF3FF Window Packet with PNR=0x1C 0xEC00-0xEFFF Window Packet with PNR=0x1B 0xE800-0xEBFF Window Packet with PNR=0x1A 0xE400-0xE7FF Window Packet with PNR=0x19 0xE000-0xE3FF Window Packet with PNR=0x18 0xDC00-0xDFFF Window Packet with PNR=0x17
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8237 MEMORY ADDRESS 0xD800-0xDBFF 0xD400-0xD7FF 0xD000-0xD3FF 0xCC00-0xCFFF 0xC800-0xCBFF 0xC400-0xC7FF 0xC000-0xC3FF 0xBC00-0xBFFF 0xB800-0xBBFF 0xB400-0xB7FF 0xB000-0xB3FF 0xAC00-0xAFFF 0xA800-0xABFF 0xA400-0xA7FF 0xA000-0xA3FF 0x9C00-0x9FFF 0x9800-0x9BFF 0x9400-0x97FF 0x9000-0x93FF 0x8C00-0x8FFF 0x8800-0x8BFF 0x8400-0x87FF 0x8000-0x83FF 0x0000-0x7FFF
DESCRIPTION Window Packet with PNR=0x16 Window Packet with PNR=0x15 Window Packet with PNR=0x14 Window Packet with PNR=0x13 Window Packet with PNR=0x12 Window Packet with PNR=0x11 Window Packet with PNR=0x10 Window Packet with PNR=0x0F Window Packet with PNR=0x0E Window Packet with PNR=0x0D Window Packet with PNR=0x0C Window Packet with PNR=0x0B Window Packet with PNR=0x0A Window Packet with PNR=0x09 Window Packet with PNR=0x08 Window Packet with PNR=0x07 Window Packet with PNR=0x06 Window Packet with PNR=0x05 Window Packet with PNR=0x04 Window Packet with PNR=0x03 Window Packet with PNR=0x02 Window Packet with PNR=0x01 Window Packet with PNR=0x00 Window External
actual packet composed different byte non-contiguous packets, re-maps internal addresses automatically such that 8237 8051 only need reference packet number offset within packet. example, suppose (0x138) byte packet received SIEDMA from host. patented allocates bytes packet (including byte status header) returns 0x0A. SIEDMA engine will place 0x0A receive packet queue notify 8051. 8051 will take that PNR, examine packet through PNR/Pointer registers, determine offset payload data wants transfer from packet, 0x027. address must calculate 8237 base address register would therefore 0xA827 (0xA800+0x027). Each channel programmed with different same) Packet Number offset data will appear ordinary contiguous (see table more information). Software written this model will work virtually Endpoint number Buffer size combination.
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Runtime Registers controller block registers which normally occupy locations 0x00-0x0F bus. When they located 0x0000-0x000F bus, 8051 access them programming IOBASE Register 0x00, reading writing from 0x4000-0x400F. Table 8237 Registers Space Channel Current Address Channel Byte Count Channel Current Address Channel Byte Count Channel Current Address Channel Byte Count Channel Current Address Channel Byte Count Status/Command Register Write Request Register Write Single Mask Register Write Mode Register Clear Byte Read Temp Register Master Clear Clear Mask Write Mask Bits
0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C 0x000D 0x000E 0x000F
Note: write these registers, HLDA must logic low. Table 8237 Address Programming Guide 8237 INTERNAL ADDRESS PROGRAMMING GUIDE NAME DESCRIPTION INT_EXT Indicates whether this address refers Internal Buffer External Memory Space External Internal When this zero (0), capability added External Memory DMA. This capability only used channels PN[4:0]/SA[14:10] External Address -or- Internal Packet Number SA[14.10] when INT_EXT=0 PN[4.0] when INT_EXT=1 PTR[9:0]/SA[9:0] External Address -or- Internal Packet Offset Pointer SA[9.0] when INT_EXT=0 PTR[9.0] when INT_EXT=1
[14:10]
[9:0]
Note: SA[19.15] driven when 8237 accessing external memory. PTR10 driven when 8237 accessing internal buffer RAM. Note that actual transfer size ISADMA limited 1024 bytes, which limits payload data 1016 bytes transfer when byte header skipped. Also note that 8051 still access 1Meg external through MEMBASE register independent 8237's external limit. Table Channel Current Address Register CH0_ADDR (ISA 0x0000) NAME CH0_ADDRL CH0_ADDRH CHANNEL CURRENT ADDRESS DESCRIPTION Lower bits Base Current Address when Byte Upper bits Base Current Address when Byte
[7:0] [7:0]
Note: Byte internal Flip Flop which reflects which byte (high low) being written. CLEAR_FF register should written before writing this register guarantee which byte (high low) being written. Address Programming Table Address definitions.
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Table Channel Byte Count Register CH0_CNT (ISA 0x0001) NAME CH0_CNTL CH0_CNTH CHANNEL BYTE COUNT DESCRIPTION Lower bits Byte Count when Byte Upper bits Byte Count when Byte
[7:0] [7:0]
Note: CLEAR_FF register should written before writing this register guarantee which byte (high low) being written. Address Programming Table Address definitions. Table Channel Current Address Register CH1_ADDR (ISA 0x0002) NAME CH1_ADDRL CH1_ADDRH CHANNEL CURRENT ADDRESS DESCRIPTION Lower bits Base Current Address when Byte Upper bits Base Current Address when Byte
[7:0] [7:0]
Note: CLEAR_FF register should written before writing this register guarantee which byte (high low) being written. Address Programming Table Address definitions. Table Channel Byte Count Register CH1_CNT (ISA 0x0003) NAME CH1_CNTL CH1_CNTH CHANNEL BYTE COUNT DESCRIPTION Lower bits Byte Count when Byte Upper bits Byte Count when Byte
[7:0] [7:0]
Note: CLEAR_FF register should written before writing this register guarantee which byte (high low) being written. Address Programming Table Address definitions. Table Channel Current Address Register CH2_ADDR (ISA 0x0004) NAME CH2_ADDRL CH2_ADDRH CHANNEL CURRENT ADDRESS DESCRIPTION Lower bits Base Current Address when Byte Upper bits Base Current Address when Byte
[7:0] [7:0]
Note: CLEAR_FF register should written before writing this register guarantee which byte (high low) being written. Address Programming Table Address definitions. Table Channel Byte Count Register CH2_CNT (ISA 0x0005) CHANNEL BYTE COUNT NAME DESCRIPTION CH2_CNTL Lower bits Byte Count when Byte CH2_CNTH Upper bits Byte Count when Byte
[7:0] [7:0]
Note: CLEAR_FF register should written before writing this register guarantee which byte (high low) being written. Address Programming Table Address definitions. Table Channel Current Address Register CH3_ADDR (ISA 0x0006) NAME CH3_ADDRL CH3_ADDRH CHANNEL CURRENT ADDRESS DESCRIPTION Lower bits Base Current Address when Byte Upper bits Base Current Address when Byte
[7:0] [7:0]
Note: CLEAR_FF register should written before writing this register guarantee which byte (high low) being written. Address Programming Table Address definitions.
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Table Channel Byte Count Register CH3_CNT (ISA 0x0007) NAME CH3_CNTL CH3_CNTH CHANNEL BYTE COUNT DESCRIPTION Lower bits Byte Count when Byte Upper bits Byte Count when Byte
[7:0] [7:0]
Note: CLEAR_FF register should written before writing this register guarantee which byte (high low) being written. Address Programming Table Address definitions. Table Channel Status Register CH_STAT (ISA 0x0008) CHANNEL STATUS REGISTER NAME DESCRIPTION CH3RQ Channel Request Request Pending Request Pending CH2RQ Channel Request Request Pending Request Pending CH1RQ Channel Request Request Pending Request Pending CH0RQ Channel Request Request Pending Request Pending CH3TC Channel Terminal Count Reached CH2TC Channel Terminal Count Reached CH1TC Channel Terminal Count Reached CH0TC Channel Terminal Count Reached
Note These bits also visible outside space BUS_STAT register. Note These bits cleared when this register read through Window. Table 8237 Command Register CH_CMD (ISA 0x0008) NAME DACK_SENS COMMAND REGISTER DESCRIPTION DACK Sense Active High Active DREQ Sense Active Low, Active High) Write Timing Select Late Timing Extended Priority Fixed Rotating Timing Normal Compressed Controller Enable Enable Disable
DREQ_SENS WRITE_TIME
PRIORITY
COMP_TIME
CTRL_EN
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CH_CMD (ISA 0x0008) NAME ADDR_HOLD
MEM2MEM
COMMAND REGISTER DESCRIPTION Channel Address Hold Disable Hold Enable Memory-to-Memory Disable Enable
[7:3]
[1:0]
Table 8237 Write Single Request Register CH_REQ (ISA 0x0009) WRITE REQUEST REGISTER NAME DESCRIPTION Reserved Reserved SET_CLR Force Internal Request Clear SEL[1:0] '00' Select Channel DREQ '01' Select Channel DREQ '10' Select Channel DREQ '11' Select Channel DREQ Table 8237 Write Single Mask Register CH_MASK (ISA 0x000A) WRITE SINGLE MASK REGISTER NAME DESCRIPTION Reserved Reserved SET_CLR Channel Mask Clear SEL[1:0] '00' Select Channel Mask '01' Select Channel Mask '10' Select Channel Mask '11' Select Channel Mask Table Write Mode Register DMA_MODE (ISA 0x000B) NAME MODE[1:0] WRITE MODE REGISTER DESCRIPTION '00' Demand Mode Select '01' Single Mode Select '10' Block Mode Select '11' Cascade Mode Select Auto-increment/Decrement Increment Decrement Auto-initialization Disable Enable '00' Verify Transfer '01' Write Transfer '10' Read Transfer '11' Illegal 'XX' bits '11' CH_CMD register (memory-to-memory transfer) '00' Select Channel '01' Select Channel '10' Select Channel '11' Select Channel
[7:3]
[1:0]
[7:6]
INC_DEC
AUTO_INIT
[3:2]
R/WV[1:0]
[1:0]
SEL[1:0]
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[7:0]
Table Clear Byte Pointer Flip Flop Register CLEAR_FF (ISA 0x000C) CLEAR BYTE POINTER FLIP FLOP NAME DESCRIPTION BPFF This register must written clear high/low byte pointer flip flop prior reading writing address word count information 8237. Table Read Temporary Register RD_TEMP (ISA 0x000D) NAME TEMP_BYTE READ TEMPORARY REGISTER DESCRIPTION This location holds value last byte transferred memory-to-memory operation.
[7:0]
Table Master Clear Register MSTR_CLR: (ISA 0x000D) MASTER CLEAR REGISTER NAME DESCRIPTION [7:0] SW_RESET Writing this register same effect registers hardware reset. 8237 will enter idle state. Table Clear Mask Register CLR_MASK: (ISA 0x000E) CLEAR MASK REGISTER NAME DESCRIPTION [7:0] CLR_ALL Writing this register clears mask bits four channels allows them receive requests. Table Clear Mask Bits Register ALL_MASK (ISA 0x000F) NAME Reserved CH3_MASK CH2_MASK CH1_MASK CH0_MASK WRITE MASK BITS REGISTER DESCRIPTION Reserved Channel Mask Mask, Clear Mask) Channel Mask Mask, Clear Mask) Channel Mask Mask, Clear Mask) Channel Mask Mask, Clear Mask)
[7:4]
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SCATTER-GATHER (SGDMA) REGISTER DESCRIPTION SGDMA four channels with each channel having registers (FIGURE Each register starts different starting BASE address: Channels 1,2, have starting BASE addresses 7FB0, 7FBA, 7FC4, 7FCE, respectively. tables following pages describe each register register set, using denote channel ranges from address each register denoted BASE+n, where offset from BASE.
BASE Address
7FB0
Effective Address
7FB0 7FB1 7FB2 7FB3
SGDMA Channel Registers
OFFSET SGDMA_START_FIFO0 OFFSET SGDMA_DONE_FIFO0 OFFSET SGDMA_ADHI0 OFFSET SGDMA_ADLO0
OFFSET SGDMA_CMD0
7FBA
SGDMA Channel Registers
OFFSET SGDMA_START_FIFO1 OFFSET SGDMA_DONE_FIFO1 OFFSET SGDMA_ADHI1 OFFSET SGDMA_ADLO1
7FB9 7FBA 7FBB 7FBC 7FBD
7FC4
SGDMA Channel Registers
OFFSET SGDMA_CMD1 OFFSET SGDMA_START_FIFO2 OFFSET SGDMA_DONE_FIFO2 OFFSET SGDMA_ADHI2 OFFSET SGDMA_ADLO2
7FC3 7FC4 7FC5 7FC6 7FC7
7FCE
SGDMA Channel Registers
OFFSET SGDMA_CMD2 OFFSET SGDMA_START_FIFO3 OFFSET SGDMA_DONE_FIFO3 OFFSET SGDMA_ADHI3 OFFSET SGDMA_ADLO3
7FCD 7FCE 7FCF 7FD0 7FD1
OFFSET SGDMA_CMD3
7FD7
FIGURE SGDMA REGISTER SPACE
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SGDMA also contains engine that permits access cycle stealing basis with transfers (there only engine). Table SGDMA Packet Number Start FIFO Register SGDMA_START_FIFOx [x=0.3] (BASE+0 RESET 0x00) SGDMA_START_FIFO NAME DESCRIPTION [7:5] Reserved Reserved Read back [4:0] PCKTNUM Packet Number queue SGDMA_START_FIFOx [x=0.3]. Note This register used when channel configured memory operation. Note When channel enabled (CHANNEL_ENABLE=1 register SGDMA_CMDx [x=0.3]), only SGDMA read from these registers. only read from these registers when channel disabled (CHANNEL_ENABLE=0 register SGDMA_CMDx [x=0.3]), busy (DMA_BUSY=0 register SGDMA_STSx [x=0.3]). MCU's responsibility ensure that this FIFO does overflow. Table SGDMA Packet Number Done FIFO Register SGDMA_DONE_FIFOx [x=0.3] (BASE+1 RESET 0x00) SGDMA_DONE_FIFO NAME DESCRIPTION [7:5] Reserved Reserved Read back [4:0] PCKTNO Packet Number SGDMA_DONE_FIFOx [x=0.3]. Note This register used when channel configured memory operation. Note SGDMA puts packet number this FIFO when transfer complete, when disables channel that enabled busy (meaning transfer progress). When this register read, FIFO popped. MCU's responsibility ensure that this FIFO does overflow. Table SGDMA Address High Byte Register SGDMA_ADHIx [x=0.3] (BASE+2 RESET 0x00) SGDMA_ADHI NAME DESCRIPTION [7:0] ADHIx [x=0.3] Contains high byte Address use. Table SGDMA Address Byte Register SGDMA_ADLOx [x=0.3] (BASE+3 RESET 0x00) SGDMA_ADLO NAME DESCRIPTION [7:0] ADLOx [x=0.3] Contains byte Address use. Note SGDMA_ADHIx [x=0.3] SGDMA_ADLOx [x=0.3] registers used when channel [0.3] configured memory operation. Note must write these registers unless channel disabled (CHANNEL_ENABLED=0 register SGDMA_CMDx [x=0.3]) busy (DMA_BUSY=0 register SGDMA_STSx [x=0.3]). Table SGDMA Transfer Size High Register SGDMA_SIZEHIx [x=0.3] (BASE+4 RESET 0x00) SGDMA_SIZEHI NAME DESCRIPTION [7:0] SIZEHIx Contains high byte payload [x=0.3] data size bytes)
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Table SGDMA Transfer Size Register SGDMA_SIZELOx [x=0.3] (BASE+5 RESET 0x00) SGDMA_SIZELO NAME DESCRIPTION [7:0] SIZEHIx Contains byte payload [x=0.3] data size bytes). Note SGDMA_SIZEHIx [x=0.3] SGDMA_SIZELOx [x=0.3] registers used when channel [0.3] configured memory operation operation without Packet Header. Note must write these registers unless channel disabled (CHANNEL_ENABLED register SGDMA_CMDx [x=0.3]) busy ((DMA_BUSY=0 register SGDMA_STSx [x=0.3]). Table SGDMA Total Packets Channel Register SGDMA_TOTAL_PKTSx [x=0.3] (BASE+6 RESET 0x00) SGDMA_TOTAL_PKTS NAME DESCRIPTION [7:5] Reserved Reserved Read back [4:0] NUMPCKTS Number packets currently channel [0.3] Note This register contains count total number packets corresponding SGDMA channel [0.3]. incremented when puts packet number into SGDMA_START_FIFOx [x=0.3] decremented when pops packet from SGDMA_DONE_FIFOx [x=0.3]. Table SGDMA Total Packets Done FIFO Register SGDMA_DONE_PCKTSx [x=0.3] (BASE+7 RESET 0x00) SGDMA_DONE_PCKTS NAME DESCRIPTION [7:5] Reserved Reserved Read back [4:0] NUMPCKTS Number packets SGDMA_DONE_FIFOx [x=0.3] Note This register contains count total number packets SGDMA_DONE_FIFOx [x=0.3]. incremented when SGDMA puts packet number into SGDMA_DONE_FIFOx [x=0.3] decremented when pops packet from SGDMA_DONE_FIFOx [x=0.3]. Table SGDMA Status Register SGDMA_STSx [x=0.3] (BASE+8 RESET 0x00) SGDMA_STS NAME DESCRIPTION DMA_BUSY Will while SGDMA transfer progress ISA_DONE Will after memory device transfer completed. Resets when channel disabled (CHANNEL_ENABLE=0 register SGDMA_CMDx [x=0.3]) M2M_INCOMPLETE (Channel only) Set(1) only when following true: Memory-to-Memory transfer memory target SGDMA_START_FIFO1 empty SGDMA_SIZEHI0 SGDMA_SIZELO0 SGDMA Channel enabled SGDMA Channel enabled Clear(0) when they true Reserved Reserved Read back (for Channels Reserved Reserved Read back DONE_FIFO_FULLx Set(1) when SGDMA_DONE_FIFOx [x=0.3] full [x=0.3] Clear(0) when SGDMA_DONE_FIFOx [x=0.3] full DONE_FIFO_EMPTYx Set(1) when SGDMA_DONE_FIFOx[x=0.3] empty [x=0.3] Clear(0) when SGDMA_DONE_FIFOx[x=0.3] empty
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SGDMA_STSx [x=0.3] (BASE+8 RESET 0x00) NAME START_FIFO_FULLx [x=0.3] START_FIFO_EMPTY [x=0.3]
SGDMA_STS DESCRIPTION Set(1) when SGDMA_START_FIFOx [x=0.3] full Clear(0) when SGDMA_START_FIFOx [x=0.3] full Set(1) when SGDMA_START_FIFOx [x=0.3] empty Clear(0) when SGDMA_START_FIFOx [x=0.3] empty
Table SGDMA Command Register SGDMA_CMDx [x=0.3] (BASE+9 RESET 0x00) SGDMA_CMD NAME DESCRIPTION [7:3] Reserved Reserved Read back PCKT_HD Set(1) indicate that packet header present. Clear(0) indicate that there packet header. Applies only MEM_OP set(1). MEM_OP Set(1) indicate memory operation. Clear(0) indicate memory operation. When clear(0), packet size comes from SGDMA_SIZEHIx/LOx [x=0.3] registers, whose value decremented before being written into 8237 count register. memory address comes from SGDMA_ADHIx/LOx [x=0.3] registers. When set(1), PCKT_HDR=0, packet size comes from SGDMA_SIZEHIx/LOx [x=0.3] registers, whose value decremented before being written into 8237 count register. High byte address based packet number, byte address When set(1), PCKT_HDR=1, high byte address based packet number byte address MemRd transfer, packet size read from packet header this value represents number bytes payload data plus header, this value minus written into 8237 counter register. packet size header (indicating zero-byte payload), transfer will occur SGDMA will packet number into SGDMA_DONE_FIFOx [x=0.3]. MemWr transfer, SGDMA_SIZEHIx/LOx [x=0.3] registers contain number bytes payload data, this value decremented before being written into 8237 count register, this value plus written into packet memory offset Set(1) enabled channel. Clear(0) disable channel. this cleared during SGDMA cycle (before TC), then: MEM_OP=1, packet number into SGDMA_DONE_FIFOx [x=0.3] SGDMA returns idle, ready another cycle. MEM_OP=0, SGDMA returns idle ready another cycle. memory-to-memory transfer, packet number channel into SGDMA_DONE_FIFO0x none updates address size register occur, SGDMA returns idle ready another cycle.
CHANNEL _ENABLE
Note PKT_HDR MEM_OP bits must changed unless channel disabled (CHANNEL_ENABLRE=0 register SGDMA_CMDx [x=0.3]) busy (DMA_BUSY=0 register SGDMA_STSx [x=0.3]).
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Note Memory-to-memory transfer special case handled follows. memory-to-memory transfer supports transfers only between memory memory, either direction. source must Channel destination must Channel memory memory transfers Initially, performs following: Clears SGDMA_SIZEHI0/LO0 registers. Sets SGDMA_ADHI1/LO1 registers Address.
After each SGDMA will size completed transfer SGDMA_ADHI1/LO1 registers. PKT_HDR=1 SGDMA_CMD0 register, transfer size comes from packet header. PKT_HDR=0 SGDMA_CMD0 register, transfer size value SGDMA_SIZEHI1/LO1 registers. memory memory transfers Initially, performs following: Sets SGDMA_ADHI0/LO0 Address. Sets SGDMA_SIZEHI0/LO0 buffer size. Sets SGDMA_SIZEHI1/LO1 session transfer size.
After each SGDMA will session transfer size SGDMA_ADHI0/LO0 registers subtract session transfer size from SGDMA_SIZEHI0/LO0 registers. actual transfer size lesser values SGDMA_SIZEHI1/ SGDMA_SIZEHI0/LO0 registers. PKT_HDR=1 register SGDMA_CMD1, then actual transfer size plus will written packet memory offset When SGDMA_SIZEHI0/LO0 registers reach value buffer been completely transferred. SGDMA_START_FIFO1 empty when buffer been completely transferred, M2M_INCOMPLETE SGDMA_STS0 register will set. During memory-to-memory transfer, either Channel Channel Disabled during SGDMA cycle, then packet number channel into SGDMA_DONE_FIFOxx However, none updates address size registers occur, SGDMA returns idle ready another cycle. memory-to-memory transfers, SGDMA_ADHI0, SGDMA_ADLO0, SGDMA_ADHI1, SGDMA_ADLO1, SGDMA_SIZEHI0, SGDMA_SIZELO0 must read until both channels Busy (DMA_BUSY=0 SGDMA_STS0 SGDMA_STS1). REGISTER DESCRIPTION Table Upper Byte Address PIO_ADHI (0x7FD8 RESET 0x00) PIO_ADHI NAME DESCRIPTION [7:4] Reserved Reserved Read back [3:0] PIOADDRHI upper bits address Table -Middle Byte Address PIO_ADMID (0x7FD9 RESET 0x00) PIO_ADMID NAME DESCRIPTION [7:0] PIOADDRMID middle byte address
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Table -Low Byte Address PIO_ADLO (0x7FDA RESET 0x00) PIO_ADLO NAME DESCRIPTION [7:0] PIOADDRLO byte address Note must write these registers until PIO_BUSY=0 PIO_CSR register. Note Read transfers first transfer Read Multiple transfers initiated writing PIO_ADLO register. Table Data Register PIO_DATA (0x7FDB RESET 0x00) PIO_DATA NAME DESCRIPTION [7:0] PIODATA Data transfer Note must read this register until PIO_BUSY=0 PIO_CSR register. Note Write transfers initiated writing PIO_DATA register. Read Multiple transfers (except first transfer) initiated reading PIO_DATA register Table Command/Status Register PIO_CSR (0x7FDC RESET 0x00) PIO_CSR NAME DESCRIPTION PIO_BUSY Will set(1) when transfer progress Reserved Reserved Read back [5:3] STROBEWIDTH Programs width RD/WR strobes (nIOR, nIOW, nMEMR, nMEMW) Strobe Width Invalid Invalid Invalid DMACLKs DMACLKs DMACLKs DMACLKs Invalid Read accesses, data must valid DMACLK cycle before trailing edge read strobe. MEMORY Set(1) indicate memory transfer. Clear(0)to indicate transfer. [1:0] TRANSFERTYPE Transfer Type Disable Write Read Read Multiple Note STROBEWIDTH MEMORY bits PIO_CSR register must changed unless TRANSFERTYPE=00 (disabled) PIO_BUSY=0 PIO_CSR register. Note Ready input used stretch width RD/WR strobes generated PIO. When READY input high, strobes will programmed PIO_CSR register. Writes: order affect nIOW nMEMW strobes, READY signal must least DMACLK periods before scheduled rising edge strobe, then strobe will remain until DMACLK periods after READY goes high. Reads: order affect nIOR nMEMW strobes, READY signal must least DMACLK periods before scheduled rising edge strobe, then strobe will remain DMACLK periods after READY goes high. read Data must valid within DMACLKS after READY goes high that Data available least DMACLK period before rising edge read strobe.
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MEMORY MANAGEMENT UNIT (MMU) REGISTER DESCRIPTION Interface Registers Table Data Window Register MMU_DATA (0x6000) NAME [D7:D0] DATA WINDOW REGISTER DESCRIPTION Data Packet Window. When register '1', this byte pointed packet number RXFIFO, packet offset PRH:PRL. When register '0', this byte pointed packet number register, packet offset PRH:PRL.
[7:0]
Notes: Read FIFO take most 1.218µs after written present valid data. Write FIFO take most 2.520µs after writing last byte data FIFO finish writing that data buffer. worst case sequential access times FIFOs while 8237 simultaneously arbitrating MMU, packet currently being transferred, 588ns. (READ) Therefore, after changing register, 8051 should wait least instruction cycles 12MHz) before reading from this register. After waiting, 8051, auto-increment mode (PRH 6=1), read byte every cycle 16MHz). (WRITE) data register mode switched write time, data written immediately every instruction cycle. After writing data, 8051 should wait least instruction cycles 12MHz) before changing :PRL registers Read Again, after waiting 1.218µs, 8051 read byte every instruction cycle.
Each endpoint will have three up/dn counter which will maintain number packets queued transmit that endpoint. These counters readable through these registers (there sixteen from 7F40 7F4F). Table FIFO Counter TX_FIFOx (0x7F40-0x7F4F) NAME Reserved TxFIFO Count FIFO Counter DESCRIPTION Reserved This field will contain number packets that queued transmit each endpoint. incremented when there push FIFO corresponding endpoint, decremented when there FIFO corresponding endpoints. Table Pointer Register (Low) (0x7F50) NAME A[7:0] POINTER REGISTER (LOW) DESCRIPTION (0-1277 Max) offset allocated Packet Pointed PNR. byte(s) pointed this register read written 0x6000.
[7:3] [2:0]
[7:0]
Note This register must written before Note value read from this register necessarily what last written actually last address used access buffer RAM.
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Table Pointer Register (High) (0x7F51) NAME POINTER REGISTER (HIGH) DESCRIPTION packet 0x6000 packet pointed register. packet available 0x6000 packet pointed packet Packet Number FIFO. Auto-increment disabled Causes PRH:PRL register automatically incremented each time 0x6000 data window accessed. Data register direction. This required MMU/Arbiter provide transparent interface buffer MCU. When first set, immediately fills read FIFO. must wait 2.5us Arbiter clocks) after writing MMU_DATA register before changing this from '1'. WRITE READ Reserved (0-1277 Max) offset allocated Packet Pointed PNR. byte(s) pointed this register read written 0x6000.
AUTO_INCR
READ
[4:3] [2:0]
Reserved A[10:8]
Note: This register must written after value take effect.
Table Transmit FIFO Select Register MMUTX_SEL (0x7F52) NAME Reserved EP[3:0] TRANSMIT FIFO SELECT REGISTER DESCRIPTION Reserved This register selects which Endpoint Commands "110" "111" will affect when issued
[7:4] [3:0]
Note: This register must written before writing "Enqueue Packet into Endpoint "Reset Endpoint command MMUCR. Table Command Register MMUCR (0x7F53) NAME MMU_CMD Reserved N[3:0] COMMAND REGISTER DESCRIPTION MMUCR COMMAND Reserved, writes ignored read return Number byte Pages. N[3.0]=0000 indicates page, N[3.0]=1001 indicates pages, 1280 bytes.
[7:5] [3:0]
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COMMAND Bits Description: NOOP, operation Allocate Memory N3-0 specify many byte pages allocate that packet pages allowed (1280 bytes) packet.) Immediately generates "FAILED" code code cleared when complete. generate ALLOC interrupt upon completion. When allocation request cannot completed insufficient memory, FAILED will remain set. subsequent release memory pages either MMUCR SIEDMA) will cause MMUCR automatically continue allocate command until requested pages have been successfully allocated. Software should never issue another allocate command until previous allocate command been successfully completed. RESET Frees buffer RAM, clears interrupts, resets queue pointers. Remove Packet from Queue issued after completed processing packet number RXFIFO. Remove Release RXFIFO Same (011), also frees memory used packet. This command especially useful quick "ignore" packets. Release specific Packet Frees pages allocated packet specified PNR. Enqueue Packet into Endpoint Places Packet number indicated register transmit queue endpoint pointed MMUTX_SEL register. MMUTX_SEL register must written before this command issued. Reset Endpoint Resets FIFO holding packet numbers awaiting transmission TXFIFO_STAT bits endpoint pointed MMUTX_SEL register. MMUTX_SEL register must written before this command issued. This command does release memory allocated packets that dequeued. Table Allocation Result Register (0x7F54) NAME FAILED Reserved P[4:0] ALLOCATION RESULT REGISTER DESCRIPTION Reserved Returns Packet Number (0-31, 0x00-0x1F) from allocation command. This written directly into register
[6:5] [4:0]
[7:5 [4:0]
(0x7F55) NAME Reserved P[4:0]
Table Packet Number Register PACKET NUMBER REGISTER DESCRIPTION Reserved Packet selector access packet 0x6000 buffer window
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Free Pages Register Free Pages bits, global NAK_ALLRX (this only NACK Bulk packets) control firmware view real time status page allocation bits. This allows NAK_ALLRX which would inhibit from asking SIEDMA allocate packets, checks many pages left, issue allocate enough free, then release SIE/SIEDMA. current design, number free pages would range from 0x00 0x1F (32) pages left unallocated. indication pages free invalid during allocation deallocation. Table PAGES FREE PAGS_FREE (0x7F56 RESET=0x20) NAME NAK_ALLRX PAGES FREE DESCRIPTION NACK received packets Normal Operation (Default) NACK packets Reserved These bits indicate number free pages MMU.
[5:0]
Reserved PAGS_FREE
Note Firmware NAK_ALLRX inhibit from asking SIEDMA allocate pages while observing page free bits. Note This register used indicate many pages left many situations, including after RX_OVRN, before multi-packet allocation, etc. This eliminates possibility failed allocation, simplifying software without adding additional hardware abort allocation. BYTE DEEP COMPLETION FIFO REGISTER Table Management Register TX_MGMT (0x7F57 RESET=0x80) Management Register NAME DESCRIPTION CTX_EMTY Completed FIFO empty status more packet Empty CTX_FULL Completed FIFO full status FULL FULL Reserved Reserved [4:0] CTX_FIFO This data port deep completion FIFO. This FIFO automatically updated hardware with last successfully completed transmit packet. responsibility software ensure that this FIFO never overflows and/or becomes full.
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[4:0]
Table Receive Packet Number FIFO Register RXFIFO (0x7F58) NEXT PACKET NUMBER FIFO REGISTER NAME DESCRIPTION RXFIFO_EMPTY pending packets from host processed RXFIFO_FULL SIEDMA will accept packets from host (via Overflow) Reserved Reserved P[4:0] Packet Number When packet been received, 8-byte header been written SIEDMA, associated Packet Number placed this FIFO.
"complete" reception requires that byte status header correctly written into packet buffer, with correct data, moved into Packet Number FIFO. "successful" reception requires that check bits "complete" reception good. hardware queues only "complete" packets. Firmware must determine "complete" packets were "successful". Corrupted token packets causes complete data payload ignored.
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FIFO Register This register used help software manage Queues. This will provide method handle CLEAR_FEATURE:ENDPOINT_STALL condition gracefully. When read, this register will return Packet Number next packet waiting queue pointed MMUTX_SEL register, will that Packet Number selected FIFO. Table FIFO POP_TX (0x7F59 RESET=0x80) NAME POPTX_STAT FIFO DESCRIPTION FIFO empty status more packet Empty Reserved This value packet number handle that FIFO pointer MMUTX_SEL. FIFO popped when this register read.
[6:5] [4:0]
Reserved POP_TX
Note: software's responsibility ensure that appropriate disabled during this operation, issue de-allocate command desired. Table Transmit FIFO Status Register TXSTAT_A (0x7F60 RESET=0x55) TRANSMIT FIFO STATUS REGISTER NAME DESCRIPTION EP3TX_EMPTY Endpoint Transmit Packet FIFO Status Bits [7:6]='11' Invalid Bits [7:6]='10' Empty Packets queued) Bits [7:6]='01' Full Packets queued) Bits [7:6]='00' Partially Full Packets queued) EP3TX_FULL EP2TX_EMPTY Endpoint Transmit Packet FIFO Status Bits [5:4]='11' Invalid Bits [5:4]='10' Empty Packets queued) Bits [5:4]='01' Full Packets queued) Bits [5:4]='00' Partially Full Packets queued) EP2TX_FULL EP1TX_EMPTY Endpoint Transmit Packet FIFO Status Bits [3:2]='11' Invalid Bits [3:2]='10' Empty Packets queued) Bits [3:2]='01' Full Packets queued) Bits [3:2]='00' Partially Full Packets queued) EP1TX_FULL EP0TX_EMPTY Endpoint Transmit Packet FIFO Status Bits [1:0]='11' Invalid Bits [1:0]='10' Empty Packets queued) Bits [1:0]='01' Full Packets queued) Bits [1:0]='00' Partially Full Packets queued) EP0TX_FULL
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Table Transmit FIFO Status Register STAT_B (0x7F61 RESET=0x55) TRANSMIT FIFO STATUS REGISTER NAME DESCRIPTION EP7TX_EMPTY Endpoint Transmit Packet FIFO Status Bits [7:6]='11' Invalid Bits [7:6]='10' Empty Packets queued) Bits [7:6]='01' Full Packets queued) Bits [7:6]='00' Partially Full Packets queued) EP7TX_FULL EP6TX_EMPTY Endpoint Transmit Packet FIFO Status Bits [5:4]='11' Invalid Bits [5:4]='10' Empty Packets queued) Bits [5:4]='01' Full Packets queued) Bits [5:4]='00' Partially Full Packets queued) EP6TX_FULL EP5TX_EMPTY Endpoint Transmit Packet FIFO Status Bits [3:2]='11' Invalid Bits [3:2]='10' Empty Packets queued) Bits [3:2]='01' Full Packets queued) Bits [3:2]='00' Partially Full Packets queued) EP5TX_FULL EP4TX_EMPTY Endpoint Transmit Packet FIFO Status Bits [1:0]='11' Invalid Bits [1:0]='10' Empty Packets queued) Bits [1:0]='01' Full Packets queued) Bits [1:0]='00' Partially Full Packets queued) EP4TX_FULL
Table Transmit FIFO Status Register TXSTAT_C (0x7F62 RESET=0x55) TRANSMIT FIFO STATUS REGISTER NAME DESCRIPTION EP11TX_EMPTY Endpoint Transmit Packet FIFO Status Bits [7:6]='11' Invalid Bits [7:6]='10' Empty Packets queued) Bits [7:6]='01' Full Packets queued) Bits [7:6]='00' Partially Full Packets queued) EP11TX_FULL EP10TX_EMPTY Endpoint Transmit Packet FIFO Status Bits [5:4]='11' Invalid Bits [5:4]='10' Empty Packets queued) Bits [5:4]='01' Full Packets queued) Bits [5:4]='00' Partially Full Packets queued) EP10TX_FULL EP9TX_EMPTY Endpoint Transmit Packet FIFO Status Bits [3:2]='11' Invalid Bits [3:2]='10' Empty Packets queued) Bits [3:2]='01' Full Packets queued) Bits [3:2]='00' Partially Full Packets queued) EP9TX_FULL EP8TX_EMPTY Endpoint Transmit Packet FIFO Status Bits [1:0]='11' Invalid Bits [1:0]='10' Empty Packets queued) Bits [1:0]='01' Full Packets queued) Bits [1:0]='00' Partially Full Packets queued) EP8TX_FULL
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Table Transmit FIFO Status Register TXSTAT_D (0x7F63 RESET=0x55) TRANSMIT FIFO STATUS REGISTER NAME DESCRIPTION EP15TX_EMPTY Endpoint Transmit Packet FIFO Status Bits [7:6]='11' Invalid Bits [7:6]='10' Empty Packets queued) Bits [7:6]='01' Full Packets queued) Bits [7:6]='00' Partially Full Packets queued) EP15TX_FULL EP14TX_EMPTY Endpoint Transmit Packet FIFO Status Bits [5:4]='11' Invalid Bits [5:4]='10' Empty Packets queued) Bits [5:4]='01' Full Packets queued) Bits [5:4]='00' Partially Full Packets queued) EP14TX_FULL EP13TX_EMPTY Endpoint Transmit Packet FIFO Status Bits [3:2]='11' Invalid Bits [3:2]='10' Empty Packets queued) Bits [3:2]='01' Full Packets queued) Bits [3:2]='00' Partially Full Packets queued) EP13TX_FULL EP12TX_EMPTY Endpoint Transmit Packet FIFO Status Bits [1:0]='11' Invalid Bits [1:0]='10' Empty Packets queued) Bits [1:0]='01' Full Packets queued) Bits [1:0]='00' Partially Full Packets queued) EP12TX_FULL
Table Management Register TX_MGMT (0x7F67 RESET=0x00) Management Register NAME DESCRIPTION [7:1] Reserved Reserved MEM_DALL Memory deallocate Mode Auto Manual deallocation, FIFO still automatic. This control selects between Auto Manual memory pages deallocation. This should statically start operation, changed during about transmit. This defaults normal operation. When set, handles freeing memory pages.
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SERIAL INTERFACE ENGINE (SIE) REGISTER DESCRIPTION Packet Header Definition following header contains information determine endpoint, status, length received packet, payload "received data". Table Packet Header Definition Payload Data Byte payload data size, which Byte Count Length Packet, Byte Count 0x008 byte Packet, Byte Count 0x009 Packet, (Byte Count-1) points last byte payload data Payload Data Byte BYTE COUNT[10.8] BYTE COUNT[7.0] EXTENDED FRAME COUNT[15.11] FRAME COUNT[10.8] FRAME COUNT[7.0] RESERVED TMP_ADDRESS[6.0] PACKET ID[3.0] Bad_CR Last_TOG Bad_TOG ENDPOINT[3.0]
OFFSET
0x008 0x007 0x006 0x005 0x004 0x003 0x002 0x001 0x000
Packet Description: Offset packet header. Offset 0x000 0x005 generated SIE. iii) Offset 0x000 Bad_TOG- This when receives unexpected toggle. This necessarily error condition, This could indicate condition when return handshake packet lost. Note that this isochronous transfers. LAST PACKET TOGGLE VALUE CURRENT PACKET TOGGLE VALUE
"BAD TOG"
iii) Offset 0x000 Last_TOG last toggle received. iii) Offset 0x000 Bad_CRC, when detects CRC. Offset 0x006 0x007 generated SIEDMA.
Offset actual data received from stored memory.
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Interface Registers architecture USB97C102 such that there data FIFO's associated with individual endpoints. does differentiate packets endpoint number. firmware must read endpoint number from packet header pass packet appropriate endpoint handler. This makes chip dynamic flexible allocating buffers store payload size from 1280 bytes. Each endpoint configured separately following register. Table Endpoint Control Registers EP_CTRL[15.0] (0x7F8F-0x7F80 RESET=0x00) ENDPOINT CONTROL REGISTERS NAME DESCRIPTION TX_ISO instructs handle handshakes transmit endpoints during "IN" transactions, SIEDMA engine should handle packet queue status after packet transmission. When endpoint configured isochronous operation (Bit '1'), packet transmissions considered successful SIEDMA must move packet number into Completion FIFO. When endpoint nonisochronous (Bit '0'), then must receive valid handshake from host before packet released. This guarantees data integrity non-isochronous transactions. Successfully transmitted packets automatically de-queued packet released. Non-Isochronous Isochronous instructs handle handshakes receive endpoints during "OUT" "SETUP" transactions. Once packet matches 7-bit Function Address, must begin page allocation generate packet buffer RAM. must check PID_Valid CRC_Valid bits dequeue "bad" packets. will inhibit handshakes when enabled. Non-isochronous Isochronous 0,0= Endpoint disabled, does send handshakes. 0,1= Send STALL handshake transaction directed this 1,0= Normal Operation. sent depending whether data EPXs TX_QUEUE. 1,1= Send handshake transaction directed this regardless TX_QUEUE status. (Note 0,0= Endpoint disabled, does send handshakes. 0,1= Send STALL handshake transaction directed this 1,0= Normal Operation. sent depending RX_OK status 1,1= Send handshake transaction directed this (Note This toggled after each successful transmission. TX_TOGGLE reset cleared must insure that endpoint disabled before modifying them. isochronous transmits, this won't toggled hardware. This reflects last DATA0/DATA1 toggle. isochronous receives, this will still hold received toggle, won't checked Toggle error.
RX_ISO
TX_CONT[1:0]
RX_CONT[1:0]
TX_TOGGLE
RX_TOGGLE
Note There Endpoint Control Register virtual endpoint. When decodes token, endpoint number used index which EP_CTRL register bits should used respond SIEDMA. Note This register allows firmware throttle back packets specific endpoint(s) until firmware decides congestion subsided.
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Note firmware needs STALL endpoint, should first taken off-line setting RX_CONT1=0, then RX_CON0=1. Note This allows firmware manage endpoint(s) hold queued data until firmware ready, even host asking. This critical version, required Isochronous synchronization, well STALL recovery. Note These registers written time won't affected until after current transaction particular endpoint) completed. particular register written several times during transaction, only last value written will take effect after transaction complete. Table FRAME Count Register FRAMEL 0x7F90 Reset 0x00 FRAME COUNT REGISTER (LOW) NAME DESCRIPTION [7:0] FRAME[7:0] Frame Number from each packet loaded with RISING edge when SOF_TOKEN '1'. Note: This register always last correctly received valid Frame number. Garbled invalid tokens alter this register. However, FRAME/MSB FRAME Count registers will incremented hardware when missing detected, when there error frame number. defined missing does occur within range USBCLKs from expected frame length. expected frame length previous interval between SOFs. Table FRAME Count Register FRAMEH 0x7F91 Reset 0x00 NAME EXT_FR[15:11] FRAME COUNT REGISTER (HIGH) DESCRIPTION Extended Frame Count. extended count bits loaded with RISING edge when SOF_TOKEN '1'. extended Frame count must also enabled (EN_EXTFRAME SIE_CONFIG). Frame Number from each packet loaded with RISING edge when SOF_TOKEN '1'.
[7:3]
[2:0]
FRAME[10:8]
Note:
This register always last correctly received valid Frame number. Garbled invalid tokens alter this register. However, FRAME/MSB FRAME Count registers will incremented hardware when missing detected, when there error frame number. defined missing does occur within range USBCLKs from expected frame length. expected frame length previous interval between SOFs. Table Local Address Register SIE_ADDR (0x7F92 RESET=0x00) LOCAL ADDRESS REGISTER NAME DESCRIPTION RX_ALL Overrides token address decoding such that compare done. Token also ignored when RX_ALL=1. This forces packets transmitted wire received Packet Queue [6:0] ADDR[6:0] This register only written 8051. SIE's local address assigned during enumeration. This default
address. endpoints will send/receive this address. This address used address.
Note: When RX_ALL enabled, software should enable endpoints they will respond Address with same endpoint possibly cause contention line. Software should also each endpoint RX_ISO prevent handshakes from being sent.
SMSC USB97C102
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Rev. 03/23/2000
Table Alternate Address Register ALT_ADDR1 (0x7F99 RESET=0x00) ALTERNATE ADDRESS NAME DESCRIPTION EN_ALTADDR1 Alternate address. Enabled, this allows Endpoints through available this address. Disabled, this register does affect EP_OK generation. ALT6 Alternate address ALT5 Alternate address ALT4 Alternate address ALT3 Alternate address ALT2 Alternate address ALT1 Alternate address ALT0 Alternate address Note Firmware (8051) must make sure that endpoint configurations overlap. Table Alternate Address Register ALT_ADDR2 (0x7F9E RESET=0x00) ALTERNATE ADDRESS NAME DESCRIPTION EN_ALTADDR2 Alternate address Enabled, this allows Endpoints through available this address. Disabled, this register does affect EP_OK generation. ALT6 Alternate address ALT5 Alternate address ALT4 Alternate address ALT3 Alternate address ALT2 Alternate address ALT1 Alternate address ALT0 Alternate address Table Alternate Address Register ALT_ADDR3 (0x7F9F RESET=0x00) ALTERNATE ADDRESS NAME DESCRIPTION EN_ALTADDR Alternate address Enabled, this allows Endpoints through available this address. Disabled, this register does affect EP_OK generation. ALT6 Alternate address ALT5 Alternate address ALT4 Alternate address ALT3 Alternate address ALT2 Alternate address ALT1 Alternate address ALT0 Alternate address
SMSC USB97C102
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Rev. 03/23/2000
ALTERNATE ADDRESS ENDPOINT MAPPING
This section will describe Endpoint Mapping relative Alternate Address registers defined above. Table Mapping External Endpoint Numbers Internal Endpoint Numbers, page below, describes Endpoint mapping relative address embedded packet. This table describes mapping Packet which transmitted (USB Packet) received (USB packet) destined particular USB97C102 address. Remember, that USB97C102 possible address filters. translation conversion Endpoint Number. Endpoint Number packets destined particular address, Endpoint Number translated accordingly defined Table 102. Example packet: packet wire, which contains address destined USB97C102 with value that matches Alternate Address (ALT_ADDR2 Register- 0x7F9E) endpoint number received, then packet header contains Alternate Address address value Endpoint Number External Endpoint Number converted internal endpoint number packets directed alternate address Example packet: When SMSC 97C102 (8051) building packet send host, packet enqueued onto Transmit FIFO's which maps each Endpoint. other words, each Endpoint transmit FIFO. When token received from host, that addressed alternate address endpoint then pops packet FIFO endpoint seen, endpoint translation performed outgoing well incoming packets described Table 102. Please refer SMSC USB97C102 Programmers Reference Guide additional details. Multiple Endpoint Mapping When SMSC USB97C102 Firmware Developer uses Alternate Address registers implement specific device implementations, internal Endpoints mapped multiple times relative External Endpoint. Example: packet received, that addressed alternate address then external endpoint numbers converted internal endpoint number Table Mapping External Endpoint Numbers Internal Endpoint Numbers EXTERNAL WIRE) INTERNAL PACKET HEADER) Addr Addr Addr Addr
SMSC USB97C102
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Table Status Register SIE_STAT (0x7F93 RESET=0x03) STATUS REGISTER NAME DESCRIPTION Indicates that error occurred during last transaction. Considered valid rising edge TIMEOUT Indicate that last transaction ended because inter-packet time condition (i.e.:>16 times). Considered valid rising edge EOT. SETUP_TOKEN Indicates that token received SETUP token. SOF_TOKEN Indicates that been received. Considered valid when '0'. PRE_TOKEN Indicates that detected (preamble) packet bus. signal asserted when seen valid SYNC followed valid PID. Indicates that last transaction completed without error time-out. Considered valid rising edge EOT. USB_RESET When active '1', indicates that line being reset. This signal asserted when detects string single ended long time. [During USB_RESET, this set(1). When firmware sends system reset, this cleared(0)] Transaction. transition '1', indicates transaction. transition indicates beginning transaction. Note: This read only register reflects status signals from state machine. This register polled test purposes, error handling routines recovery. Table Control Register SIE_CTRL1 (0x7F94 RESET=0x00) CONTROL REGISTER NAME DESCRIPTION SIEDMA_DISABLE Normal operation Inhibits SIEDMA operation facilitate override FORCE_RXOK Forces send Acknowledge during receive. Must normal operation. FORCE_TTAG Normal operation Signals that next byte written TX_FIFO last payload byte. FORCE_RXOVFLO Normal operation. Forces generate RXOVFLO clear FIFO. FORCE_TXABORT Normal operation Forces bit-stuff error host FORCE_EOT Normal operation Forces End-of-Transaction RTAG_IN Status RTAG signal from FIFO TXOK_IN Status TXOK from
Note:
Bits must normal operation. Altering these bits will cause abnormal behavior.
SMSC USB97C102
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Table Configuration Register. SIE_CONFIG (0x7F98 RESET=0x40) CONFIGURATION REGISTER NAME DESCRIPTION FSEN This indicates that USB97c102 supports 12Mbps data rates. This must normal operation. RST_SIE Resets RST_FRAME Clears FRAMEL through FRAMEH EN_EXTFRAME Extended Frame Count Enable. Expands Frame count from bits bits 8051 use. Bits FRAMEH driven Bits FRAMEH count transitions FRAMEH. SIE_SUSPEND Forces into Suspend Mode. must determine that Suspend must entered. SIE_RESUME Forces transmit Resume signaling line. USB_RESUME Indicates Resume signaling been detected line while Suspend State. This signal causes Resume Power Management interrupt). USB_RESET Indicates that line being reset. Asserted when present more Mbps times. This causes USB_RESET Power management interrupt. Table Control Register SIE_CTRL (0x7FA9 RESET=0x00) CONTROL REGISTER NAME DESCRIPTION Reserved Reserved This should always cleared Reserved Reserved This should always cleared Reserved Reserved This should always cleared Reserved Reserved This should always cleared Reserved Reserved This should always cleared SET_BUSY_ON_SETU When (1), setup pckt rcvd control endpoint will that endpoint busy direction disabled. When clear (0), setup pckt will have effect endpoint's control condition. [1:0] ISO_LIMIT ISO_Limit Defines maximum size isochronous packet PAYLOAD SIZE 1023 byte payload byte payload total less byte header byte Data payload byte payload total less byte header byte Data payload byte payload total less byte header byte Data payload conjunction with Endpoint Control Registers defined above, Endpoint Command Register allows dynamic modification configuration specific endpoints. This register which SMSC Family devices, allows write each individual field within existing register Endpoint without having read modify write operations. Firmware this register with full constant, could OR-in number.
SMSC USB97C102
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This register allows individual setting clearing bits EP_CTRL registers. Table Endpoint Command Register EP_COMM (0x7FAA- RESET=0x00) ENDPOINT Command Register NAME DESCRIPTION This bit, when will allow command specified bits TX/RX control endpoint. When this cleared (0), command control endpoint. other words, (1), command will affect TX_ISO, TX_ENABLE, STALL_TXEP, TX_TOGGLE (defined EPCTRL). clear (0), command will affect RX_ISO, RX_ENABLE, STALL_RXEP, RX_TOGGLE (also defined EPCTRL). [6:4] COMMAND COMMAND BITS Endpoint disabled, does send handshakes. Send STALL handshake and/or transaction directed this Normal Operation. sent depending whether data EPXs TX_QUEUE conversely EPX's receive transactions. Send handshake and/or transaction directed this regardless TX_QUEUE status. Clear Toggle Toggle Clear
EP_COMM (0x7FAA- RESET=0x00) NAME [3:0] EP_Select
ENDPOINT Command Register DESCRIPTION ENDPOINT SELECT Endpoint Endpoint Endpoint Endpoint Endpoint Endpoint Endpoint Endpoint Endpoint Endpoint Endpoint Endpoint Endpoint Endpoint Endpoint Endpoint
Section 8.4.5.4 Spec V1.1 states that non-control endpoint receives SETUP PID, must ignore transaction return response." order hardware this correctly, needs know which endpoints non-control endpoints. Each NonControl Endpoint registers will correspond associated Endpoint. Bits NonControl Endpoint register will correspond Endpoints 7-15. Bits NonControl Endpoint will correspond
SMSC USB97C102 Page Rev. 03/23/2000
Endpoints 0-7. will write these registers, corresponding bit=1 each endpoint that noncontrol endpoint. hardware will respond Setup endpoint whose corresponding (1). Table NonControl Endpoint Register (high endpoints) NONCTRL_EP1 (0x7FAB RESET=0x00) NONCONTROL ENDPOINT REGISTER NAME DESCRIPTION EP15 When this (1), Endpoint will respond Setup PID. When this cleared (0), Endpoint will respond setup EP14 When this (1), Endpoint will respond Setup PID. When this cleared (0), Endpoint will respond setup EP13 When this (1), Endpoint will respond Setup PID. When this cleared (0), Endpoint will respond setup EP12 When this (1), Endpoint will respond Setup PID. When this cleared (0), Endpoint will respond setup EP11 When this (1), Endpoint will respond Setup PID. When this cleared (0), Endpoint will respond setup EP10 When this (1), Endpoint will respond Setup PID. When this cleared (0), Endpoint will respond setup When this (1), Endpoint will respond Setup PID. When this cleared (0), Endpoint will respond setup When this (1), Endpoint will respond Setup PID. When this cleared (0), Endpoint will respond setup Table NonControl Endpoint Register (low endpoints) NONCTRL_EP2 (0x7FAC RESET=0x00) NONCONTROL ENDPOINT REGISTER NAME DESCRIPTION When this (1), Endpoint will respond Setup PID. When this cleared (0), Endpoint will respond setup PID. When this (1), Endpoint will respond Setup PID. When this cleared (0), Endpoint will respond setup PID. When this (1), Endpoint will respond Setup PID. When this cleared (0), Endpoint will respond setup PID. When this (1), Endpoint will respond Setup PID. When this cleared (0), Endpoint will respond setup PID. When this (1), Endpoint will respond Setup PID. When this cleared (0), Endpoint will respond setup PID. When this (1), Endpoint will respond Setup PID. When this cleared (0), Endpoint will respond setup PID. When this (1), Endpoint will respond Setup PID. When this cleared (0), Endpoint will respond setup PID. When this (1), Endpoint will respond Setup PID. When this cleared (0), Endpoint will respond setup PID. Table Reserved RESERVED DESCRIPTION Reserved
[7:0]
RESERVED NAME Reserved
Memory Management Policy (MMP) feature permits limiting number received packets memory endpoint. five up/down counter will implemented each endpoint. Each counter will incremented initialize limit, then decremented hardware packets arrive corresponding endpoint, incremented after releases packet. count reaches feature enabled, then hardware will receive packet will non-isochronous tokens. count zero, will decrement further; count will increment further. enable disable this feature independently each endpoint. default condition disabled.
SMSC USB97C102
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following register allows access control up/down counters each endpoint: Table Memory Management Policy Command Register MMPCMD (0x7FAE) ENDPOINT COMMAND REGISTER NAME DESCRIPTION COMMAND COMMAND BITS Disable Memory Management Policy feature. disabled, endpoint counters will still count, there will action taken when counter reaches zero. Enable Memory Management Policy feature. Decrement count must have previously made endpoint busy before executing this command. Increment count must have previously made endpoint busy before executing this command. State this will cause count enable/disable state latched into MMPSTAT register. Reserved
[7:5]
Reserved MMPCMD (0x7FAE)
Reserved Reset counter zero disable feature. Reserved Reads back
[3:0]
NAME EP_Select
ENDPOINT COMMAND REGISTER DESCRIPTION ENDPOINT SELECT Endpoint Endpoint Endpoint Endpoint Endpoint Endpoint Endpoint Endpoint Endpoint Endpoint Endpoint Endpoint Endpoint Endpoint Endpoint Endpoint
Table Memory Management Policy State Register MMPSTATE 0x7FAF Reset 0x00 MEMORY MANAGEMENT POLICY STATE REGISTER NAME DESCRIPTION Enabled State latched most recent State Command MMPCMD register. When set(1), feature will enabled; when clear(0), feature will disabled. [6:5] Reserved Reserved Read back [4:0] Count Count latched most recent State Command MMPCMD register. Note MMPSTATE register read/write only read normal operation.
SMSC USB97C102 Page Rev. 03/23/2000
Table IN_NAKLO Register IN_NAKLO (0x7FEC RESET=0x00) IN_NAKLO REGISTER NAME DESCRIPTION This when responds with IN_NAK_7 tokens reset when writes This when responds with IN_NAK_6 tokens reset when writes IN_NAK_5 This when responds with tokens reset when writes IN_NAK_4 This when responds with tokens reset when writes IN_NAK_3 This when responds with tokens reset when writes IN_NAK_2 This when responds with tokens reset when writes IN_NAK_1 This when responds with tokens reset when writes IN_NAK_0 This when responds with tokens reset when writes Table IN_NAKHI Register IN_NAKHI (0x7FED RESET=0x00) IN_NAKHI REGISTER NAME DESCRIPTION This when responds with IN_NAK_15 tokens reset when writes This when responds with IN_NAK_14 tokens reset when writes IN_NAK_13 This when responds with tokens reset when writes IN_NAK_12 This when responds with tokens reset when writes IN_NAK_11 This when responds with tokens reset when writes IN_NAK_10 This when responds with tokens reset when writes IN_NAK_9 This when responds with tokens reset when writes IN_NAK_8 This when responds with tokens reset when writes Table OUT_NAKLO Register OUT_NAKLO (0x7FEE RESET=0x00) OUT_NAKLO REGISTER NAME DESCRIPTION OUT_NAK_7 This This set(1) when after responds with tokens reset(0) after when writes OUT_NAK_6 This set(1) when after responds with tokens reset(0) when after writes OUT_NAK_5 This set(1) when responds with tokens reset(0) when after writes OUT_NAK_4 This set(1) when responds with tokens reset(0) when after writes OUT_NAK_3 This set(1) when responds with tokens reset(0) when after writes
SMSC USB97C102
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Rev. 03/23/2000
OUT_NAKLO (0x7FEE RESET=0x00) NAME OUT_NAK_2
OUT_NAK_1
OUT_NAK_0
OUT_NAKLO REGISTER DESCRIPTION This set(1) when responds with tokens reset(0) when after writes This set(1) when responds with tokens reset(0) when after writes This set(1) when responds with tokens reset(0) when after writes
Table OUT_NAKHI Register OUT_NAKHI (0x7FEF RESET=0x00) OUT_NAKHI REGISTER NAME DESCRIPTION OUT_NAK_15 This set(1) when after responds with tokens reset(0) when after writes OUT_NAK_14 This set(1) after when responds with tokens reset(0) when after writes OUT_NAK_13 This set(1) when after responds with tokens reset(0) when after writes OUT_NAK_12 This set(1) when after responds with tokens reset(0) when after writes OUT_NAK_11 This set(1) when after responds with tokens reset(0) when after writes OUT_NAK_10 This set(1) when after responds with tokens reset(0) when after writes OUT_NAK_9 This set(1) when after responds with tokens reset(0) when after writes OUT_NAK_8 This set(1) when after responds with tokens reset(0) when after writes
SMSC USB97C102
Page
Rev. 03/23/2000
BLOCK registers shown below interface Internal 8051 with SMSC97C102 internal Block. MCU, subsequent reset initialization, must initialize register block first task. Initialization registers below, must accomplished within after de-assertion reset. must initialize registers before stream host controller relinquishes reset pulse internal block that Host Controller enumerate device. Below block diagram block. indicated diagram, block consists Repeater, Control Command sequencer.
Down Stream Ports Upstream Port
PORT0 PORT1 Internal PORT2 Walkup PORT3 Walkup PORT4 Walkup PORT5 Walkup
Port Control
Port Control
Port Control
Port Control
Port Control
Port Control
Repeater
Serial Interface Engine
Command Sequencer
Power Control
Mode
From Control Reg.
Power Control
USB97C102 Compound Device Block
System Interface Unit This module consists address decoding multiplex logic. address decoder logic used compare address received from host during SETUP, token transfer with address HUB. There address decodes, endpoint Remote Device Control endpoint which part Block. Interface Unit Interface Unit (HIU) provides controller function this compound device. controller provides functionality Host communication. specific control status commands defined device class specification permit host controller configure control monitor each down stream port. control block, most part, like full speed device hence consists function blocks needed implement device. Included functionality required endpoint control, enumeration, control packet decoding, status maintenance reporting. Additional functions that will performed block include: Provide descriptors defined Device Class Specification Configuration Port Status
SMSC USB97C102 Page Rev. 03/23/2000
Power Status
Interrupt endpoint status change reporting Port Power control Frame Timer logic Fault Recovery Selective Suspend Resume port port basis Selective Reset port port basis ability decode preamble allowing Speed port enabling. Full-speed/Low-speed transceivers implemented internally; placed upstream port four placed downstream ports Reflecting Remote Resume Upstream enabled down stream ports Block Register Summary Register definitions defined below defined Table and. These registers memory mapped into 8051 memory space defined Figure Table Block Register Summary DESCRIPTION byte Vendor little endian format (Bit LSB) High byte Vendor little endian format (Bit LSB) byte Product value little endian format (Bit LSB). This value initialized firmware upon initialization/power This value must initialized prior device participating enumeration transactions. IdProductR/W High byte Product value little endian High Byte format (Bit LSB). This value initialized firmware upon initialization/power This value must initialized prior device participating enumeration transactions. BcdDevice This 8-bit value defines device release Byte number, which assigned system manufacture. NAME IdVendorLow Byte IdVendorHigh Byte IdProductLow Byte BcdDevice High Byte HubControl1 Reserved This 8-bit value defines device release number, which assigned system manufacture. Control register Reserved This register should never accessed
ADDRESS 7FA0 7FA1 7FA2
PAGE
7FA3
7FA4
7FA5
7FA6 7FA7
Table Control Register1 HubControl1 (0x7FA6- RESET=0x00) NAME NhubReset CONTROL REGISTER1 DESCRIPTION NHubReset When this asserted (0), controller reset state. will respond enumeration device requests. When this de-asserted (1), controller ready receive packets from Root Host Controller. Each Port will then enabled control packet from Host Reserved This should always cleared When this set(1), Ports longer connected hub. Port (which connected rest 97C102) connected port Port becomes upstream Port figure next page. Note1. When this set(1), Ports longer connected hub. Port (which connected rest 97C102) connected port Port becomes upstream Port figure next page. Note1.
Page Rev. 03/23/2000
Reserved HubBypass5
HubBypass4
SMSC USB97C102
HubControl1 (0x7FA6- RESET=0x00) NAME HubBypass3
HubBypass2
ForceSE0
GangedPWR
CONTROL REGISTER1 DESCRIPTION When this set(1), Ports longer connected hub. Port (which connected rest 97C102) connected port Port becomes upstream Port figure next page. Note1. When this set(1), Ports longer connected hub. Port (which connected rest 97C102) connected port Port becomes upstream Port figure next page. Note1. Force Single Ended zero (SE0). This will force condition upstream port Port selected Host_EmuX bits). responsibility 8051 make sure duty cycle assertion within specified range intended operation (EOP exactly speed periods; Disconnect 2.5µs). Ganged Power Sense enable When this (1), Power Control block Compound device will internally power sense pins (nPWROK[5:2]) Power Enable (nPWREN[5:2]) pins. This will allow system designer ability reduce implementation costs reducing external current hardware. this mode, since only Sense Enable required, unused input pins must tied unused output pins left unconnected.
Note When SMSC USB97C102 "HubBypass" mode, other ports, with HubBypass cleared (0), still connected internal Hub. Please refer FIGURE HUBBYPASS2 page diagram showing "HubBypass" mode. recommended that only "HubBypass" set.
SMSC USB97C102
Page
Rev. 03/23/2000
BYPASS MODE
Bypass mode configuration option availaible SMSC USB978C102. This optional mode operation allows system developer ability disconnect Internal compliant from SIE. reasons designer would want this follows: designer want disconnect from function diagnostic purposes. This option give designer ability make 97C102 backward compatible SMSC 97C100 device.
Disconnecting from function "HubBypass mode", Table Control Register1 page setting appropriate HubBypass2, HubBypass3, etc., will connect associated Down stream port internal function. Please note that only HubBypass should time. Setting more than will cause unexpected results. USB97C100 Compatibility Mode SMSC USB97C102 placed mode emulate SMSC USB97C100 terms functionality. SMSC USB97C102 also "Pin" compatible USB97C100. Please refer application note titled "Utilizing SMSC USB97C102 USB97C100 designs" additional information. order place USB97C102 mode that function compatible SMSC USB97C100, SMSC USB97C102 should have "HubBypass2" HubControl1 register. Table Control Register1 page diagram shown FIGURE shows configured bypass mode
PORT0
Upstream Port
Block
Down Stream Ports
PORT1 Internal
Upstream Port Port
PORT3 PORT4 PORT5 PORT2
FIGURE HUBBYPASS2
SMSC USB97C102
Page
Rev. 03/23/2000
PARAMETERS
MAXIMUM GUARANTEED RATINGS Operating Temperature Range Storage Temperature Range .-55 +150 Lead Temperature Range (soldering, seconds). +325 Positive Voltage pin, with respect Ground Vcc+0.3V Negative Voltage pin, with respect Ground .-0.3V Maximum .+3.6V *Stresses above specified parameters could cause permanent damage device. This stress rating only functional operation device other condition above those indicated operation sections this specification implied. Note: When powering this device from laboratory system power supplies, important that Absolute Maximum Ratings exceeded device failure result. Some power supplies exhibit voltage spikes their outputs when power switched off. addition, voltage transients power line appear output. When this possibility exists, suggested that clamp circuit used. ELECTRICAL CHARACTERISTICS 70°C, +3.3 10%) PARAMETER SYMBOL UNITS Type Input Buffer Input Level High Input Level ICLK Input Buffer Input Level High Input Level Input Leakage (All buffers) Input Leakage High Input Leakage Type Buffer Output Level

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