Frequency Generator Integrated Buffers Celeron PII/IIIRecommended Appl
|
|
|
Top Searches for this datasheet
ICS9250-28
Frequency Generator Integrated Buffers Celeron PII/IIIRecommended Application: 810/810E type chipset. Output Features: (2.5V) 133MHz achievable through I2C) SDRAM (3.3V) 133MHz achievable through I2C) (3.3 @33.3MHz IOAPIC (2.5V) 33.3 Hublink clocks (3.3 66.6 (3.3V) (Non spread spectrum) (3.3V) 14.318 Features: Supports spread spectrum modulation, -0.5% down spread. support power management Efficient power management scheme through Uses external 14.138 crystal Alternate frequency selections available through control.
Configuration
IOAPIC VDDL *FS1/REF0 VDDREF VDD3V66 3V66_0 3V66_1 3V66_2 VDDPCI PCICLK0 PCICLK1 VDDA SCLK SDATA VDD48 48MHz_0 48MHz_1 VDDL CPUCLK0 CPUCLK1 SDRAM0 SDRAM1 VDDSDR SDRAM2 SDRAM3 SDRAM4 VDDSDR SDRAM5 SDRAM6 VDDSDR SDRAM7 SDRAM8 SDRAM9 VDDSDR SDRAM10 SDRAM11 VDDSDR SDRAM12
56-Pin 300mil SSOP
This input 50KW pull-down GND.
Functionality Block Diagram
REF0 PLL1 Spread Spectrum
ICS9250-28
Function Tristate Test Active 66MHz SDRAM 100MHz Active 100MHz SDRAM 100MHz Active 133MHz SDRAM 133MHz Active 133MHz SDRAM 100MHz
XTAL
CPU66/100/133 [1:0] 3V66 (2:0) SDRAM (12:0) PCICLK (1:0) IOAPIC
FS(2:0)
Control Logic Config
SDATA SCLK PLL2
Power Groups
Analog VDDREF VDDA PLL1 VDD48 PLL2 Digital VDD3V66, VDDPCI VDDSDR, VDDL
48MHz (1:0)
9250-28 10/26/00 Third party brands names property their respective owners.
reserves right make changes device data identified this publication without further notice. advises customers obtain latest version device data verify that information being relied upon customer current accurate.
ICS9250-28
General Description
ICS9250-28 part chip clock solution 810/810E type chipset. Combined with ICS9112-17, ICS9250-28 provides necessary clock signals such system. Spread spectrum enabled through programming. Spread spectrum typically reduces This simplifies qualification without resorting board design iterations costly shielding. ICS9250-28 employs proprietary closed loop design, which tightly controls percentage spreading over process temperature variations.
Configuration
NUMBER IOAPIC VDDL TYPE DESCRIPTION 2.5V clock output running 33.3MHz. 2.5V power supply IOAPIC Function Select pin. Determines frequency, output functionality 3.3V, 14.318MHz reference clock output. 3.3V power supply Crystal input, internal load (33pF) feedback resistor from Crystal output, nominally 14.318MHz. internal load (33pF) Ground pins 3.3V supply Function Select pins. Determines frequency, output functionality. Please refer Functionality table page 3.3V clock outputs Asynchronous active input used power down device into power state. internal clocks disabled crystal stopped. latency power down will greater than 3ms. Clock circuitry tolerant Data circuitry tolerant 3.3V output running 100MHz. SDRAM outputs turned 2.5V Host clock output. 66MHz, 100MHz 133MHz depending (2:0) pins.
REF0 3V66 (2:0) PCICLK[1:0] SCLK SDATA 48MHz_0
(12RAM CPUCLK (1:0)
ICS9250-28
Power Down Waveform
Note
After sampled active (Low) consective rising edges CPUCLKs, output clocks driven their next High tranistiion. Power-up latency <3ms. Waveform shown 100MHz
Maximum Allowed Current
Condition Powerdown Mode (PWRDWN# Full Active 66MHz FS[2:0] Full Active 100MHz FS[2:0] Full Active 133MHz FS[2:0] 2.5V supply consumption discrete loads, Vddq2 2.625V static inputs Vddq3 10mA 70mA 100mA 130mA 2.5V supply consumption discrete loads, Vddq2 3.465V static inputs Vddq3 10mA 400mA 400mA 450mA
Clock Enable Configuration
CPUCLK SDRAM IOAPIC 66MHz PCICLK REF, 48MHz VCOs
ICS9250-28
Truth Table
Tristate TCLK/2 66.6 SDRAM Tristate TCLK/2 3V66 Tristate TCLK/3 66.6 66.6 66.6 66.6 Tristate TCLK/6 33.3 33.3 33.3 33.3 48MHz Tristate TCLK/2 Tristate TCLK 14.318 14.318 14.318 14.318 IOAPIC Tristate TCLK/6 33.3 33.3 33.3 33.3
Byte Reserved Functionality frequency select register (Default noted PWD)
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Reserved (Note Reserved (Note Reserved (Note Reserved (Note Reserved (Note Undefined (Note Undefined (Note
Desctiption
CPUCLK SDRAM 66.66 100.0 133.32 133.32 66.66 100.0 133.32 133.32 100.0 100.0 133.32 100.0 100.0 100.0 133.32 133.32
3V66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66
PCICLK IOAPIC 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 Note
Note system operation, BSEL lines will program FS0, appropriate speed, always with SDRAM 100MHz. After BIOS verifies SDRAM PC133 speed, then written from default change SDRAM output frequency from 100MHz 133MHz. This will only change 133MHz speed shown this table. CPU, 3V66, PCI, IOAPIC clocks will glitch free during this transition, only SDRAM will change. Note "ICS RESERVED BITS" must writtern "0". Note3: Undefined bits written either
ICS9250-28
Byte Control Register enable, disable)
Name Reserved Reserved Reserved Reserved SpreadSpectrum (1=On/0=Off) 48MHz 48MHz Reserved Note: Reserved bits must written
Byte Control Register enable, disable)
Pin#
Description (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive)
Pin#
Name SDRAM7 SDRAM6 SDRAM5 SDRAM4 SDRAM3 SDRAM2 SDRAM1 SDRAM0
Description (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive)
Byte Control Register enable, disable)
Pin#
Name 3V66-2 (AGP) SDRAM12 SDRAM11 SDRAM10 SDRAM9 SDRAM8 PCICLK1 Reserved
Description (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive)
Notes: Inactive means outputs held disabled from switching. These outputs designed configured power-on expected configured during normal modes operation. Power Default Undefined wirtten with either "0".
ICS9250-28
Byte Reserved Register enable, disable)
Pin#
Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Description (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive)
Notes: Inactive means outputs held disabled from switching. These outputs designed configured power-on expected configured during normal modes operation. Power Default
Group Timing Relationship Table1
Group 66MHz SDRAM 100MHz Offset SDRAM 3V66 SDRAM 3V66 3V66 -2.5ns 7.5ns 0.0ns 1.5-3.5ns 0.0ns Asynch Tolerance 500ps 500ps 500ps 500ps 500ps 100MHz SDRAM 100MHz Offset 5.0ns 5.0ns 0.0ns 1.5-3.5ns 0.0ns Asynch Tolerance 500ps 500ps 500ps 500ps 500ps 133MHz SDRAM 100MHz Offset 0.0ns 0.0ns 0.0ns 1.5-3.5ns 500ps Asynch Tolerance 500ps 500ps 500ps 500ps 1.0ns 133MHz SDRAM 133MHz Offset 3.75ns 0.0ns -3.75ns -3.5ns 0.0ns Asynch Tolerance 500ps 500ps 500ps 500ps 500ps
ICS9250-28
Absolute Maximum Ratings
Core Supply Voltage Supply Voltage 3.6V Logic Inputs -0.5 +0.5 Ambient Operating Temperature +70°C Maximum Case Operating Temperature +135°C Storage Temperature -65°C +150°C Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. These ratings stress specifications only functional operation device these other conditions above those listed operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect product reliability.
Electrical Characteristics Input/Supply/Common Output Parameters
70C; Supply Voltage +/-5%, VDDL +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Input High Voltage VSS-0.3 Input Voltage Input High Current IIL1 Inputs with pull-up resistors Input Current Inputs with pull-up resistors IIL2 -200 66/100 100/100 133/133 133/100 IDD3.3OP loads; 66/100 loads; 100/100 loads; 133/133 Operating Supply Current loads; 133/100 66/100 100/100 133/133 133/100 loads; 66/100 loads; 100/100 loads; 133/133 IDD3.3PD IDD.25PD Ttrans loads; 133/100 loads Input address crossing target frequency From crossing target frequency 14.318 VDD+0.3 UNITS
IDD2.5OP
Powerdown Current Input Frequency Transition time
Settling time Stabilization1 Delay1
TSTAB From target frequency tPZH,tPZL Output enable delay (all outputs) tPHZ,tPLZ Output disable delay (all outputs)
Guaranteed design, 100% tested production.
ICS9250-28
Electrical Characteristics
70C; VDDL +/-5%; 10-20 (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Impedance RDSP2B VDD*(0.5) VDD*(0.5) Output Impedance RDSN2B1 Output High Voltage VOH2B Output Voltage VOL2B IOH2B Output High Current 2.375 IOL2B Output Current Rise Time1 Fall Time
13.5 13.5
UNITS
tr2B tf2B dt2B tsk2B tjcyc-cyc2B
1.25 1.25 1.25
Duty Cycle Skew window1 Jitter, Cycle-to-cycle1
Guaranteed design, 100% tested production.
Electrical Characteristics 3V66
70C; +/-5%; 10-20 (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Impedance RDSP1B1 VDD*(0.5) VDD*(0.5) Output Impedance RDSN1B1 Output High Voltage VOH1 Output Voltage VOL1 IOH1 Output High Current 3.135 1.95 IOL1 Output Current Rise Time1 Fall Time1 Duty Cycle1 Skew window1 Jitter, Cycle-to-cycle1
14.5
UNITS 0.55
-108
tsk1 tjcyc-cyc1
Guaranteed design, 100% tested production.
ICS9250-28
Electrical Characteristics IOAPIC
70C; VDDL +/-5%; 10-20 (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Impedance RDSP4B VDD*(0.5) Output Impedance RDSN4B1 VDD*(0.5) Output High Voltage VOH4B Output Voltage VOL4B IOH4B Output High Current 2.375 IOL4B Output Current Rise Time1 Fall Time
UNITS
tr4B tf4B dt4B tjcyc-cyc4B
1.25 1.25
Duty Cycle Jitter, Cycle-to-cycle1
Guaranteed design, 100% tested production.
Electrical Characteristics SDRAM
70C; +/-5%; 20-30 (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Impedance RDSP3B1 VDD*(0.5) VDD*(0.5) Output Impedance RDSN3B1 Output High Voltage VOH3 Output Voltage VOL3 IOH3 Output High Current 3.135 IOL3 Output Current Rise Time1 Fall Time1 Duty Cycle1 Skew window1 Jitter, Cycle-to-cycle
UNITS
tsk3 tjcyc-cyc3
Guaranteed design, 100% tested production.
ICS9250-28
Electrical Characteristics
70C; +/-5%; 10-30 (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Impedance RDSP1B VDD*(0.5) VDD*(0.5) Output Impedance RDSN1B1 Output High Voltage VOH1 Output Voltage VOL1 IOH1 Output High Current 3.135 1.95 IOL1 Output Current Rise Time1 Fall Time
UNITS 0.55
-106
tsk1 tjcyc-cyc1
Duty Cycle Skew window1 Jitter, Cycle-to-cycle1
Guaranteed design, 100% tested production.
Electrical Characteristics REF, 48MHz_0 (Pin
70C; +/-5%; 10-20 (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Impedance RDSP5B1 VDD*(0.5) Output Impedance RDSN5B1 VDD*(0.5) Output High Voltage VOH15 Output Voltage VOL5 IOH5 Output High Current 3.135 1.95 IOL5 Output Current Rise Time1 Fall Time1 Duty Cycle1 Jitter, Cycle-to-cycle1 Jitter, Cycle-to-cycle1
UNITS 0.55 1000
tjcyc-cyc5 tjcyc-cyc5
Fixed clocks clocks
Guaranteed design, 100% tested production.
ICS9250-28
Electrical Characteristics 48MHz_1 (Pin
70C; +/-5%; 10-15 (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Impedance RDSP3B VDD*(0.5) Output Impedance RDSN3B1 VDD*(0.5) Output High Voltage VOH3 Output Voltage VOL3 IOH3 Output High Current 3.135 IOL3 Output Current Rise Time1 Fall Time
UNITS 0.55
tjcyc-cyc3B
Duty Cycle Jitter, Cycle-to-cycle1
Guaranteed design, 100% tested production.
ICS9250-28
Group Skews (CPU MHz, SDRAM 100MHz)
+/-5%, VDDL +/-5% IOAPIC load (lumped) PCI, SDRAM, 3V66 load (lumped) Refer Group Offset Waveforms diagram definition transition edges. PARAMETER SYMBOL CONDITIONS Tsk1 CPU-SDRAM SDRAM Skew 1.25 SDRAM Skew Window CPU-SDRAM Tsk1 CPU-3V66 3V66 Skew 1.25 3V66 CPU-3V66 Skew Window -500 SDRAM 3V66 Skew1 Tsk1 SDRAM-3V66 SDRAM, 3V66 Skew Window1 SDRAM-3V66 Tsk1 3V66-PCI 3V66 Skew1 3V66, 3V66-PCI Skew Window1 IOAPIC Skew1 Tsk1 IOAPIC-PCI IOAPIC 1.25 Skew Window1 IOAPIC-PCI Guaranteed design, 100% tested production.
-2.7 -0.1
UNITS
Group Skews (CPU MHz, SDRAM 100MHz)
+/-5%, VDDL +/-5% IOAPIC load (lumped) PCI, SDRAM, 3V66 load (lumped) Refer Group Offset Waveforms diagram definition transition edges. PARAMETER SYMBOL CONDITIONS SDRAM Skew1 Tsk2 CPU-SDRAM 1.25 SDRAM CPU-SDRAM Skew Window Tsk2 CPU-3V66 3V66 Skew1 1.25 3V66 CPU-3V66 Skew Window1 -500 SDRAM 3V66 Skew Tsk2 SDRAM-3V66 SDRAM, 3V66 SDRAM-3V66 Skew Window Tsk2 3V66-PCI 3V66 Skew 3V66, 3V66-PCI Skew Window Tsk2 IOAPIC-PCI IOAPIC Skew IOAPIC 1.25 IOAPIC-PCI Skew Window Guaranteed design, 100% tested production.
-0.1
UNITS
ICS9250-28
Group Skews (CPU MHz, SDRAM 133MHz)
+/-5%, VDDL +/-5% IOAPIC load (lumped) PCI, SDRAM, 3V66 load (lumped) Refer Group Offset Waveforms diagram definition transition edges. PARAMETER SYMBOL CONDITIONS Tsk3 CPU-SDRAM 3.25 SDRAM Skew 1.25 SDRAM Skew Window1 CPU-SDRAM Tsk3 CPU-3V66 -500 3V66 Skew 1.25 3V66 CPU-3V66 Skew Window1 Tsk3 SDRAM-3V66 -3.25 SDRAM 3V66 Skew SDRAM, 3V66 Skew Window1 SDRAM-3V66 Tsk3 3V66-PCI 3V66 Skew 3V66, 3V66-PCI Skew Window1 Tsk3 IOAPIC-PCI IOAPIC Skew IOAPIC 1.25 Skew Window1 IOAPIC-PCI Guaranteed design, 100% tested production.
3.45 -3.08 -0.1
UNITS 4.25 -4.25
Group Skews (CPU133 MHz, SDRAM 100MHz)
+/-5%, VDDL +/-5% IOAPIC load (lumped) PCI, SDRAM, 3V66 load (lumped) Refer Group Offset Waveforms diagram definition transition edges. PARAMETER SYMBOL CONDITIONS Tsk3 CPU-SDRAM 1.25 SDRAM -500 SDRAM Skew Skew Window1 CPU-SDRAM Tsk3 CPU-3V66 1.25 3V66 -500 3V66 Skew CPU-3V66 Skew Window1 SDRAM, 3V66 -500 SDRAM 3V66 Skew1 Tsk3 SDRAM-3V66 Skew Window1 SDRAM-3V66 Tsk3 3V66-PCI 3V66, 3V66 Skew1 3V66-PCI Skew Window1 Tsk3 IOAPIC-PCI IOAPIC 1.25 IOAPIC Skew Skew Window1 IOAPIC-PCI Guaranteed design, 100% tested production.
-0.1
UNITS
ICS9250-28
10ns
20ns
30ns
40ns
Cycle Repeats
66MHz 100MHz 133MHz
SDRAM 100MHz SDRAM 133MHz
3V66MHz 33MHz APIC 33MHz 14.318MHz 48MHz
Group Offset Waveforms
ICS9250-28
General serial interface information
information this section assumes familiarity with programming. more information, contact programming application note.
Write:
Controller (host) sends start bit. Controller (host) sends write address clock will acknowledge Controller (host) sends dummy command code clock will acknowledge Controller (host) sends dummy byte count clock will acknowledge Controller (host) starts sending first byte (Byte through byte clock will acknowledge each byte time. Controller (host) sends Stop
Read:
Controller (host) will send start bit. Controller (host) sends read address clock will acknowledge clock will send byte count Controller (host) acknowledges clock sends first byte (Byte through byte Controller (host) will need acknowledge each byte Controller (host) will send stop
Write:
Controller (Host) Start Address D2(H) Dummy Command Code Dummy Byte Count Byte Byte Byte Byte Byte Byte Stop
Stop Byte Byte Byte Byte Byte Byte
(Slave/Receiver)
Read:
Controller (Host) Start Address D3(H) (Slave/Receiver)
Byte Count
Notes:
clock generator slave/receiver, component. read back data stored latches verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. data transfer rate supported this clock generator 100K bits/sec less (standard mode) input operating 3.3V logic levels. data byte format bytes. simplify clock generator interface, protocol only "Block-Writes" from controller. bytes must accessed sequential order from lowest highest byte with ability stop after complete byte been transferred. Command code Byte count shown above must sent, data ignored those bytes. data loaded until Stop sequence issued. power-on, registers default condition, shown.
ICS9250-28
General Layout Precautions: ground plane routing layer areas used traces. Make power traces ground traces wide lower inductance.
Ferrite Bead
22µF/20V Tantalum
22µF/20V Tantalum
Ferrite Bead
3.3V Power Route Ground Clock Load 2.5V Power Route
Notes: clock outputs should have provisions 15pf capacitor between clock output series terminating resistor. shown places improve readability diagram. Optional crystal load capacitors recommended. They should included layout inserted unless needed.
Component Values: Crystal load values determined user 22µF/20V/D case/Tantalum TAJD226M020R 15pF capacitor Fair-Rite products 2512066017X1 unmarked capacitors 0.01µF ceramic
Connections VDD:
ICS9250-28
SYMBOL
Millimeters COMMON DIMENSIONS 2.413 0.203 0.203 2.794 0.406 0.343
Inches COMMON DIMENSIONS .095 .008 .008 .110 .016 .0135
VARIATIONS
0.127 0.254 VARIATIONS 10.033 7.391 0.381 10.668 7.595 0.635
.005 .010 VARIATIONS .395 .291 .015 .420 .299 .025
0.635 BASIC 0.508 1.016 VARIATIONS
0.025 BASIC .020 .040 VARIATIONS
9.398 11.303 15.748 18.288 20.828 9.652 11.557 16.002 18.542 21.082 .370 .445 .620 .720 .820
(inch) .380 .455 .630 .730 .830
Ordering Information
ICS9250yF-28-T
Example:
XXXX
Designation tape reel packaging Pattern Number digit number parts with code patterns) Package Type F=SSOP
Revision Designator (will correlate with datasheet revision)
Device Type (consists digit numbers) Prefix ICS, Standard Device
reserves right make changes device data identified this publication without further notice. advises customers obtain latest version device data verify that information being relied upon customer current accurate.
Other recent searches
SAM87RI - SAM87RI SAM87RI Datasheet
S75WS-P - S75WS-P S75WS-P Datasheet
S30MS-P - S30MS-P S30MS-P Datasheet
PZT-5 - PZT-5 PZT-5 Datasheet
MA3SD29FG - MA3SD29FG MA3SD29FG Datasheet
M312L2920MT0 - M312L2920MT0 M312L2920MT0 Datasheet
HMC866LC3C - HMC866LC3C HMC866LC3C Datasheet
BAS69 - BAS69 BAS69 Datasheet
2SC4962 - 2SC4962 2SC4962 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
