RTD2000 Dual-Interface Display Controller Revision Oct. 2000
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RTD2000
RTD2000 Dual-Interface Display Controller
Revision Oct. 2000
Copyright ©1999-2000
RTD2000
Contents
Features Pin-out General Description Functional Description
Input Output Brightness, Contrast Gamma Correction Color Auto-Adjustment System Host Interface
Register Description Electrical Specification Mechanical Specification
Copyright©1999-2000
RTD2000 Features
General Convert NTSC/PAL signal into flat panel display device timing resolution Built-in color space converter Embedded external OSD; transparent mode support Input Interface Support 24/48-bit pixel input 100MHz Support TMDS receiver digital interface Support 16-bit YUV422/ 24-bit YUV444 video format input Interface NTSC/PAL decoder, vertical de-interlaced supported Capture window auto position auto phase tracking capability Scaling Fully programmable zoom ratios, times up/down scaling Independent horizontal/vertical zoom advanced zoom algorithm provides original image quality Sharpness filter enhancement Color Processor Digital brightness contrast adjustments Gamma correction Dithering logic 18-bit panel color depth enhancement Output Interface Built-in display timing generator fully programmable 2-pixel/clock panel support pixels/second Compliant with proposed VESA FPDI-2 standard Host Interface Support pins serial interface Power 3.3V power supplier Technology 0.35um SPCMOS process
Copyright©1999-2000
RTD2000 RTD2000 Pin-Out Diagram
AGRN2 AGRN3 AGRN4 AGRN5 AGRN6 AGRN7 ABLU0 ABLU1 ABLU2 ABLU3 ABLU4 ABLU5 ABLU6 ABLU7 BENA VODD BCLK BRED0 BRED1 BRED2 GNDS BRED3 BRED4 BRED5 VDDS BRED6 BRED7 BGRN0 BGRN1 BGRN2 VDDS BRGN3 BGRN4 BGRN5 GNDS BGRN6 BGRN7 BBLU0 BBLU1 BBLU2 BBLU3 BBLU4 BBLU5 BBLU6 BBLU7 GNDP DBBLU0 DBBLU1 DBBLU2 DBBLU3 VDDP DBBLU4 DBBLU5 DBBLU6 DBBLU7 GNDP DBGRN0 DBGRN1 GNDC DBGRN2 DBGRN3 VDDP
AGRN1 AGRN0 ARED7 ARED6 ARED5 ARED4 ARED3 ARED2 ARED1 ARED0 ACLK AENA CLAMP HS_OUT GNDS COAST HS_RAW VDDP GNDP VDDC GNDC GNDP VDDP GNDP
Realtek RTD2000
GNDP REFCLK2 VDDC GNDC GNDP VDDP GNDP VDDP GNDS GNDP VDDS VDDP GNDP GNDP VDDP GNDS SCLK SCSB PWDN# RESET# IRQ# PWM_1 PWM_0 PLLGND FILTER2 PLLVDD AGND
DBGRN4 DBGRN5 DBGRN6 VDDC DBGRN7 DBRED0 GNDP DBRED1 DBRED2 DBRED3 DBRED4 DBRED5 DBRED6 DBRED7 VDDP DABLU0 DABLU1 GNDP DABLU2 DABLU3 DABLU4 DABLU5 DABLU6 GNDC DABLU7 DAGRN0 VDDP DAGRN1 DAGRN2 GNDP DAGRN3 DAGRN4 DAGRN5 DAGRN6 DAGRN7 DARED0 VDDC DARED1 DARED2 GNDP DARED3 DARED4 VDDP DARED5 DARED6 DARED7 GNDC GNDP DCLK OV_VS VDDP OV_HS OVCLK REFCLK1 OV_R OV_G OV_B OVENA OV_I AVDD FILTER1
Copyright©1999-2000
RTD2000 RTD2000 Pin-Out:
Graphic Input Port (RGB data) pins
Name ACLK AENA ARED[0:7] AGRN[0:7] ABLU[0:7] Type Description port input system clock port input system clock enable port vertical sync port horizontal sync port input data port green input data port blue input data
Video/Graphic Input Port (YUV data) pins
Name BCLK BENA BRED/YIN[0:7] BGRN[0:7] BBLU/UVIN[0:7] Type Description port input system clock port input system clock enable port vertical sync port horizontal sync port input data input data port green input data port blue input data input data
Input Port Signals pins
Name CLAMP VODD HS_RAW HS_OUT COAST Type Description Output pulse with programmable width location Interlace mode field status Sync Green Digital Input Horizontal sync (Composite Sync) Output De-composite horizontal sync Output coast signal
Display Port pins
Name DCLK DARED[0:7] DAGRN[0:7] DABLU[0:7] DBRED[0:7] DBGRN[0:7] DBBLU[0:7] Type Description Display reference clock Display vertical sync phase programmable Display horizontal sync phase programmable Display enable Display port data Display port green data Display port blue data Display port data Display port green data Display port blue data
Copyright©1999-2000
RTD2000
Overlay Port Screen Display) pins
Name OVCLK OV_VS OV_HS OVENA OV_I OV_R OV_G OV_B Type Description Clock external overlay circuit Overlay vertical synchronization pulse Overlay horizontal synchronization pulse Enable overlay color Overlay Intensity select Overlay color select Overlay color select Overlay color select
Interface pins
Name RESET# PWDN# IRQ# SCSB SCLK Type Description Reset input initialing device least 8ms) Power Down Mode Interrupt request signal Serial control chip select Serial control clock Serial control input data Serial control output data
Miscellaneous Interface pins
Name FILTER1 FILTER2 REFCLK1 REFCLK2 PWM_0 PWM_1 Type Description Reference clock input Reference clock output DCLK Filter MCLK Filter Input clock display output (DCLK) Input clock DRAM interface (MCLK) Independent PWM_0 output Independent PWM_1 output
Power Ground pins
Name Power Ground Type Description VDDP:13, VDDC:4, VDDS:3, AVDD:1, PLLVDD:1 GNDP:16, GNDC:5, GNDS:5, AGND:1, PLLGND:1
Copyright©1999-2000
RTD2000 General Description
Figure Application System Block Diagram
NTSC
Video Decoder
TMDS/LVDS Transmitter (Option)
RTD2000 Flat Panel Display Application
Panel
14.318MHz
Triple
Key-In
(Option)
EEPROM
12MHz
Copyright©1999-2000
RTD2000
Figure Chip Functional Block Diagram
Flat Panel Display RTD2000
RGB/YUV
Input Latch
FIFO Control
Color Conversion
Sync Processor
Control Register
Scaling
Build-In
Color Processing
Panel
14.318MHz
8-bit
External
Copyright©1999-2000
RTD2000 Functional Description: Input
RTD2000 designed connect interfaces TMDS receiver, call that analog digital interfaces. Obviously, signal "ENA" difference between analog digital I/F. short, latched input data within capture window analog input mode. latched input data while signal "ENA" asserted digital input mode. There four timing schemes designed various input devices switched from control registers. These four schemes single pixel timing, double pixel timing, double pixel offset timing showed following; 4.1.1 Single Pixel Mode
Figure Analog Digital Single Pixel Timing
VGACLK VGAIN Internal Capture Ext.
rgb0 rgb1 rgb2 rgb3 rgb4 rgb5
4.1.2 Double Pixel Mode
Figure Analog Digital Double Pixel Timing
VGACLK VGAIN VGBIN Internal Capture Ext.
rgb0 rgb2 rgb4 rgb6 rgb8 rgb10
rgb1
rgb3
rgb5
rgb7
rgb9
rgb11
Copyright©1999-2000
RTD2000
4.1.3 Double Pixel Offset Mode
Figure Analog Digital Double Pixel Offset Timing
VGACLK VGAIN VGBIN Internal Capture Ext.
rgb0 rgb2 rgb4 rgb6 rgb8 rgb10
rgb1
rgb3
rgb5
rgb7
rgb9
Figure Analog Digital Double Pixel Offset Timing
VGACLK VGAIN VGBIN Internal Capture Ext.
rgb0 rgb2 rgb4 rgb6 rgb8
rgb1
rgb3
rgb5
rgb7
rgb9
rgb11
Copyright©1999-2000
RTD2000
4.1.4 Single Pixel Mode RTD2000 also provides interface video decoder supports interlaced streams which includes 16-bit 4:2:2 24-bit 4:4:4 formats. RTD2000 uses field merging de-interlacing technique outputs progressive scan format.
Figure Input 4:2:2 4:4:4 Timing
VGBCLK YIN(Byte) UVIN(Byte) Internal Capture
VGBCLK YIN(Byte) UIN(Byte) VIN(Byte) Internal Capture
Copyright©1999-2000
RTD2000
4.1.5 Input Capture Window Inside RTD2000, there four registers IPH_ACT_STA, IPH_ACT_WID, IPV_ACT_STA IPV_ACT_LEN define input capture window selected input video either input port while programmed analog input mode. horizontal sync(IHS) vertical sync(IVS) signals used from selected port determine capture window region. Figure Input Capture Window
Vertical blanking region (back porch)
IPV_ACT_STA
IPV_ACT_LEN
Input Capture Window
Horizontal blanking region (back porch)
Horizontal blanking region (front porch)
Vertical blanking region (front porch)
IPH_ACT_STA IPH_ACT_WID
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RTD2000 Output
4.2.1 Display Output Timing display output port sends single/double pixel data transfer synchronized display timing external device. display port also support display panel with 6-bit color, turn dithering function enhance color depth. single pixel output mode, single pixel data (24-bit RGB) transferred display port each active edge DCLK, rate DCLK also equal display pixel clock. sync enable signals also sent display port each active edge DCLK. Seeing figure below double pixel output mode, double pixel data (48-bit RGB) transferred display port each active edge DCLK rate DCLK equal half display pixel clock this moment. sync enable signals also sent display port each active edge DCLK. Seeing figure below
Figure Single Pixel Mode Display Data Timing
DCLK DA/RGB DB/RGB
rgb0 rgb1 rgb2 rgb3 rgb4 rgb5
Figure Double Pixel Mode Display Data Timing
DHCLK DA/RGB DB/RGB
rgb0 rgb2 rgb4 rgb6 rgb8 rgb10
rgb1
rgb3
rgb5
rgb7
rgb9
rgb11
Copyright©1999-2000
RTD2000
4.2.2 Display Active Window These registers define display active window showed below application with frame buffer. case without frame buffer that means frame sync mode, definitions these registers quiet different from description below. There frame sync modes applied RTD2000 chip various applications. Refer register description detailed. Figure Display Active Window Diagram
DV_VS_END Vertical blanking region (back porch) DV_BKGD_STA Background Region DV_ACT_STA
Display Active Window
Horizontal blanking region (back porch) DV_ACT_END DV_BKGD_END Vertical blanking region (front porch) Horizontal blanking region (front porch)
DV_TOTAL DH_HS_END DH_BKGD_STA DH_ACT_STA DH_ACT_END DH_BKGD_END DH_TOTAL
Copyright©1999-2000
RTD2000 Brightness, Contrast Gamma Correction
Digital color independent channel contrast brightness controls built RTD2000. contrast control performed multiply value from 0/128, 1/128, 2/128. 255/128 each R/G/B channel. brightness control used offset value from -128 +127 also each R/G/B channel. Figure Brightness, contrast gamma correction block diagram
Scaled
Gamma Correction
Dithering
Contrast Brightness (-128 +127)
Color
4.4.1 Build-In detailed function-description build-in OSD, please refer application note RTD2000 embedded OSD. 4.4.2 Color Look-Up Table Overlay Port following diagram presents data flow among gamma correction, dithering, overlay MUX, output format conversion blocks. Figure color look-up table data path diagram
Gamma Correction
Dithering
Output Format Conversion
External Internal Background Color
24/48
16x24 color look-up table
CR38
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RTD2000 Auto-Adjustment
There main functions supported RTD2000, including auto-position auto-tracking. operation procedure following; 4.5.1 Auto-Position Define color noise margin: When value color channel greater than these noise margins, valid pixel found. Define measured line number HOR_START HOR_END parameters. Start auto-position function. Seeing figure below details. 4.5.2 Auto-Tracking After above procedure, then enter auto-tracking procedure phase fine tuning, follows; Setting value(phase zero) into register phase-adjust start auto-tracking function. Till finished this measurement, result that correspondence with Repeat routine until different phases were measured. Calculated pick best phase setting
Figure Display Timing Diagram
VER_START
LINE_SEL
VER_END
HOR_START HOR_END
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RTD2000 System
Inside RTD2000, there systems display clock memory clock, called that DCLK MCLK respectively. course, still force these clocks from external oscillators through pins REFCLK1 REFCLK2 your applications. Each provides wide range user-programmable frequency synthesis options, formula following; DCLK M_DCLK N_DCLK,
Meanwhile, 14.318MHz, M_DCLK[7:0] N_DCLK[5:0] 8-bit 6-bit value DCLK.
MCLK M_MCLK N_MCLK,
Meanwhile, 14.318MHz, M_MCLK[7:0] N_MCLK[5:0] 8-bit 6-bit value MCLK.
Figure System Control Diagram
Control Bit1
REFCLK1 Internal DCLK DCLK
Control Bit0
Control Bit3
REFCLK2 Internal MCLK MCLK
Control Bit2
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RTD2000 Host Interface
4.7.1 Host Interface Hardware transaction should start from asserted SCS# stop after de-asserted SCS#. Within this period, data driving clock rising edge latched clock falling edge. detailed timing diagrams following; Figure Serial Port Write Timing Data Format
Write Address Auto-Inc SCLK SCSB STOP
Address
Data0
Data1
Data2
Address: A0~A7 R/W: Read/Write Mode Data Phase, Write, Read INC: Address Auto-Increasing Mode, enable auto-increasing, disable
Figure Serial Port Read Timing
Read Non-Address Auto-Inc STOP
SCLK SCSB
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RTD2000 Registers Description:
Reading unimplemented registers will return
Address: Mode Address: Mode Default: Function bits 0001 product code, bits 0100 rev. code STATUS0 (Status0 Register) Default: Function Line Buffer Underflow status Line Buffer underflow occurred since last status read Input Overflow Status Input data capture buffer occurred overflow Input Vertical Sync Occurs input vertical sync edge occurs, this will Input Vertical Sync Occurs input vertical sync edge occurs, this will Input Error interlaced modes, signal should toggle every SYNC period does this "1", cleared after read Input HSYNC Changed input horizontal sync occurs within programmed active period this "1", cleared after read Input VSYNC Changed input vertical sync occurs within programmed active period this "1", cleared after read Default: Function Reset whole chip (Low pulse least 8ms) normal enable reset Power saving mode enable (except sync processor serial port) normal enable power saving mode IRQCTRL (IRQ Control Register) Default: Function IRQ0 Enable Disable this interrupt Enable this interrupt. Once enable, interrupt source enable will logical "OR" together. disable Line Buffer underflow event interrupt source enable Line Buffer underflow event interrupt source disable Input Buffer overflow event interrupt source enable Input Buffer overflow event interrupt source disable RGB(VGA) Input Sync event interrupt source enable RGB(VGA) Input Sync event interrupt source disable YUV(VGB) Input Sync event interrupt source enable YUV(VGB) Input Sync event interrupt source disable Input error event interrupt source enable Input error event interrupt source disable Input Format error event interrupt source enable Input Format error event interrupt source HOSTCTRL ID_REG
Address: Mode
Address: Mode
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RTD2000
Input Video Capture:
Capture Format
Address: VGIP_CTRL (Video Graphic Input Control Register) Default: Mode Function Input video enable, data transferred sampling input pixels Input graphic/video mode, from input.(input captured window size, enable tied high) from digital interface (captured enable signal, still stored capture window size) Input double pixel width enable single pixel double pixel Select either port single pixel transfers, single pixel input port single pixel input port Input video double pixel wide offset mode enable disable offset enable offset (latched data rising/falling edge respectively) Double Pixel Offset Mode Selection Offset Mode Offset Mode Capture Follow Image Freeze Function Disable (Motion Image) Enable triggers start stop latching) Address: VGIP_SIGINV (Input Control Signal Inverted Register) Default: Mode Function Input Port Clock Polarity rising edge latched falling edge latched Input Port Signal Polarity Inverted inverted (input high active) inverted (while input active) Input Port Signal Polarity Inverted inverted positive polarity) inverted negative polarity) Input Port Signal Polarity Inverted inverted positive polarity) inverted negative polarity) Input Video signal invert enable inverted (ODD positive polarity) inverted (ODD negative polarity) Input CSYNC (HS_RAW SOG) Inverted Enable Disable Enable
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RTD2000
Input Frame Window
Address: IPH_ACT_STAL (Input Horizontal Active Start Low) Mode Function Input Video Horizontal Active Start Byte [0:7] Address: IPH_ACT_STAH (Input Horizontal Active Start) Mode Function Input Video Horizontal Active Start High Byte [8:10] number pixel clocks from leading edge first pixel active line. Note: analog single double pixel mode (except offset mode), should fill number into these registers stead This capture starting address number also must times that's constraint. Address: IPH_ACT_WIDL (Input Horizontal Active Width Low) Mode Function Input Video Horizontal Active Width Byte [0:7] Address: IPH_ACT_WIDH (Input Horizontal Active Width High) Mode Function Input Video Horizontal Active Width High Byte [8:10] This register defines number active pixel clocks. (Horizontal Active Start Horizontal Active Width) 2047 This capture width number also must times four that's constraint. Address: IPV_ACT_STAL (Input Vertical Active Start Low) Mode Function Input Video Vertical Active Start Byte [0:7] Address: IPV_ACT_STAH (Input Vertical Active Start High) Mode Function Input Video Vertical Active Start High Byte [8:10] number lines from leading edge selected input video VSYNC first line active window Address: IPV_ACT_LENL (Input Vertical Active Lines) Mode Function Input Video Vertical Active Lines Byte [0:7] Address: IPV_ACT_LENH (Input Vertical Active Lines) Mode Function Input Video Vertical Active Lines High Byte [8:10] number active lines from start vertical active window.
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RTD2000
Scaling Function:
Address: SCALE_CTRL (Scale Control Register) Mode Function Enable Horizontal Filter Function pass horizontal filter function block Enable horizontal filter function block Enable Vertical Filter Function pass vertical filter function block Enable vertical filter function block Enable Horizontal Filter Sharpness Effect Disable Enable horizontal sharpness enhancement Enable Vertical Filter Sharpness Effect Disable Enable vertical sharpness enhancement Address: Address: HOR_SCA_L (Horizontal Scale Factor Low) Mode Function byte horizontal scale factor HOR_SCA_H (Horizontal Scale Factor High) Mode Function High byte horizontal scale factor Default:
Address: VER_SCA_L (Vertical Scale Factor Low) Mode Function byte vertical scale factor Address: VER_SCA_H (Vertical Scale Factor High) Mode Function High byte vertical scale factor This vertical horizontal scale factor includes 16-bit fraction part present vertical horizontal scaled size over stream input. example, 800-pixel original picture scales 1024-pixel, factor should fill (800 1024) 2^16 0.78125 2^16 51200 C800h C8h, 00h.
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RTD2000
Display Format:
Address: VDIS_CTRL (Video Display Control Register) Default: Mode Function Display video timing enable, Display Timing Generator halted, Zoom Filter halted Display Timing Generator Zoom Filter enabled normally Display output Enable DHS, DVS, DEN, DCLK data clamped Display output normal operation. Display Video Output Pixel Double Width Enable, Single width pixels output display with every DCLK cycle Double width pixels output display with every DHCLK cycle Frame Sync Mode Enable Free running mode Frame sync mode Display Mode Enable, individual output pixels full 24-bit individual output pixels rounded 18-bit Display Output Force Background Color Display output operates normally Zoom Filter output forced color selected background color Frame Sync Mode Select Frame Sync Mode Frame Sync Mode Output Format Select (only available Frame Sync Mode Disable output while inactive Enable output while inactive Address: VDIS_SIGINV (Display Control Signal Inverted) Default: Mode Function Display Clock Invert Enable Display output clock (DCLK) normal Display output clock inverted Display Data Enable (DEN) Output Invert Enable Display Data Enable output normal active high logic Display Data Enable output inverted logic Display Horizontal Sync (DHS) Output Invert Enable Display Horizontal Sync output normal active high logic Display Horizontal Sync output inverted logic Display Vertical Sync (DVS) Output Invert Enable Display Vertical Sync output normal active high logic Display Vertical Sync output inverted logic Background color select [0:3] Select color from look-up-table
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RTD2000
Address: DH_TOTAL (Display Horizontal Total Pixels) Mode Function Display Horizontal Total Pixel Clocks Byte[0:7] Address: DH_TOTAL (Display Horizontal Total Pixels) Mode Function Display Horizontal Total Pixel Clocks High Byte[8:10] Determines number DCLK cycles each display line (DHS leading edge leading edge) Address: DH_HS_END (Display Horizontal Sync End) Mode Function Display Horizontal Sync Determines width pulse DCLK cycles Address: DH_BKGD_STA (Display Horizontal Background Start) Mode Function Display Horizontal Background Start Byte[0:7] Address: DH_BKGD_STA (Display Horizontal Background Start) Mode Function Display Horizontal Background Start High Byte[8:10] Determines number DCLK cycles from leading edge first pixel Background region. Address: DH_ACT_STA (Display Horizontal Active Start) Mode Function Display Horizontal Active Region Start Byte[0:7] Address: DH_ACT_STA (Display Horizontal Active Start) Mode Function Display Horizontal Active Region Start High Byte[8:10] Determines number DCLK cycles from leading edge first pixel Active region. Address: DH_ACT_END (Display Horizontal Active End) Mode Function Display Horizontal Active Width Byte[0:7] Address: DH_ACT_END (Display Horizontal Active End) Mode Function Display Horizontal Active Width High Byte[8:10] Determines number DCLK cycles from leading edge pixel background region. Address: DH_BKGD_END (Display Horizontal Background End) Mode Function Display Horizontal Background Byte[0:7] Address: DH_BKGD_END (Display Horizontal Background End) Mode Function Display Horizontal Background High Byte[8:10] Determines number DCLK cycles from leading edge pixel start horizontal blanking.
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RTD2000
Address: DV_TOTAL (Display Vertical Total Lines) Mode Function Display Vertical Total Byte[0:7] Address: DV_TOTAL (Display Vertical Total Lines) Mode Function Display Vertical Total High Byte[8:10] Determines number lines each frame (DVS leading edge leading edge) When switched into frame sync mode this register [0:7] represents number count [0:7] between input output input While frame sync mode this register [0:7] means delay count from leading edge DVS. Address: DV_VS_END (Display Vertical Sync End) Mode Function Display Vertical Sync Determines duration pulse lines Address: DV_BKGD_STA (Display Vertical Background Start) Mode Function Display Vertical Background Start Byte[0:7] Address: DV_BKGD_STA (Display Vertical Background Start) Mode Function Display Vertical Background Start High Byte[8:10] Determines number lines from leading edge first line background region. While frame sync mode ignored this register. Address: DV_ACT_STA (Display Vertical Active Start) Mode Function Display Vertical Active Region Start Byte[0:7] Address: DV_ACT_STA (Display Vertical Active Start) Mode Function Display Vertical Active Region Start High Byte[8:10] Determines number lines from leading edge first line active region. While frame sync mode ignored this register. Address: DV_ACT_END (Display Vertical Active End) Mode Function Display Vertical Active Region Byte[0:7] Address: DV_ACT_END (Display Vertical Active End) Mode Function Display Vertical Active Region High Byte[8:10] Determines number lines from leading edge line follow background region. While frame sync mode this register expresses length output active region DHS. Address: DV_BKGD_END (Display Vertical Background End) Mode Function Display Vertical Background Byte[0:7] Address: DV_BKGD_END (Display Vertical Background End) Mode Function Display Vertical Background High Byte[8:10] Determines number lines from leading edge line start vertical blanking. While frame sync mode ignored this register. Note: display timing values above must satisfied with even number constraint.
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RTD2000
RGB/YUV Mode Control:
Address: Mode MEMCTRL0 (Memory Control Register) Function Enable Conversion Disable YVB-to-RGB conversion Enable YUV-to-RGB conversion YUV-to-RGB Conversion Mode Selection YUV422 YUV444 Input Vertical-Interlace Mode Enable Non-interlace mode Vertical-Interlace mode (Odd/Even De-Interlace) Default:
Address: DIS_TIMING (Display Clock Fine Tuning Register) Default: Mode Function Display Output Clock Fine Tuning Control 000: DCLK rising edge correspondents with output display data 001: advanced 010: advanced 011: delay 100: delay Display Output Clock/2 Force (Test Mode) normal divided (Forced) External Port Latch Clock Delay normal delay Force Display Timing Generator Enable wait input trigger force enable Output Format Select (only available Frame Sync Mode Inhibit output while falling edge occurred Continue output
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RTD2000
Phase Lock Loop:
Address: PLLCTRL (Internal Control Register) Default: Mode Function DCLK output enable inhibit DCLK output; enable DCLK output MCLK output enable inhibit MCLK output; enable MCLK output DCLK Output Select Select internal clock source DCLK output Select external REFCLK1 clock source DCLK output Select internal clock source DCLK REFCLK1 output reserved MCLK Output Select Select internal clock source MCLK output Select external REFCLK2 clock source MCLK output Select internal clock source MCLK REFCLK2 output reserved Address: DCLK_M1 Parameter Register) Default: Mode Function value Address: DCLK_N1 Parameter Register) Default: Mode Function value Write into this while DCLK output over 100MHz DCLK-PLL Test Mode forced DCLK divided F_dclk F_in meanwhile, F_in 14.318MHz. default value DCLK block M1=92h N1=20h; 14.318 65.32Mhz. Write register will issue frequency change command DCLK block. Address: MCLK_M2 Parameter Register) Default: Mode Function value Address: MCLK_N2 Parameter Register) Default: Mode Function value Write into this while MCLK output over 100MHz MCLK-PLL Test Mode forced MCLK divided F_mclk F_in meanwhile, F_in 14.318MHz. default value MCLK block M2=BEh N2=20h; 14.318 85.01Mhz. Write register will issue frequency change command MCLK block.
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RTD2000
SYNC Processor:
Address: SYNC_CTRL (SYNC Control Register) Default: Mode Function Sync Mode Select Separate Composite Sync from HSYNC Green Sync-On-Green Enable Disable; Enable (set Sync-Mode-Select same time) CLAMP Signal Output Enable Disable; Enable CLAMP Signal Invert Enable inverted inverted HS_OUT Signal Output Enable disable; enable; HS_OUT Signal Invert Enable inverted inverted COAST Signal Output Enable disable; enable; COAST Signal Invert Enable inverted inverted Address: SYNC_POR SYNC Polarity Measured Result) Default: Mode Function HSYNC VSYNC measured mode period counted memory clock period counted resolution counted input clock resolution counted (get correct resolution which triggered enable signal, ENA) Start period resolution polarity measurement disable start measurement enable start measurement, cleared after finished Input HSYNC Polarity Indicator negative polarity (high period longer than one) positive polarity (low period longer than high one) Input VSYNC Polarity Indicator negative polarity (high period longer than one) positive polarity (low period longer than high one)
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RTD2000
Address: MEAS_HS_PER (HSYNC Period Measured Result) Mode Function Input HSYNC Period Measurement Result -Low Byte[0:7] Address: MEAS_HS_PER (HSYNC Period Measured Result) Mode Function Input HSYNC Period Measurement Result High Byte[8:11] Input HSYNC Period Measurement Result Over-flow over-flow occurred This result expressed terms memory clocks divided Address: MEAS_VS_PER (VSYNC Period Measured Result) Mode Function Input VSYNC Period Measurement Result Byte[0:7] Address: MEAS_VS_PER (VSYNC Period Measured Result) Mode Function Input VSYNC Period Measurement Result High Byte[8:10] Input HSYNC Period Measurement Result Over-flow over-flow occurred This result expressed terms input pulses Address: MEAS_HS_HI (HSYNC High Period Measured Result) Mode Function Input HSYNC Period Measurement Result -Low Byte[0:7] Address: MEAS_HS_HI (HSYNC High Period Measured Result) Mode Function Input HSYNC Period Measurement Result High Byte[8:11] This result expressed terms memory clocks divided Address: MEAS_VS_HI (VSYNC High Period Measured Result) Mode Function Input VSYNC Period Measurement Result Byte[0:7] Address: MEAS_VS_HI (VSYNC High Period Measured Result) Mode Function Input VSYNC Period Measurement Result High Byte[8:10] This result expressed terms input pulses
Clamping Signal Control:
Address: CLAMP_START (Clamp Signal Output Start) Mode Function Start Output Clamp Signal Pulse Determine number input double-pixel between front edge input HSYNC start output CLAMP signal. Address: CLAMP_END (Clamp Signal Output End) Mode Function Output Clamp Signal Pulse Determine number input double-pixel between front edge input HSYNC output CLAMP signal.
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RTD2000
Color Processor Control:
Address: COLOR_CTRL (Color Control Register) Default: Mode Function Enable Brightness Control Coefficient disable coefficient enable coefficient Enable Contrast Control Coefficient disable coefficient enable coefficient Enable Look-Up Table Gamma Correction Coefficient disable look-up table enable look-up table coefficient Enable Dithering Function disable dithering function enable dithering function Enable Access Channels Gamma Correction Coefficient disable these channels enable these channels (address should auto increase) Enable Access Channel Dithering Table disable this channel enable this channel (address should auto increase)
Brightness Coefficient:
Address: BRI_R_COE (Brightness Coefficient) Mode Function Brightness Coefficient Valid range: -128(00h) 0(80h) +127(FFh) Address: BRI_G_COE (Brightness Green Coefficient) Mode Function Brightness Green Coefficient Valid range: -128(00h) 0(80h) +127(FFh) Address: BRI_B_COE (Brightness Blue Coefficient) Mode Function Brightness Blue Coefficient Valid range: -128(00h) 0(80h) +127(FFh)
Contrast Coefficient:
Address: CTS_R_COE (Contrast Coefficient) Mode Function Contrast Coefficient Valid range: 0(00h) 1(80h) 2(FFh) Address: CTS_G_COE (Contrast Green Coefficient) Mode Function Contrast Green Coefficient Valid range: 0(00h) 1(80h) 2(FFh) Address: CTS_B_COE (Contrast Blue Coefficient) Mode Function Contrast Blue Coefficient Valid range: 0(00h) 1(80h) 2(FFh)
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RTD2000
Gamma Correction:
Address: RED_GAMMA_PORT (Red Gamma Table Access Port) Mode Function Access port gamma correction table Address: GRN_GAMMA_PORT (Green Gamma Table Access Port) Mode Function Access port green gamma correction table Address: BLU_GAMMA_PORT (Blue Gamma Table Access Port) Mode Function Access port blue gamma correction table When enable gamma correction table accessing, total size coefficient table bytes each color respectively. input data sequence c255.
Dithering Coefficient:
Address: DITHER_PORT (Dithering Table Access Port) Mode Function Access port dithering table When enable dithering table accessing, total size coefficient table bits color. input data sequence {c1, c0}, {c3, {c15, c14}.
Cyclic-Redundant-Check:
Address: OP_CRC_CTRL (Output Control Register) Default: Mode Function Output Control Stop finish (Auto-stop after checked completed display frame) Start Address: OP_CRC_BYTE_0 (Output Checksum Byte Mode Function Output CRC-24 Address: _CRC_BYTE_1 (Output Checksum Byte Mode Function Output CRC-24 8~15 Address: _CRC_BYTE_2 (Output Checksum Byte Mode Function Output CRC-24 16~23
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RTD2000
Overlay Control:
Address: OVL_CTRL (Overlay Display Control Register) Mode Function Overlay Port Enable Disable Enable Internal/External Select Internal External Sampling Mode Select dual pixels clock single pixel clock Enable Overlay Color Plate Access Disable Enable Overlay OVCLK Output Inverted Enable Disable Enable Overlay OV_VS Output Inverted Enable Disable Enable Overlay OV_HS Output Inverted Enable Disable Enable Default:
Address: OVL_LUT_ADDR (Overlay Address) Mode Function Overlay 16x24 Look-Up-Table Write Address [0:5] Auto-increment while every accessing "Overlay Access Port".
Default:
Address: OVL_LUT_PORT (Overlay Access Port) Mode Function Overlay 16x24 Look-Up-Table access port [0:7] Using this port access overlay color plate which addressing above register. writing sequence into {R0, B1,. R15, G15, B15} address counter will automatic increment circular from
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RTD2000
Image Boundary Search Auto-Phase Tracking:
Address: AUTO-ADJ_CTRL (Auto adjustment control register Mode Function Start Boundary Search Function stop finished start Start Auto-Phase Tracking Function stop finished start Auto-Phase Tracking Configuration Selection Blue color phase measurement. Green color phase measurement. color phase measurement. Boundary Search Mode Selection single pixel over threshold. continued pixels over threshold. Auto-Phase Bit-Mask Selection 000: mask. 001: Mask Bit-0; 111: Mask Bit-0 Bit-6. Address: RED_NOISE_MARGIN (Red Noise Margin Register) Mode Function pixel noise margin setting register Address: GRN_NOISE_MARGIN (Green Noise Margin Register) Mode Function Green pixel noise margin setting register Address: BLU_NOISE_MARGIN (Blue Noise Margin Register) Mode Function Blue pixel noise margin setting register Address: LINE_SEL_L active measure line selection Register) Mode Function Horizontal active region measured line selection bit[0:7] Address: LINE_SEL_H active measure line selection Register) Mode Function Horizontal active region measured line selection bit[8:10] Address: VER_START_L (Active region vertical start Register) Mode Function Active region vertical start measurement result bit[0:7] Address: VER_START_H (Active region vertical start Register) Mode Function Active region vertical start measurement result bit[8:10] Address: VER_END_L (Active region vertical Register) Mode Function Active region vertical measurement result bit[0:7] Address: VER_END_H (Active region vertical Register) Mode Function Active region vertical measurement result bit[8:10] Default:
Copyright©1999-2000
RTD2000
Address: HOR_START_L (Active region horizontal start Register) Mode Function Active region horizontal start measurement result bit[0:7] Address: HOR_START_H (Active region horizontal start Register) Mode Function Active region horizontal start measurement result bit[8:10] Address: HOR_END_L (Active region horizontal Register) Mode Function Active region horizontal measurement result bit[0:7] Address: HOR_END_H (Active region horizontal Register) Mode Function Active region horizontal measurement result bit[8:10] Address: AUTO_PHASE_0 (Auto phase result byte0 register) Mode Function Auto phase measurement result byte0 bit[0:7] Address: AUTO_PHASE_1 (Auto phase result byte1 register) Mode Function Auto phase measurement result byte1 bit[8:15] Address: AUTO_PHASE_2 (Auto phase result byte2 register) Mode Function Auto phase measurement result byte2 bit[23:16] Address: AUTO_PHASE_3 (Auto phase result byte3 register) Mode Function Auto phase measurement result byte3 bit[28:24]
Embedded OSD:
Address: OSD_ROW_ADDR (OSD Address) Mode Function Address embedded access Address: OSD_COL_ADDR (OSD Column Address) Mode Function Column Address embedded access Address: OSD_DATA_PORT (OSD Data Port) Mode Function Data port embedded access Refer RTD2000 embedded application note detailed.
Copyright©1999-2000
RTD2000 Electrical Specification:
Characteristics
Absolute Maximum Ratings
Rating Voltage Voltage Input, Pins Operating Temperature, (ambient) Storage temperature (plastic) Power Dissipation Value Unit
Electrical Characteristics Operating Condition
(0<TA<70; 3.3V 0.3V) Symbol Parameter Supply Voltage Output High Voltage Output Voltage Input High Voltage Input Voltage Pull-up resistance Pull-down resistance Input Leakage Current Output Leakage Current Unit Conditions IOH=-1.0mA IOL=2.0mA
VI=VCC VO=VCC
Copyright©1999-2000
RTD2000
Characteristics Input Signal
Figure Input Signal Timing
ICLK
TIPDS TIPDH
Data Port
ICLK
TIPCS TIPCH
Control Signals
Symbol TIPCS TIPCH TIPDS TIPDH
Parameter Input control signals setup time ICLK Input control signals hold time ICLK Input data setup time ICLK Input data hold time ICLK
Unit
Copyright©1999-2000
RTD2000
Output Signal
Figure Output Signal Timing
DCLK
TOPDS TOPDH
Data Port
DCLK
TOPCS TOPCH
Control Signals
Symbol TOPCS TOPCH TOPDS TOPDH
Parameter Output control signals setup time DCLK Output control signals hold time DCLK Output data setup time DCLK Output data hold time DCLK
Unit
Copyright©1999-2000
RTD2000
Serial Port Signal
Figure Serial Port Signal Timing
SCLK
TSPIS TSPIH
SCLK
TSPOS TSPOH
Symbol TSPIS TSPIH TSPOS TSPOH
Parameter Serial port input signal setup time SCLK Serial port input signal hold time SCLK Serial port output signal setup time SCLK Serial port output signal SCLK
Unit
Copyright©1999-2000
RTD2000
Tcycle
3.3V 2.8V
DCLK
1.65V 0.8V
Electrical Characteristics
Characteristics Output rise time (20pf Load) Output fall time (20pf Load) Duty cycle (20pf Load, 1.5V) Clock Skew (20pf Load, 1.5V) Jitter, Absolute (20pf Load) Symbol Tduty Tskw1 Conditions From 0.8V 2.0V,Vdd=3.3V From 2.0V 0.8V,Vdd=3.3V DCLK DCLK DCLK DCLK Type Unit
Copyright©1999-2000
RTD2000 Mechanical Specification:
Copyright©1999-2000
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