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April 1999
Features
Description
Generates clocks required Intel Pentium based systems, including: Four enabled 2.5V 100MHz 66MHz system clock outputs Seven enabled 3.3V clocks free-running clock Three 3.3V clocks 14.318MHz 2.5V APIC clocks 14.318MHz APIC timing 3.3V 48MHz clocks Universal Serial (USB) timing
FS6251-01 CMOS clock generator designed high-speed motherboard applications. different frequencies selected clocks pins. Glitch-free stop clock control clocks provided. current powerdown mode available mobile applications. Separate clock buffers provide 2.5V voltage range CPU_0:3 APIC_0:1 clocks.
Figure Configuration (FS6251)
CPU_STOP# PCI_STOP# PWR_DWN#
(2.5V outputs)
(reserved) APIC_0 APIC_1 VDD_R VDD_C VDD_C VDD_A VSS_C CPU_0 CPU_1 CPU_2 CPU_3 VSS_A REF_2 VSS_C
SS_EN#
SEL_0
Non-linear spread spectrum modulation (-0.5% 31.5kHz) Selectable 100MHz 66MHz system clock Supports Intel Test Mode tristate output control facilitate board testing
SEL_1 48M_1
FS6251-01
REF_0
REF_1
VSS_R
48M_0
Separate CPU-enable, PCI-enable power-down inputs with glitch-free stop clock controls clocks clock control power management inputs 3.3V outputs LVTTL-compatible
48-pin SSOP
Figure Configuration (FS6252)
CPU_STOP# PCI_STOP#
(2.5V outputs)
VDD_R VDD_C VSS_R VSS_C CPU_0 CPU_1 REF_2
Figure Block Diagram (FS6251)
VDD_R
Crystal Oscillator XOUT CPU_STOP#
REF_0:2
VSS_R VDD_A
FS6252-01
PCI_2
PCI_3
PCI_4
PCI_1
PCI_5
VSS_P
VDD_P
VSS_A VDD_C
CPU_0:3 SEL_0:1
VSS_C
28-pin SSOP, SOIC
(2.5V outputs)
VDD_P
Table CPU/PCI Frequency Selection
SEL_100/66# SEL_1 SEL_0 (MHz) tristate 73.33 66.67 XIN/2 (MHz) tristate 36.67 33.33 XIN/6 36.67 33.33
SEL_100/66# PCI_STOP# SS_EN# PWR_DWN#
delay
PCI_F PCI_1:7
VSS_P VDD_U
48M_0:1
VSS_U
FS6251-01
Intel Pentium registered trademarks Intel Corporation. Lexmark trademark Lexmark International, Inc. Spread spectrum modulation licensed under Patent 5488627, Lexmark International, Inc. American Microsystems, Inc. reserves right change detail specifications required permit improvements design products.
VDD_P
VSS_P
PCI_F
XOUT
APIC_0:1
SEL_100/66#
PWR_DWN#
VDD_U
VDD_P
VDD_P
VSS_U
VSS_P
VSS_P
VSS_P
PCI_F
XOUT
Synchronous clocks skew-matched <175ps APIC buffers <250ps buffers
PCI_2
PCI_3
PCI_4
PCI_5
PCI_6
PCI_1
PCI_7
SEL_100/66#
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Table Descriptions
Key: Analog Input; Analog Output; Digital Input; Input with Internal Pull-Up; Input with Internal Pull-Down; Digital Input/Output; DI-3 Three-Level Digital Input, Digital Output; Power/Ground; Active-low
(FS6251)
(FS6252)
TYPE
NAME 48M_0:1 CPU_0:3 CPU_STOP# APIC_0:1 PCI_1:7 PCI_F PCI_STOP# PWR_DWN# REF_0:2 SEL_0:1 SEL_100/66# SS_EN# VDD_A VDD_C VDD_P VDD_R VDD_U VSS_A VSS_C VSS_P VSS_R VSS_U XOUT (reserved)
DESCRIPTION 48MHz clock outputs Universal Serial (USB) timing Four low-skew (<175ps 1.25V) 2.5V 3.3V clock outputs host frequencies. (Two copies clock available FS6252 version) CPU_0:3 clock output enable. Asynchronous, active-low disable stops clocks state. buffered low-skew (<175ps 1.25V) 2.5V/3.3V outputs 14.318MHz reference clock APIC timing Seven low-skew (<250ps 1.5V) 3.3V clock outputs. clocks synchronous with clocks clocks 4ns. (Four copies clock available FS6252 version) free-running 3.3V clock output. PCI_1:7 clock output enable. Asynchronous, active-low disable stops clocks state. Asynchronous active-low power-down signal shuts down oscillator, PLLs, puts clocks state. Clock re-enable latency 3ms. Three buffered outputs 14.318MHz reference clock. (One copy reference clock available FS6252 version) frequency select inputs (Both pins tied together FS6252 version) Selects 100MHz 66MHz clock frequency (pull-up/pull-down must provided externally) Spread spectrum enable. Active-low enable turns spread spectrum feature; logic-high turns spread spectrum modulation. 3.3V Power supply 2.5V APIC_0:1 clock outputs Power supply 2.5V CPU_0:3 clock outputs Power supply 3.3V PCI_1:7 PCI_F clock outputs Power supply 3.3V REF_0:2 clock outputs Power supply 3.3V 48M_0:1 clock outputs Ground Ground APIC_0:1 clock outputs Ground CPU_0:3 clock outputs Ground PCI_1:7 PCI_F clock outputs Ground REF_0:2 clock outputs Ground 48M_0:1 clock outputs 14.318MHz crystal oscillator feedback 14.318MHz crystal oscillator drive reserved
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Table Actual Clock Frequencies
Note: Spread spectrum disabled
CLOCK CPU_0:3 PCI_1:7, PCI_F 48M_0:1 TARGET (MHz) 100.00 66.67 33.33 (with 100) 33.33 (with 66.67) 48.00 ACTUAL (MHz) 99.9963 66.6536 33.3321 33.3268 48.0080 DEVIATION (ppm) -196 -196 +167
48MHz clock required 167ppm from 48.000MHz conform requirements.
Programming Information
Table Function/Clock Enable Configuration
CONTROL INPUTS SEL_ 100/66# SEL_1 SEL_0 PWR_ DWN# SEL_0:1 SEL_100/66# CPU_ STOP# PCI_ STOP# REF_0:2 tristate 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 CPU_0:3 tristate 73.33 66.67 XIN÷2 running running CLOCK OUTPUTS (MHz) PCI_F tristate 36.67 33.33 XIN÷6 36.67 33.33 running running running running PCI_1:7 tristate 36.67 33.33 XIN÷6 36.67 33.33 running running APIC_ tristate 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318 48M_0:1 tristate XIN÷2
Frequency Selection
Output frequencies selected three pins: SEL_100/66#, SEL_1 SEL_0. three pins should fixed logic state before power-up occurs. Table provides guide operation.
66MHz 100MHz, depending state SEL_100/66# pin. Both overclocking frequencies available system testing. Both pins bonded together FS6252 pin.
3.1.1 SEL_1, SEL_0 Pins These pins either tristate output drivers, select Test Mode frequency, choose frequencies. Both SEL_1 SEL_0 pins have pullups that default output frequency either
3.1.2 SEL_100/66# This active-low LVTTL input that switches between 100MHz 66MHz system (CPU) clock. pullup pull-down must provided externally.
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Stop Clock Control
Clock Latency
Three pins control clock outputs: CPU_STOP#, PCI_STOP# PWR_DWN#.
3.2.1 CPU-Enable, PCI-Enable CPU_STOP# active-low LVTTL input that disables CPU_0:3 clocks power operation. CPU_STOP# asserted asynchronously, stop clock control glitch-free, that clock must complete full cycle before clock stopped low. PCI_STOP# active-low LVTTL input that disables PCI_1:7 clocks power operation, except PCI_F clock. PCI_F free-running clock, will continue even other clocks have stopped. PCI_STOP# asserted asynchronously, stop-clock control glitch-free, that clock must complete full cycle before clock stopped low. 3.2.2 Power Down PWR_DWN# signal asynchronous, active-low LVTTL input that puts device power inactive state without removing power from device. internal clocks turned off, clock outputs held low. Powering down occurs less than clocks from falling edge PWR_DWN# when clock outputs forced low.
clock outputs stopped state, started that first high pulse full pulse width. clocks complete full period transitions between running (enabled) stopped (disabled) ensure glitchfree stop clock control. enabled clocks will continue while disabled clocks stopped. clock enable signals assumed asynchronous inputs relative clock outputs. Enable signals synchronized their respective clocks this device. clocks will transition between running stopped according Table
Power-Up Latency
Power-up latency defined time from moment when PWR_DWN# goes inactive rising edge) when first valid clocks driven from device. Upon release PWR_DWN#, external circuitry should allow minimum PLLs lock before enabling clocks.
Clock Enable Latency
Clock enable latency defined number rising edges free-running clocks between when enable signal becomes active rising edge) when first valid clock driven from device.
Figure CPU_STOP# Timing
clock (internal) clock (internal) CPU_STOP# CPU_0:3
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Figure PCI_STOP# Timing
clock (internal) clock (internal) PCI_STOP# PCI_1:7
Figure PWR_DWN# Timing
clock (internal) clock (internal) PWR_DWN# CPU_0:3 PCI_1:7 Crystal Oscillator
Shaded regions Crystal Oscillator waveforms indicate that clock valid Crystal Oscillator active.
Table Latency Table
SIGNAL SIGNAL STATE CLOCK ENABLE LATENCY (Number rising edges clock) MIN. CPU_STOP# disabled enabled disabled enabled Power Power MAX. (max.) CLOCK ENABLE LATENCY (Number rising edges clock)
PCI_STOP#
PWR_DWN#
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Spread Spectrum Modulation
Modulation Frequency
limit peak emissions, high-speed motherboard designs require reduction peak harmonic energy contained system frequencies. reduction peak energy specific frequency accomplished spreading energy over limited range frequencies through technique known spread spectrum clocking. this technique, generated clock frequency dithered tightly controlled sweep near clock frequency using predetermined modulation profile period.
frequency modulation, noted describes fast center frequency sweeps between fnom, (1-) fnom,. Typical modulation frequencies must greater than 30kHz (above audio band) small enough upset system timing. Since tracking cannot instantaneously update output clock match modulated input clock, accumulation difference phase between modulated input clock tracking output clock called tracking skew. resulting phase error will decrease timing margins successive circuitry.
Figure Spectral Energy Distribution
spreadspectrum clock
Modulation Profile
(1-)fnom
non-spread clock
fnom
amount reduction directly related three parameters: modulation percentage, frequency modulation, modulation profile.
Modulation Percentage
modulation profile determines shape spectral energy distribution defining time that clock spends specific frequency. longer clock remains specific frequency, larger energy concentration that frequency. sinusoidal modulation spends large portion time between fnom, (1-) fnom, resulting large energy peaks edges spectral energy distribution. linear modulation, such triangle profile, improves spectral distribution also exhibits energy peaking edges. non-linear modulation profile, known "Hershey Kiss" profile patented Lexmark International, Inc., offers best distribution spectral energy.
modulation percentage typically 0.5% center frequency (denoted here fnom). modulation percentage determines range frequencies spectral energy distributed over. 100MHz clock frequency, ±0.5% modulation sweeps clock frequency between 99.5MHz 100.5MHz. sweep symmetrical around center frequency, technique known center-spread modulation. However, circuit that designed 100MHz reference have enough timing margin support clock greater then 100MHz. clock frequency instead modulated between fnom, (1-) fnom,; technique known down-spread modulation. -0.5%, clock will sweep between 99.5MHz 100MHz. small degradation circuit performance noticed, clock frequency averages 99.75MHz.
Figure Modulation Profiles
fnom fnom
time
time
(1-)fnom
1/fm
(1-)fnom
1/fm
type modulation profile used will also impact tracking skew. maximum frequency change occurs profile limits where modulation changes slew rate polarity. track sudden reversal clock frequency, downstream must have large loop bandwidth.
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April 1999 Compared profile limits modulation slew rate relatively slow between limits, allowing downstream chance reduce tracking skew. ability downstream catch determined loop transfer function phase angle. Spread spectrum clocking shown have negligible effect cycle-to-cycle jitter performance. increase jitter less than when fm<50kHz. Careful design downstream PLLs ensure that tracking skew minimized. have less than 100ps tracking skew, downstream should have loop bandwidth greater than 1MHz, phase angle less than 0.1°. Figure shows tracking skew downstream with loop bandwidth 1.5MHz phase angle 0.26° following non-linear profile-modulated 100MHz input clock with =-0.5% fm=31.2kHz.
Figure Tracking Skew
Tracking Skew
Skew [ps]
Time [us]
Spread Spectrum Enable
active-low LVTTL SS_EN# input enables spread spectrum modulation clocks. When SS_EN# logic-high, spread spectrum modulation these clocks disabled. SS_EN# logic-low, spread spectrum modulation enabled. pull-up this disables spread spectrum modulation default.
Figure Actual Modulation Profile
99.9
Frequency (MHz)
99.8
99.7
99.6
99.5
1/fm (µs)
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Electrical Specifications
Table Absolute Maximum Ratings
Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. These conditions represent stress rating only, functional operation device these other conditions above operational limits noted this specification implied. Exposure maximum rating conditions extended conditions affect device performance, functionality, reliability.
PARAMETER Supply Voltage (VSS ground) Input Voltage, Output Voltage, Input Clamp Current, VDD) Output Clamp Current, VDD) Storage Temperature Range (non-condensing) Ambient Temperature Range, Under Bias Junction Temperature Lead Temperature (soldering, 10s) Input Static Discharge Voltage Protection (MIL-STD 883E, method 3015.7)
SYMBOL
MIN. VSS-0.5 VSS-0.5 VSS-0.5
MAX. VDD+0.5 VDD+0.5
UNITS
CAUTION: ELECTROSTATIC SENSITIVE DEVICE
Permanent damage resulting loss functionality performance occur this device subjected high-energy electrostatic discharge.
Table Operating Conditions
PARAMETER SYMBOL CONDITIONS/DESCRIPTION
Core (VDD) 3.3V
MIN. 3.135 3.135 2.375 14.316
TYP. 14.318
MAX. 3.465 3.465 2.625 14.32 22.5
UNITS
Supply Voltage Operating Temperature Range Crystal Resonator Frequency Crystal Resonator Load Capacitance
fXTAL
Clock Buffers (VDD_P, VDD_R, VDD_U) 3.3V Clock Buffers (VDD_A,, VDD_C) 2.5V
XIN, XOUT pins 48M_0:1 APIC_0:1
13.5
Load Capacitance
CPU_0:3 PCI_F, PCI_1:7 REF_0:2
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Table Electrical Specifications
Unless otherwise stated, power supplies 3.3V 10%, load output, ambient temperature range 70°C. Parameters denoted with asterisk represent nominal characterization data currently production tested specific limits. characterization data from typical. Negative currents indicate current flows device.
PARAMETER Overall
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
UNITS
fCPU 100MHz; VDD_A VDD_C 3.465V
Supply Current, Dynamic, with Loaded Outputs
fCPU 100MHz; VDD_A VDD_C 2.625V fCPU 66.67MHz; VDD_A VDD_C 3.465V fCPU 66.67MHz; VDD_A VDD_C 2.625V
Supply Current, Static
IDDs
PWR_DWN# low; VDD_A VDD_C 3.465V PWR_DWN# low; VDD_A VDD_C 2.625V
Digital Inputs (CPU_STOP#, PCI_STOP#, PWR_DWN#, SEL_0:1, SS_EN#) High-Level Input Voltage Low-Level Input Voltage High-Level Input Current Low-Level Input Current (pull-up) Digital Input (SEL_100/66#) High-Level Input Voltage Low-Level Input Voltage Input Leakage Current Crystal Oscillator Feedback (XIN) Threshold Bias Voltage High-Level Input Current Low-Level Input Current Crystal Loading Capacitance Input Loading Capacitance Crystal Oscillator Drive (XOUT) High Level Output Source Current Level Output Sink Current 3.3V -3.0 CL(xtal) CL(XIN) 3.3V
seen external crystal connected XOUT seen external clock driver XOUT; unconnected
0.4V
VSS-0.3
VDD+0.3
VSS-0.3
VDD+0.3
1.49
13.5
22.5
CPU_0:3 Clock Outputs (2.5V Type Clock Buffer) High Level Output Source Current Level Output Sink Current Output Impedance Tristate Output Current Short Circuit Output Source Current Short Circuit Output Sink Current ISCH ISCL shorted 30s, max. 2.5V; shorted 30s, max. VDD_C 2.375V, 1.0V VDD_C 2.625V, 2.375V VDD_C 2.375V, 1.2V VDD_C 2.625V, 0.3V Measured 1.25V, output driving Measured 1.25V, output driving high 13.5 13.5
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Table Electrical Specifications, continued
Unless otherwise stated, power supplies 3.3V 10%, load output, ambient temperature range 70°C. Parameters denoted with asterisk represent nominal characterization data currently production tested specific limits. characterization data from typical. Negative currents indicate current flows device.
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
UNITS
APIC_0:1 Clock Output (2.5V Type Clock Buffer) High-Level Output Source Current Low-Level Output Sink Current Output Impedance Tristate Output Current Short Circuit Output Source Current Short Circuit Output Sink Current IOSH IOSL shorted 30s, max. 2.5V; shorted 30s, max. VDD_A 2.375V, 1.4V VDD_A 2.625V, 2.5V VDD_A 2.375V, 1.0V VDD_A 2.625V, 0.2V Measured 1.25V, output driving Measured 1.25V, output driving high
REF_0:2, 48M_0:1 Clock Outputs (3.3V Type Clock Buffer) High-Level Output Source Current Low-Level Output Sink Current Output Impedance Tristate Output Current Short Circuit Output Source Current Short Circuit Output Sink Current IOSH IOSL shorted 30s, max. 3.3V; shorted 30s, max. VDD_R, VDD_U 3.135V, 1.0V VDD_R, VDD_U 3.465V, 3.135V VDD_R, VDD_U 3.135V, 1.95V VDD_R, VDD_U 3.465V, 0.4V Measured 1.65V, output driving Measured 1.65V, output driving high
PCI_1:7, PCI_F Clock Outputs (3.3V Type Clock Buffer) High Level Output Source Current Level Output Sink Current Output Impedance Tristate Output Current Short Circuit Output Source Current Short Circuit Output Sink Current IOSH IOSL shorted 30s, max. 3.3V; shorted 30s, max. VDD_P 3.135V, 1.0V VDD_P 3.465V, 3.135V VDD_P 3.135V, 1.95V VDD_P 3.465V, 0.4V Measured 1.65V, output driving Measured 1.65V, output driving high
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Table Timing Specifications
Unless otherwise stated, power supplies 3.3V load output, ambient temperature range 70°C. Parameters denoted with asterisk represent nominal characterization data currently production tested specific limits. characterization data from typical. Negative currents indicate current flows device. Spread spectrum modulation disabled except Rise/Fall time measurements.
PARAMETER Overall Spread Spectrum Modulation Frequency Spread Spectrum Modulation Profile Spread Spectrum Modulation Index Clock Skew
SYMBOL
CONDITIONS/DESCRIPTION MIN.
100MHz TYP. MAX. MIN.
66.67MHz TYP. MAX.
UNITS
SS_EN# SS_EN# Lexmark
31.5 Lexmark -0.5 1.73 1.88
31.5
SS_EN#
1.25V, CL=20pF
-0.5
tskw
APIC APIC 1.25V, CL=20pF 1.5V, CL=30pF
Clock Offset Tristate Enable Delay Tristate Disable Delay Clock Stabilization power-up)
tDZL, tDZH tDZL, tDZH tSTB
1.25V, 20pF 1.5V, 30pF
SEL_0:1 SEL_100/66# SEL_0:1 SEL_100/66# PWR_DWN#
CPU_0:3 Clock Outputs (2.5V Type Clock Buffer) Duty Cycle Jitter, Long Term (y()) Jitter, Period (peak-peak) Rise Time Fall Time Enable Delay Disable Delay tj(LT) tj(P) tDLH tDHL
Ratio high pulse width, measured from rising edge next falling edge 1.25V, clock period rising edges 500µs apart 1.25V relative ideal clock, CL=20pF, PLLs active From rising edge next rising edge 1.25V, CL=20pF, PLLs active Measured 0.4V 2.0V; 10pF Measured 0.4V 2.0V; 20pF Measured 2.0V 0.4V; 10pF Measured 2.0V 0.4V; 20pF
CPU_STOP# CPU_STOP#
APIC_0:1 Clock Output (2.5V Type Clock Buffer) Duty Cycle Jitter, Long Term (y()) Jitter, Period (peak-peak) Rise Time Fall Time tj(LT) tj(P)
Ratio high pulse width, measured from rising edge next falling edge 1.25V, clock period rising edges 500µs apart 1.25V relative ideal clock, CL=20pF, PLLs active From rising edge next rising edge 1.25V, CL=20pF, PLLs active Measured 0.4V 2.0V; 10pF Measured 0.4V 2.0V; 20pF Measured 2.0V 0.4V; 10pF Measured 2.0V 0.4V; 20pF
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Table Timing Specifications, continued
Unless otherwise stated, power supplies 3.3V load output, ambient temperature range 70°C. Parameters denoted with asterisk represent nominal characterization data currently production tested specific limits. characterization data from typical. Negative currents indicate current flows device. Spread spectrum modulation disabled except Rise/Fall time measurements.
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION MIN.
100MHz TYP. MAX. MIN.
66.67MHz TYP. MAX.
UNITS
REF_0:2, 48M_0:1 Clock Outputs (3.3V Type Clock Buffer) Duty Cycle Jitter, Long Term (y()) Jitter, Period (peak-peak) Rise Time Fall Time tj(LT) tj(P)
Ratio high pulse width, measured from rising edge next falling edge 1.5V, clock period rising edges 500µs apart 1.5V relative ideal clock, CL=20pF, PLLs active From rising edge next rising edge 1.5V, CL=20pF, PLLs active Measured 0.4V 2.4V; 10pF Measured 0.4V 2.4V; 20pF Measured 2.4V 0.4V; 10pF Measured 2.4V 0.4V; 20pF
PCI_1:7, PCI_F Clock Outputs (3.3V Type Clock Buffer) Duty Cycle Jitter, Long Term (y()) Jitter, Period (peak-peak) Rise Time Fall Time Enable Delay Disable Delay tj(LT) tj(P) tDLH tDHL
Ratio high pulse width, measured from rising edge next falling edge 1.5V, clock period rising edges 500µs apart 1.5V relative ideal clock, CL=30pF, PLLs active From rising edge next rising edge 1.5V, CL=30pF, PLLs active Measured 0.4V 2.4V; 15pF Measured 0.4V 2.4V; 30pF Measured 2.4V 0.4V; 15pF Measured 2.4V 0.4V; 30pF
PCI_STOP# PCI_STOP#
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Figure CPU_0:3 Clock Outputs (2.5V Type Clock Buffer)
Voltage
2.375 2.625
High Drive Current (mA) MIN.
TYP.
MAX.
Voltage
2.375 2.625
Drive Current (mA) MIN.
TYP.
MAX.
-107 -107 -107 -107 -105 -101 -100 -120
MIN. TYP. MAX.
Figure APIC_0:1 Clock Output (2.5V Type Clock Buffer)
Voltage
2.375 2.625
High Drive Current (mA) MIN.
TYP.
MAX.
Voltage
2.375 2.625
Drive Current (mA) MIN.
TYP.
MAX.
-159 -159 -159 -159 -157 -150 -140 -127 -109
-100 -120
MIN.
-140 -160
TYP. MAX.
-180
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Figure REF_0:2, 48M_0:1 Clock Outputs (3.3V Type Clock Buffer)
Voltage
0.65 0.85 1.65 1.95 3.135
High Drive Current (mA) MIN.
TYP.
MAX.
Voltage
1.65 3.135 3.465
Drive Current (mA)
MIN.
TYP.
MAX.
MIN.
-100 -120
TYP. MAX.
Figure PCI_1:7, PCI_F Clock Outputs (3.3V Type Clock Buffer)
Voltage
0.65 0.85 1.65 1.95 3.135
High Drive Current (mA) MIN.
17.7 26.5
TYP.
MAX.
Voltage
1.65 3.135 3.465
Drive Current (mA)
MIN.
-25.5 -14.5
TYP.
MAX.
-195 -194 -189 -184 -172 -159 -140 -100
-100 -120 -140 -160 -180 -200
MIN. TYP. MAX.
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Figure Measurement Points
3.3V 2.4V 1.5V 0.4V (device interface) 0.8V
2.5V 2.0V 2.0V 1.25V 0.4V 0.7V 1.7V
(system interface)
(device interface)
(system interface)
3.3V Clock Interface
2.5V Clock Interface
Figure Clock Skew Diagrams
1.25V 2.5V 1.5V 3.3V 1.5V 3.3V
1.25V
2.5V
3.3V
1.25V 2.5V
3.3V IOAPIC
1.25V 2.5V
1.5V
1.5V
2.5V 3.3V Clock Offset
2.5V 2.5V Clock Skew
3.3V 3.3V Clock Skew
3.3V 2.5V Clock Offset
Figure Timing Diagrams
Duty Cycle
2.4V 1.5V 0.4V
Duty Cycle
2.0V 1.25V 0.4V
3.3V Clock Interface
2.5V Clock Interface
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Package Information
Table 48-pin SSOP (7.5mm/0.300") Package Dimensions
DIMENSIONS INCHES MIN. 0.095 0.008 0.088 0.008 0.005 0.620 0.292 0.400 0.024 MAX. 0.110 0.016 0.092 0.0135 0.010 0.630 0.299 0.410 0.040 MILLIMETERS MIN. 2.41 0.203 2.24 0.203 0.127 15.75 7.42 10.16 0.610 MAX. 2.79 0.406
2.34 0.343 0.254
16.00 7.59 10.41 1.02
BASE PLANE
RADII: 0.005" 0.01"
typ.
0.025
0.64
SEATING PLANE
Table 48-pin SSOP (7.5mm/0.300") Package Characteristics
PARAMETER Thermal Impedance, Junction Free-Air Lead Inductance, Self Lead Inductance, Mutual Lead Capacitance, Bulk Lead Capacitance, Mutual SYMBOL CONDITIONS/DESCRIPTION flow Center lead Center lead adjacent lead Center lead Center lead adjacent lead TYP. UNITS °C/W
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Table 28-pin SSOP Package Dimensions
DIMENSIONS INCHES MIN. 0.068 0.002 0.066 0.01 0.005 0.396 0.205 0.301 0.022 MAX. 0.078 0.008 0.07 0.015 0.008 0.407 0.212 0.311 0.037 MILLIMETERS MIN. 1.73 0.05 1.68 0.25 0.13 10.07 5.20 7.65 0.55 MAX. 2.00 0.21 1.78 0.38 0.20 10.33 5.38
RADII: 0.005" 0.01"
typ.
0.028
0.65 7.90 0.95
BASE PLANE
SEATING PLANE
Table 28-pin SSOP Package Characteristics
PARAMETER Thermal Impedance, Junction Free-Air Lead Inductance, Self Lead Inductance, Mutual Lead Capacitance, Bulk Lead Capacitance, Mutual SYMBOL CONDITIONS/DESCRIPTION flow Center lead Center lead adjacent lead Center lead Center lead adjacent lead TYP. 2.24 0.95 0.25 0.07 UNITS °C/W
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Table 28-pin SOIC (0.300") Package Dimensions
DIMENSIONS INCHES MIN. 0.093 0.004 0.08 0.013 0.009 0.697 0.291 0.393 0.010 0.016 MAX. 0.104 0.012 0.100 0.013 0.009 0.713 0.299 0.419 0.030 0.05 MILLIMETERS MIN. 2.35 0.10 2.05 0.33 0.23 17.70 7.40 10.00 0.25 0.40 MAX. 2.65 0.30 2.55 0.51 0.32 18.10 7.60 10.65 0.75 1.27
BASE PLANE RADII: 0.005" 0.01"
typ.
0.05
1.27
SEATING PLANE
Table 28-pin SOIC (0.300") Package Characteristics
PARAMETER Thermal Impedance, Junction Free-Air Lead Inductance, Self Lead Inductance, Mutual Lead Capacitance, Bulk Lead Capacitance, Mutual SYMBOL CONDITIONS/DESCRIPTION flow Center lead Center lead adjacent lead Center lead Center lead adjacent lead TYP. 2.53 0.85 0.42 0.08 UNITS °C/W
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Ordering Information
FONT ORDERING CODE 11525-801 11525-802 PACKAGE TYPE 48-pin (7.5mm/0.300") SSOP (Shrink Small Outline Package) 28-pin (7.5mm/0.300") SOIC (Small Outline Package) 28-pin (5.3mm/0.209") SSOP (Shrink Small Outline Package) OPERATING TEMPERATURE RANGE 70°C (Commercial) 70°C (Commercial) 70°C (Commercial) SHIPPING CONFIGURATION Tape Reel Tape Reel Tape Reel
DEVICE NUMBER FS6251
FS6252
11525-803
Copyright 1998, 1999 American Microsystems, Inc.
Devices sold covered warranty patent indemnification provisions appearing Terms Sale only. makes warranty, express, statutory implied description, regarding information forth herein regarding freedom described devices from patent infringement. makes warranty merchantability fitness purposes. reserves right discontinue production change specifications prices time without notice. AMI's products intended commercial applications. Applications requiring extended temperature range, unusual environmental requirements, high reliability applications, such military, medical life-support life-sustaining equipment, specifically recommended without additional processing such applications.
American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, 83201, (208) 233-4690, (208) 234-6796, Address: http://www.amis.com E-mail: tgp@amis.com
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Tracking Skew
Time-Domain Simulator Tracking
Michael Zhang Intel Corp. Platform Architecture Lab. 2111 25th Ave., M/S: JF2-54 Hillsboro, 97124-5961
email: michael.t.zhang@intel.com phone: (503)-264-2301 fax: (503)-264-6053 This application note Mathcad simulation downstream tracking skew spread spectrum clock with Lexmark profile. Mathcad document, along with three different modulation profiles, obtained from Intel's site http://www.intel.com from AMI's site http://www.amis.com. either document unavailable, contact your local sales representative obtain copy. This document supplied application information only, intended imply acceptance this other device Intel.
Clementi American Microsystems, Inc. Timing Generator Products Bethlehem Pike Ambler, 19002-2659
email: dclement@focus.amis.com phone: (215)-654-1719 fax: (215)-654-9791
April 1998
Information this document provided connection with Intel products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Patent Royalty Payments applicable responsibility Intel. Third-party brands names property their respective owners. Copyright 1998, Intel Corporation, Rights Reserved.
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Note: inputs needed highlighted equations (with yellow background color).
Read modulation profile: (Use .prn file name argument READPRN function. file names three example modulation profiles are: lexmark.prn, triangle.prn, sin.prn)
READPRN( "lexmark.prn" wavepoints rows wavepoints
carrier
mean(
min(
carrier 99.75
<-the center frequency clock <-the spread amount
max(
max(
max(
min(
carrier max( max(
31.17
<-the modulation frequency
Input modulation amount (peak peak percentage, _mod)
_mod 0.5.%
f_mod carrier max( _mod _mod carrier
Display profiles
9.99 1000 2000 3000 4000 5000 6000 7000 8000 9000
Modulation Profile
Frequency [Hz]
9.98 9.96 9.95 9.94
Build simulation. general methodology that will here Compute phase source waveform (the that applied tracking PLL) series points time. Iteratively compute phase tracking clock successive points series, take error between clocks adjust frequency tracking suit. Note that spacing points regular. actual PLL, corrections loop applied only zero crossings signals. This deviation from actual practice demonstrated have very small effect resulting performance loop (assuming that cycle slips occurring). simulation time step will average clock period: step range variables simulation:
carrier
wavepoints
wavepoints
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Compute accumulated phase each source clock each point simulation:
.f_modi1 step
Define parameters tracking PLL:
400. volt
<-the gain (not including feedback divider) <-the modulus feedback divider <-the loop filter resistor
9750.ohm
11.10
farad farad
<-the loop filter capacitors
356.10
7.10 .amp
<-the charge pump current
Calculate effective series capacitance (used later):
10.67
Find loop bandwidth phase angle transfer function:
VCO.I FB.C
root
1.504
0.262
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Display Bode plot tracking closed loop response:
.1000.Hz
bpts
.10.MHz
bpts
min.e
bpts
Input-to-Output Transfer Function
Remove dimensions speed iterative calculations:
step
farad
step
farad
carrier.sec
VCO.sec .volt
carrier
farad
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functions calculate voltage after some time (t), with applied current (I), with initial voltages capacitors (V10 V20, respectively):
.R.C
.R.C
function used compute area under loop filter voltage curve (this will used twice: once time charge pump second time when off):
.R.C
.R.C
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Define function accept array incoming phase time data simulate response PLL:
trackPLL( _src
_trk0
initialize tracking phase initialize voltage
carrier.N carrier.N _trkk
initialize voltage
wavepoints _src
sample phase error
carrier step step CP.sgn step step step _trkk
calculate pulse width
make correct polarity charge pump current
compute voltage current pulse
compute voltage sampling period
compute total volt-seconds under loop filter voltage curve parts)
incr _trkk _trk
total phase accumulated this step
incr
running total phase accumulated return saved data
function above compute response pre-calculated source phase sequences:
300. wavepoints
simdata
trackPLL(
skewi
simdata
carrier.Hz
translate time-domain
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Display resulting skew time plots:
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max( skew min( skew
Tracking Skew
Skew [ps]
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