CILETIV LESO System Frequency (fCK) Clock Cycle Time (tCK3) Clock

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

CILETIV LESO System Frequency (fCK) Clock Cycle Time (tCK3) Clock

Datasheet Thumbnail

Top Searches for this datasheet

V54C3128(16/80/40)4V(BGA) 128Mbit SDRAM VOLT, PACKAGE
CILETIV LESO
System Frequency (fCK) Clock Cycle Time (tCK3) Clock Access Time (tAC3) Latency Clock Access Time (tAC2) Latency
Features
banks 2Mbit organization banks 4Mbit organization banks 8Mbit organization High speed data transfer rates Full Synchronous Dynamic RAM, with signals referenced clock rising edge Single Pulsed Interface Data Mask Read/Write Control Four Banks controlled Programmable Latency: Programmable Wrap Sequence: Sequential Interleave Programmable Burst Length: Sequential Type Interleave Type Multiple Burst Read with Single Write Operation Automatic Controlled Precharge Command Random Column Address every (1-N Rule) Power Down Mode Auto Refresh Self Refresh Refresh Interval: 4096 cycles/64 Available WBGA LVTTL Interface Single +3.3 ±0.3 Power Supply
Description
V54C3128(16/80/40)4V(BGA) four bank Synchronous DRAM organized banks 2Mbit banks 4Mbit banks 8Mbit V54C3128(16/80/40)4V(BGA) achieves high speed data transfer rates employing chip architecture that prefetches multiple bits then synchronizes output data system clock control, address, data input output circuits synchronized with positive edge externally supplied clock. Operating four memory banks interleaved fashion allows random access operation occur higher rate than possible with standard DRAMs. sequential gapless data rate possible depending burst length, latency speed grade device.
Device Usage Chart
Operating Temperature Range
70°C
Package Outline
Access Time (ns)
Power
Std.
Temperature Mark
Blank
V54C3128(16/80/40)4V(BGA) Rev. November 2002
V54C3128(16/80/40)4V(BGA)
MOSEL-VITELIC MANUFACTURED SYCHRONOUS DRAM FAMILY CMOS PROCESS 3.3V, LVTTL, INTERFACE WBGA DEVICE NUMBER LVTTL SPECIAL FEATURE COMPONENT REV. LEVEL 8Mbit 128164 16Mbit 128804 32Mbit 128404 PKG.
CILETIV LESO
128404
SPEED
Description WBGA
Pkg.
Count
WBGA CONFIGURATION View
VCCQ
VSSQ VCCQ VSSQ A10/AP
LDQM
DQ13 DQ11 UDQM
DQ15 VCCQ VSSQ VCCQ
VSSQ DQ14 DQ12 DQ10 Vref
VCCQ
VSSQ VCCQ VSSQ A10/AP
VCCQ VSSQ VCCQ
VSSQ Vref
VCCQ
VSSQ VCCQ VSSQ A10/AP
VCCQ VSSQ VCCQ
VSSQ Vref
V54C3128(16/80/40)4V(BGA) Rev. November 2002
V54C3128(16/80/40)4V(BGA)
Absolute Maximum Ratings*
Max. Unit
Block Diagram
Column decoder Sense amplifier I(O)
Column decoder Sense amplifier I(O)
Column decoder Sense amplifier I(O)
Bank
Bank
Bank
Column decoder Sense amplifier I(O)
LDQM
V54C3128(16/80/40)4V(BGA) Rev. November 2002
UDQM
CILETIV LESO
Capacitance*
70°C,
Symbol Parameter Input Capacitance A11) Input Capacitance RAS, CAS, CLK, CKE, Output Capacitance (I/O) Input Capacitance (CLK)
Operating temperature range Storage temperature range .-55 Input/output voltage. -0.3 (VCC+0.3) Power supply voltage -0.3 Power dissipation Data current (short circuit).50
*Note: Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. Exposure absolute maximum rating conditions extended periods affect device reliability.
*Note:Capacitance sampled 100% tested.
Configuration
Column Addresses BA0, Addresses A11, BA0,
Column address counter
Column address buffer
address buffer
Refresh Counter
decoder Memory array
decoder Memory array
decoder Memory array
decoder Memory array Bank
4096
4096
4096
4096
Input buffer
Output buffer
Control logic timing generator
I/O1-I/O16
V54C3128(16/80/40)4V(BGA)
Configuration
Column Addresses BA0, Addresses A11, BA0,
Block Diagram
Column decoder Sense amplifier I(O)
Column decoder Sense amplifier I(O)
Column decoder Sense amplifier I(O)
Bank
Bank
Bank
Column decoder Sense amplifier I(O)
V54C3128(16/80/40)4V(BGA) Rev. November 2002
CILETIV LESO
Column address counter
Column address buffer
address buffer
Refresh Counter
decoder Memory array
decoder Memory array
decoder Memory array
decoder Memory array Bank
4096 1024
4096 1024
4096 1024
4096 1024
Input buffer
Output buffer
Control logic timing generator
I/O1-I/O8
V54C3128(16/80/40)4V(BGA)
Configuration
Column Addresses A11, BA0, Addresses A11, BA0,
Block Diagram
Column decoder Sense amplifier I(O)
Column decoder Sense amplifier I(O)
Column decoder Sense amplifier I(O)
Bank
Bank
Bank
Column decoder Sense amplifier I(O)
V54C3128(16/80/40)4V(BGA) Rev. November 2002
CILETIV LESO
Column address counter
Column address buffer
address buffer
Refresh Counter
decoder Memory array
decoder Memory array
decoder Memory array
decoder Memory array Bank
4096 2048
4096 2048
4096 2048
4096 2048
Input buffer
Output buffer
Control logic timing generator
I/O1-I/O4
V54C3128(16/80/40)4V(BGA)
CILETIV LESO
Signal Description
Type
Input
Signal
Pulse
Polarity
Positive Edge
Function
system clock input. SDRAM inputs sampled rising edge clock.
Input
Level
Active High Activates signal when high deactivates signal when low, thereby initiates either Power Down mode Self Refresh mode. Active enables command decoder when disables command decoder when high. When command decoder disabled, commands ignored previous operations continue. Active When sampled positive rising edge clock, CAS, RAS, define command executed SDRAM. During Bank Activate command cycle, A0-A11 defines address (RA0-RA11) when sampled rising clock edge. During Read Write command cycle, A0-An defines column address (CA0-CAn) when sampled rising clock edge.CAn depends from SDRAM organization: SDRAM CA0-CA9, CA11. SDRAM CA0-CA9. SDRAM CA0-CA8. addition column address, A10(=AP) used invoke autoprecharge operation burst read write cycle. high, autoprecharge selected BA0, defines bank precharged. low, autoprecharge disabled. During Precharge command cycle, A10(=AP) used conjunction with control which bank(s) precharge. high, four banks will used define which bank precharge.
Input
Pulse
RAS,
Input
Pulse
Input
Level
BA0,
Input
Level
Selects which bank active.
Input Output Input
Level
Data Input/Output pins operate same manner conventional DRAMs.
LDQM UDQM
Pulse
Active High Data Input/Output mask places buffers high impedance state when sampled high. Read mode, latency clock cycles controls output buffers like output enable. Write mode, latency zero operates word mask allowing input data written blocks write operation high. Power ground input buffers core logic.
VCC, Supply VCCQ VSSQ Supply
Isolated power supply ground output buffers provide improved noise immunity.
V54C3128(16/80/40)4V(BGA) Rev. November 2002
V54C3128(16/80/40)4V(BGA)
CILETIV LESO
Operation Definition
SDRAM operations defined states control signals RAS, CAS, positive edge clock. following list shows thruth table operation commands.
Operation
Activate Read Read w/Autoprecharge Write Write with Autoprecharge Precharge Precharge Mode Register Operation Device Deselect Auto Refresh Self Refresh Entry Self Refresh Exit
Device State
Idle3 Active3 Active
A0-9,
Active3 Active3 Idle Idle Idle Idle (Self Refr.) Idle Active4 (Power Down) Active Active
Power Down Entry
Power Down Exit
Data Write/Output Enable Data Write/Output Disable
Notes: Valid Don't Care, Level, High Level CKEn signal input level when commands provided, CKEn-1 signal input level clock before commands provided. These state bank designated BS0, signals. Power Down Mode entry burst cycle.
V54C3128(16/80/40)4V(BGA) Rev. November 2002
V54C3128(16/80/40)4V(BGA)
operation must done before activate command after initial power content mode register altered re-executing mode command. banks must precharged state must high least clock before mode operation. After mode register set, Standby command required. signals RAS, CAS, positive edge clock activate mode operation. Address input data this timing defines parameters shown previous table.
default power state mode register supplier specific undefined. following power initialization sequence guarantees device preconditioned each users specific needs. Like conventional DRAM, Synchronous DRAM must powered initialized predefined manner. During power VCCQ pins must built simultaneously specified voltage when input signals held "NOP" state. power voltage must exceed VCC+0.3V input pins supplies. signal must started same time. After power initial pause required followed precharge both banks using precharge command. prevent data contention during power required that pins held high during initial pause period. Once banks have been precharged, Mode Register Command must issued initialize Mode Register. minimum eight Auto Refresh cycles (CBR) also required.These done before after programming Mode Register. Failure follow these steps lead unpredictable start-up modes.
Mode register designates operation mode read write cycle. This register divided into fields. Burst Length Field length burst, Addressing Selection program column access sequence burst cycle (interleaved sequential), Latency Field access time clock cycle Operation mode field differentiate between normal operation (Burst read burst Write) special Burst Read Single Write mode. mode
CILETIV LESO
Power Initialization
Read Write Operation
When both high positive edge clock, cycle starts. According address data, word line selected bank activated sense amplifiers associated wordline set. cycle triggered setting high clock timing after necessary delay, tRCD, from timing. used define either read write this stage. SDRAM provides wide variety fast access modes. single cycle, serial data read write operations allowed data rate. numbers serial data bits burst length programmed mode operation, i.e., Column addresses segmented burst length serial data accesses done within this boundary. first column address accessed supplied timing subsequent addresses generated automatically programmed burst length sequence. example, burst length with interleave sequence, first address `2', then rest burst sequence
Programming Mode Register
V54C3128(16/80/40)4V(BGA) Rev. November 2002
V54C3128(16/80/40)4V(BGA)
Address Input Mode (Mode Register Operation)
Similar page mode conventional DRAM's, burst read write accesses column address possible once cycle latches sense amplifiers. maximum tRAS refresh interval time limits number random column accesses. burst access done even before previous burst ends. interrupt operation every clock cycles supported. When previous burst interrupted, remaining addresses overridden address with full burst length. interrupt which accompanies
CILETIV LESO
Address (Ax)
Operation Mode
Latency
Burst Length
Mode Register
Operation Mode
Mode Burst Read/Burst Write Burst Read/Single Write
Burst Type
Type Sequential Interleave
Latency
Latency Reserve Reserve Reserve Reserve Reserve Reserve
Burst Length
Length Sequential Reserve Reserve Reserve Reserve Interleave Reserve Reserve Reserve Reserve
with operation change from read write possible exploiting avoid contention. When more banks activated sequentially, interleaved bank read write operations possible. With programmed burst length, alternate access precharge operations more banks realize fast serial data access modes among many different pages. Once more banks activated, column column interleave operation done between different pages.
V54C3128(16/80/40)4V(BGA) Rev. November 2002
V54C3128(16/80/40)4V(BGA)
CILETIV LESO
Burst Length Sequence:
Burst Starting Address Length Sequential Burst Addressing (decimal) Interleave Burst Addressing (decimal)
Refresh Mode
SDRAM refresh modes, Auto Refresh Self Refresh. Auto Refresh similar -before-RAS refresh conventional DRAMs. banks must precharged before applying refresh mode. on-chip address counter increments word bank addresses bank information required both refresh modes. chip enters Auto Refresh mode, when held held high clock timing. mode restores word line after refresh external precharge command necessary. minimum time required between automatic refreshes burst refresh mode. same rule applies access command after automatic refresh operation. chip on-chip timer Self Refresh mode available. enters mode when RAS, CAS, high clock timing. external control signals including clock disabled. Returning high enables clock initiates refresh exit operation. After exit command, least delay required prior access command.
data mask function writes. When activated, write operation next clock prohibited (DQM Write Mask Latency tDQW zero clocks).
Power Down
order reduce standby power consumption, power down mode available. banks must precharged necessary Precharge delay (trp) must occur before SDRAM enter Power Down mode. Once Power Down mode initiated holding low, receiver circuits except gated off. Power Down mode does perform refresh operations, therefore device can't remain Power Down mode longer than Refresh period (tref) device. Exit from this mode performed taking "high". clock delay required mode entry exit.
Auto Precharge
methods available precharge SDRAMs. automatic precharge mode, timing accepts extra address, CA10, determine whether chip restores after operation. CA10 high when Read Command issued, Read with Auto-Precharge function initiated. SDRAM automatically enters precharge operation clock before last data latencies clocks latencies three clocks latencies CA10 high when Write Command issued, Write
Function
functions data read write operations. During reads, when turns "high" clock timing, data outputs disabled become high impedance after clock delay (DQM Data Disable Latency tDQZ also provides
V54C3128(16/80/40)4V(BGA) Rev. November 2002
V54C3128(16/80/40)4V(BGA)
Burst Termination
Once burst read write operation been initiated, there several methods which terminate burst operation prematurely. These methods include using another Read Write Command interrupt existing burst operation, Precharge Command interrupt burst cycle close active bank, using Burst Stop Command terminate existing burst operation leave bank open future Read Write Commands same page active bank. When interrupting burst with another Read Write Command care must taken avoid contention. Burst Stop Command, however, fewest restrictions making easiest method when terminating burst operation before been completed. Burst Stop command issued during burst write operation, then residual data from burst write cycle will ignored. Data that presented pins before Burst Stop Command registered will written memory.
There also separate precharge command available. When high clock timing, triggers precharge operation. Three address bits, BA0, used define banks shown following list. precharge command imposed clock before last data latency clocks before last data latency Writes require time delay from last data apply precharge command. Bank Selection Address Bits:
Bank Bank Bank Bank Banks
CILETIV LESO
with Auto-Precharge function initiated. SDRAM automatically enters precharge operation time delay equal (Write recovery time) after last data
Precharge Command
Recommended Operation Characteristics LV-TTL
VCC,VCCQ
Limit Values Parameter
Input high voltage Input voltage Output high voltage (IOUT Output voltage (IOUT Input leakage current, input other inputs Output leakage current disabled, VOUT
Symbol
II(L) IO(L)
min.
max.
Vcc+0.3
Unit
Notes
Note: voltages referenced VSS. overshoot pulse width with 3.3V. undershoot -2.0 pulse width with 3.3V. Pulse width measured points with amplitude measured peak reference.
V54C3128(16/80/40)4V(BGA) Rev. November 2002
V54C3128(16/80/40)4V(BGA)
CILETIV LESO
Operating Currents 70°C, 3.3V 0.3V)
(Recommended Operating Conditions unless otherwise noted)
Max. Symbol
ICC1
Parameter Test Condition
Operating Current tRCMIN., tCKMIN Active-precharge command cycling, without Burst Operation Precharge Standby Current Power Down Mode =VIH, VIL(max) Precharge Standby Current Non-Power Down Mode =VIH, VIL(max) Operating Current min, VIH(min) bank active state banks) bank operation
-7PC
-8PC
Unit
Note
ICC2P ICC2PS ICC2N ICC2NS ICC3N
min. Infinity min. Infinity IH(MIN.) VIL(MAX.) (Power down mode)
ICC3P
ICC4
Burst Operating Current Read/Write command cycling Auto Refresh Current Auto Refresh command cycling Self Refresh Current Self Refresh Mode, CKE0.2V
ICC5
ICC6
L-version
Notes: These parameters depend cycle rate these values measured cycle rate under minimum value tRC. Input signals changed time during tCK. These parameter depend output loading. Specified values obtained with output open.
V54C3128(16/80/40)4V(BGA) Rev. November 2002
V54C3128(16/80/40)4V(BGA)
Limit Values Symbol Parameter -7PC -8PC
CILETIV LESO
Characteristics 1,2,
Min. Max. Min. Max. Min. Max. Min. Max. Unit Note
Clock Clock Enable
Clock Cycle Time Latency Latency Clock Frequency Latency Latency Access Time from Clock Latency Latency Clock High Pulse Width Clock Pulse Width Transition
Setup Hold Times
tCKS tCKH tRSC Input Setup Time Input Hold Time Input Setup Time Hold Time Mode Register Set-up Time Power Down Mode Entry Time
Common Parameters
tRCD tRAS tRRD tCCD Column Delay Time Precharge Time Active Time Cycle Time Activate(a) Activate(b) Command Period CAS(a) CAS(b) Command Period 100K 100K 100K 100k
Refresh Cycle
tREF tSREX Refresh Period (4096 cycles) Self Refresh Exit Time
V54C3128(16/80/40)4V(BGA) Rev. November 2002
V54C3128(16/80/40)4V(BGA)
CILETIV LESO
Characteristics (Cont'd)
Limit Values Symbol Parameter -7PC -8PC
Min. Max. Min. Max. Min. Max. Min. Max. Unit Note
Read Cycle
tDQZ Data Hold Time Data Impedance Time Data High Impedance Time Data Disable Latency
Write Cycle
tDQW Write Recovery Time Write Mask Latency
Notes Parameters:
proper power-up operation section this data sheet. timing tests have 0.8V 2.0V with timing referenced crossover point. transition time measured between VIL. measurements assume with output load circuit shown Figure
COMMAND 1.4V
Z=50
1.4V
OUTPUT
Figure
clock rising time longer than time (tT/2 0.5) added this parameter. longer than time added this parameter. These parameter account number clock cycle depend operating frequency clock, follows: number clock cycle specified value timing period (counted fractions whole number) Self Refresh Exit synchronous operation begins positive clock edge after returns high. Self Refresh Exit complete until time period equal satisfied once Self Refresh Exit command registered. Referenced time which output achieves open circuit condition, output voltage levels
V54C3128(16/80/40)4V(BGA) Rev. November 2002
V54C3128(16/80/40)4V(BGA)
CILETIV LESO
Timing Diagrams
Bank Activate Command Cycle Burst Read Operation Read Interrupted Read Read Write Interval Read Write Interval Minimum Read Write Interval Non-Minimum Read Write Interval Burst Write Operation Write Read Interrupt Write Interrupted Write Write Interrupted Read Burst Write Read with Auto-Precharge Burst Write with Auto-Precharge Burst Read with Auto-Precharge Burst Termination Termination Burst Write Operation Termination Burst Write Operation Parameters Parameters Write Timing Parameters Read Timing Mode Register Power Sequence Auto Refresh (CBR) Power Down Mode Self Refresh (Entry Exit) Auto Refresh (CBR)
V54C3128(16/80/40)4V(BGA) Rev. November 2002
V54C3128(16/80/40)4V(BGA)
Random Column Write Page within same Bank) 16.1 Latency 16.2 Latency Random Read Interleaving Banks) with Precharge 17.1 Latency 17.2 Latency Random Write Interleaving Banks) with Precharge 18.1 Latency 18.2 Latency Precharge Termination Burst 19.1 Latency 19.2 Latency
CILETIV LESO
Timing Diagrams (Cont'd)
Random Column Read Page within same Bank) 15.1 Latency 15.2 Latency
V54C3128(16/80/40)4V(BGA) Rev. November 2002
V54C3128(16/80/40)4V(BGA)
Burst Read Operation (Burst Length latency
COMMAND
latency
tCK2, I/O's
latency
tCK3, I/O's
CILETIV LESO
Bank Activate Command Cycle (CAS latency
ADDRESS
Bank Addr.
Bank Col. Addr.
Bank Addr.
Bank Addr.
tRCD
tRRD
Write with Auto Precharge Bank Activate Bank Activate
COMMAND
Bank Activate
READ
DOUT
DOUT
DOUT
DOUT
DOUT
DOUT
DOUT
DOUT
V54C3128(16/80/40)4V(BGA) Rev. November 2002
V54C3128(16/80/40)4V(BGA)
CILETIV LESO
Read Interrupted Read (Burst Length latency
COMMAND
READ
READ
latency
tCK2, I/O's
latency
DOUT
DOUT
DOUT
DOUT
DOUT
tCK3, I/O's
DOUT
DOUT
DOUT
DOUT
DOUT
Read Write Interval
(Burst Length latency
Minimum delay between Read Write Commands cycles
tDQZ
tDQW
COMMAND
READ
WRITE
I/O's
DOUT Must Hi-Z before Write Command
V54C3128(16/80/40)4V(BGA) Rev. November 2002
V54C3128(16/80/40)4V(BGA)
COMMAND
CILETIV LESO
Minimum Read Write Interval (Burst Length latency
tDQW
tDQZ
Interval BANK ACTIVATE
COMMAND
READ
WRITE
Must Hi-Z before Write Command latency
tCK2, I/O's
Non-Minimum Read Write Interval
(Burst Length latency
tDQW
tDQZ
READ READ WRITE
latency
tCK1, I/O's
latency
DOUT
DOUT Must Hi-Z before Write Command
tCK2, I/O's
DOUT
V54C3128(16/80/40)4V(BGA) Rev. November 2002
V54C3128(16/80/40)4V(BGA)
CILETIV LESO
Burst Write Operation (Burst Length latency
COMMAND
WRITE
I/O's
don't care
first data element Write registered same clock edge.
Extra data ignored after termination Burst.
Write Interrupted Write (Burst Length latency
COMMAND
WRITE
WRITE
Interval
I/O's
V54C3128(16/80/40)4V(BGA) Rev. November 2002
V54C3128(16/80/40)4V(BGA)
CILETIV LESO
Write Interrupted Read (Burst Length latency
COMMAND
WRITE
READ
latency
tCK2, I/O's
latency
don't care
DOUT
DOUT
DOUT
DOUT
tCK3, I/O's
don't care
don't care
DOUT
DOUT
DOUT
DOUT
Input data must removed from I/O's least clock cycle before Read dataAPpears outputs avoid data contention.
Burst Write with Auto-Precharge Burst Length latency
COMMAND
BANK ACTIVE
WRITE
Auto-Precharge
latency
I/O's
latency
I/O's
Bank reactivated after
Begin Autoprecharge
V54C3128(16/80/40)4V(BGA) Rev. November 2002
V54C3128(16/80/40)4V(BGA)
CILETIV LESO
Burst Read with Auto-Precharge Burst Length latency
COMMAND
WRITE
READ
latency
tCK2, I/O's
latency
DOUT
DOUT
DOUT
DOUT DOUT DOUT
tCK3, I/O's
DOUT
DOUT
Bank reactivated after
Begin Autoprecharge
V54C3128(16/80/40)4V(BGA) Rev. November 2002
V54C3128(16/80/40)4V(BGA)
Termination Burst Write Operation (CAS latency
CILETIV LESO
Termination Burst Read Operation (CAS latency
COMMAND
READ
Burst Stop
latency
tCK2, I/O's
latency
DOUT
DOUT
DOUT
DOUT
tCK3, I/O's
DOUT
DOUT
DOUT
DOUT
COMMAND
latency
WRITE
Burst Stop
I/O's
don't care
Input data Write masked.
V54C3128(16/80/40)4V(BGA) Rev. November 2002
Parameters Write Timing
Burst Length Latency
Begin Auto Precharge Bank Begin Auto Precharge Bank
tCKH
tCK2
V54C3128(16/80/40)4V(BGA) Rev. November 2002
Addr
tRCD
tDPL
tRRD
Hi-Z
V54C3128(16/80/40)4V(BGA)
Activate Write with Activate Write with Activate Command Auto Precharge Command Auto Precharge Command Bank Command Bank Command Bank Bank Bank
Write Command Bank
Precharge Command Bank
Activate Command Bank
Activate Command Bank
CILETIV LESO
tCKS
Parameters Read Timing
Burst Length Latency
tCKS
Begin Auto Precharge Bank
tCKH
tCK2
V54C3128(16/80/40)4V(BGA) Rev. November 2002
Addr tRRD
tRAS tAC2 tRCD tAC2
Activate Command Bank
Hi-Z
V54C3128(16/80/40)4V(BGA)
Read Command Bank
Activate Command Bank
Read with Auto Precharge Command Bank
Precharge Command Bank
Activate Command Bank
CILETIV LESO
Mode Register
Clock min.
V54C3128(16/80/40)4V(BGA) Rev. November 2002
Address
Addr
V54C3128(16/80/40)4V(BGA)
Precharge Command Banks
Mode Register Command
Command
CILETIV LESO
Power Sequence Auto Refresh (CBR)
V54C3128(16/80/40)4V(BGA) Rev. November 2002
Address
Addr
Hi-Z
Precharge Auto Refresh Command Command Banks
Auto Refresh Command
Mode Register Command
Command
V54C3128(16/80/40)4V(BGA)
Inputs must stable 200µs
CILETIV LESO
Minimum Refresh Cycles required Clock min.
High level required
Power Down Mode
Burst Length Latency
tCKSP
V54C3128(16/80/40)4V(BGA) Rev. November 2002
Addr
Hi-Z
Activate Command Bank
Precharge Command Bank
Power Down Mode Entry
Power Down Mode Exit Command
CILETIV LESO
V54C3128(16/80/40)4V(BGA)
Self Refresh (Entry Exit)
V54C3128(16/80/40)4V(BGA) Rev. November 2002
Addr
Hi-Z
Banks must idle
Self Refresh Entry
Begin Self Refresh Exit Command Self Refresh Exit Command issued Self Refresh Exit
CILETIV LESO
CKSR tSREX
V54C3128(16/80/40)4V(BGA)
Auto Refresh (CBR)
Burst Length Latency
V54C3128(16/80/40)4V(BGA) Rev. November 2002
Addr
(Minimum Interval)
Hi-Z
V54C3128(16/80/40)4V(BGA)
Precharge Command Banks
Auto Refresh Command
Auto Refresh Command
Activate Command Bank
Read Command Bank
CILETIV LESO
tCK2
15.1 Random Column Read (Page within same Bank)
Burst Length Latency
tCK2
V54C3128(16/80/40)4V(BGA) Rev. November 2002
Addr
Hi-Z
V54C3128(16/80/40)4V(BGA)
Activate Command Bank Read Command Bank
Read Command Bank
Read Command Bank
Precharge Command Bank
Activate Command Bank
Read Command Bank
CILETIV LESO
15.2 Random Column Read (Page within same Bank)
Burst Length Latency
tCK3
V54C3128(16/80/40)4V(BGA) Rev. November 2002
Addr
Hi-Z
V54C3128(16/80/40)4V(BGA)
Activate Command Bank Read Command Bank
Read Command Bank
Read Command Bank
Precharge Command Bank
Activate Command Bank
Read Command Bank
CILETIV LESO
16.1 Random Column Write (Page within same Bank)
Burst Length Latency
tCK2
V54C3128(16/80/40)4V(BGA) Rev. November 2002
Addr
Hi-Z
DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3
DBz0 DBz1 DBz2 DBz3
V54C3128(16/80/40)4V(BGA)
Activate Command Bank
Write Command Bank
Write Command Bank
Write Command Bank
Precharge Command Bank
Activate Command Bank
Write Command Bank
CILETIV LESO
16.2 Random Column Write (Page within same Bank)
Burst Length Latency
V54C3128(16/80/40)4V(BGA) Rev. November 2002
Addr
Hi-Z
DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3
DBz0 DBz1
V54C3128(16/80/40)4V(BGA)
Activate Command Bank Write Command Bank
Write Command Bank
Write Command Bank
Precharge Command Bank
Activate Command Bank
Write Command Bank
CILETIV LESO
tCK3
17.1 Random Read (Interleaving Banks)
Burst Length Latency
tCK2
V54C3128(16/80/40)4V(BGA) Rev. November 2002
A11(BS)
tRCD tAC2
Hi-Z
V54C3128(16/80/40)4V(BGA)
Activate Command Bank
Read Command Bank
Activate Command Bank
Precharge Command Bank Read Command Bank
Activate Command Bank
Read Command Bank
CILETIV LESO
High
Random Read (Interleaving Banks)
Burst Length Latency
tCK3
V54C3128(16/80/40)4V(BGA) Rev. November 2002
A11(BS)
tRCD
tAC3
Hi-Z
V54C3128(16/80/40)4V(BGA)
Activate Command Bank
Read Command Bank
Activate Command Bank
Read Command Bank
Precharge Command Bank
Activate Command Bank
Read Command Bank
Precharge Command Bank
CILETIV LESO
High
18.1 Random Write (Interleaving Banks)
Burst Length Latency
tCK2
V54C3128(16/80/40)4V(BGA) Rev. November 2002
A11(BS)
tRCD
tDPL
tDPL
Hi-Z
DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3 DAy4
V54C3128(16/80/40)4V(BGA)
Activate Command Bank
Write Command Bank
Activate Command Bank
Write Command Bank Precharge Command Bank
Activate Command Bank
Write Command Bank Precharge Command Bank
CILETIV LESO
High
18.2 Random Write (Interleaving Banks)
Burst Length Latency
tCK3
V54C3128(16/80/40)4V(BGA) Rev. November 2002
A11(BS)
tRCD
tDPL
tDPL
Hi-Z
DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3
V54C3128(16/80/40)4V(BGA)
Activate Command Bank
Write Command Bank
Activate Command Bank
Write Command Bank
Precharge Command Bank
Activate Command Bank
Write Command Bank
Precharge Command Bank
CILETIV LESO
High
19.1 Precharge Termination Burst
Burst Length Latency
tCK2
V54C3128(16/80/40)4V(BGA) Rev. November 2002
Addr
DAx0 DAx1 DAx2 DAx3
Hi-Z
Activate Command Bank
V54C3128(16/80/40)4V(BGA)
Write Precharge Command Command Bank Bank Precharge Termination Write Burst. Write data masked.
Activate Command Bank
Read Command Bank
Precharge Command Bank
Activate Command Bank
Read Command Bank
Precharge Command Bank Precharge Termination Read Burst.
CILETIV LESO
High
19.2 Precharge Termination Burst
Burst Length Latency
tCK3
V54C3128(16/80/40)4V(BGA) Rev. November 2002
Addr
DAx0
Hi-Z
Activate Command Bank Write Command Bank Precharge Command Bank Write Data masked
Activate Command Bank Precharge Termination Write Burst.
Read Command Bank
Precharge Command Bank
Activate Command Bank Precharge Termination Read Burst.
CILETIV LESO
High
V54C3128(16/80/40)4V(BGA)
V54C3128(16/80/40)4V(BGA)
CILETIV LESO
Complete List Operation Commands SDRAM Function Truth Table
CURRENT STATE1
Idle
Addr
Code CA,AP CA,AP CA,AP CA,AP CA,AP CA,AP
ACTION
Power Down ILLEGAL2 ILLEGAL2 (&Bank) Active; Latch Address NOP4 Auto-Refresh Self-Refresh5 Mode reg. Access5 Begin Read; Latch DetermineAP Begin Write; Latch DetermineAP ILLEGAL2 Precharge ILLEGAL (Continue Burst End;>Row Active) (Continue Burst End;>Row Active) Burst Stop Command Active Term Burst, Read, DetermineAP3 Term Burst, Start Write, DetermineAP ILLEGAL2 Term Burst, Precharge ILLEGAL (Continue Burst End;>Row Active) (Continue Burst End;>Row Active) Burst Stop Command Active Term Burst, Start Read, DetermineAP Term Burst, Write, DetermineAP3 ILLEGAL2 Term Burst, Precharge3 ILLEGAL (Continue Burst End;> Precharge) (Continue Burst End;> Precharge) ILLEGAL2 ILLEGAL2 ILLEGAL ILLEGAL2 ILLEGAL2 ILLEGAL
Active
Read
Write
Read with Auto Precharge
V54C3128(16/80/40)4V(BGA) Rev. November 2002
V54C3128(16/80/40)4V(BGA)
CILETIV LESO
SDRAM FUNCTION TRUTH TABLE(continued)
CURRENT STATE1
Write with Auto Precharge
Addr
ACTION
(Continue Burst End;> Precharge) (Continue Burst End;> Precharge) ILLEGAL2 ILLEGAL2 ILLEGAL ILLEGAL2 ILLEGAL2 ILLEGAL NOP;> Idle after NOP;> Idle after ILLEGAL2 ILLEGAL2 ILLEGAL2 NOP4 ILLEGAL NOP;> Active after tRCD NOP;> Active after tRCD ILLEGAL2 ILLEGAL2 ILLEGAL2 ILLEGAL2 ILLEGAL ILLEGAL2 ILLEGAL2 ILLEGAL2 ILLEGAL2 ILLEGAL NOP;> Idle after NOP;> Idle after ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL
Precharging
Activating
Write Recovering
Refreshing
Mode Register Accessing
V54C3128(16/80/40)4V(BGA) Rev. November 2002
V54C3128(16/80/40)4V(BGA)
CILETIV LESO
Clock Enable (CKE) Truth Table:
STATE(n)
Self-Refresh6
Addr
ACTION
INVALID EXIT Self-Refresh, Idle after EXIT Self-Refresh, Idle after ILLEGAL ILLEGAL ILLEGAL (Maintain Self-Refresh) INVALID EXIT Power-Down, Idle. EXIT Power-Down, Idle. ILLEGAL ILLEGAL ILLEGAL (Maintain Low-Power Mode) Refer function truth table Enter Power- Down Enter Power- Down ILLEGAL ILLEGAL ILLEGAL Enter Self-Refresh ILLEGAL
Power-Down
All. Banks Idle7
Abbreviations:
Address Column Address Bank Address Auto Precharge
Notes SDRAM function truth table: Current State state bank determined entries assume that active (HIGH) during preceding clock cycle. Illegal bank specified state; Function legal bank indicated depending state that bank. Must satisfy contention, turn around, and/or write recovery requirements. bank precharging Idle state. precharge bank(s) indicated (andAP). Illegal bank Idle. High transition will re-enable other inputs asynchronously. minimum setup time must satisfied before command other than EXIT. Power-Down Self-Refresh entered only from Banks Idle State. Must legal command defined SDRAM function truth table.
V54C3128(16/80/40)4V(BGA) Rev. November 2002
V54C3128(16/80/40)4V(BGA)
CILETIV LESO
Package Diagram
60-Pin WBGA
8.50±0.10 1.05 1.60 0.80 0.20
0.50 13.0 ±0.10
MSAB
1.00
1.00 mark area (#2)
0.20
0.25+0.05 (#1) -0.10 0.12 0.10 (#1)
Notes: bond figure exposed measure within this area
V54C3128(16/80/40)4V(BGA) Rev. November 2002
V54C3128(16/80/40)4V(BGA)
U.S.A.
3910 NORTH FIRST STREET JOSE, 95134 PHONE: 408-433-6000 FAX: 408-433-0952
WEST
3910 NORTH FIRST STREET JOSE, 95134 PHONE: 408-433-6000 FAX: 408-433-0952
information this document subject change without notice. MOSEL VITELIC makes commitment update keep current information contained this document. part this document copied reproduced form means without prior written consent MOSEL-VITELIC.
CILETIV LESO
WORLDWIDE OFFICES
TAIWAN
MIN-CHUAN ROAD, SEC. TAIPEI PHONE: 886-2-2545-1213 FAX: 886-2-2545-1209 HSIN ROAD SCIENCE BASED IND. PARK HSIN CHU, TAIWAN, R.O.C. PHONE: 886-3-579-5888 FAX: 886-3-566-5888
SINGAPORE
ANSON ROAD #23-13 INTERNATIONAL PLAZA SINGAPORE 079903 PHONE: 65-6323-1801 FAX: 65-6323-7013
IRELAND
SUITE GROVEWOOD BUSINESS CENTRE STRATHCLYDE BUSINESS PARK BELLSHILL, LANARKSHIRE, SCOTLAND, PHONE: 44-1698-748515 FAX: 44-1698-748516
JAPAN
ONZE 1852 BUILDING 2-14-6 SHINTOMI, CHUO-KU TOKYO 104-0041 PHONE: 03-3537-1400 FAX: 03-3537-1402
U.S. SALES OFFICES
CENTRAL EAST
FIELDWOOD CIRCLE RICHARDSON, 75081 PHONE: 214-352-3775 FAX: 214-904-9029
Copyright MOSEL VITELIC Corp.
Printed U.S.A.
MOSEL VITELIC subjects products normal quality control sampling techniques which intended provide assurance high quality products suitable usual commercial applications. MOSEL VITELIC does testing appropriate provide 100% product quality assurance does assume liability consequential incidental arising from products. such products used applications which personal injury might occur from failure, purchaser must quality assurance testing appropriate such applications.
V54C3128(16/80/40)4V(BGA) Rev. November 2002

CILETIV LESO System Frequency (fCK) Clock Cycle Time (tCK3) Clock

Top Searches for this datasheet

Other recent searches