H8S/2612 HD6432612 H8S/2611 HD6432611 H8S/2612F-ZTATHD64F2612 Har
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H8S/2612 Series
H8S/2612 HD6432612 H8S/2611 HD6432611 H8S/2612F-ZTATHD64F2612
Hardware Manual
ADE-602-220A Rev. 01/24/01 Hitachi, Ltd.
Rev. 2.0, 01/01, page
Cautions
Hitachi neither warrants grants licenses rights Hitachi's third party's patent, copyright, trademark, other intellectual property rights information contained this document. Hitachi bears responsibility problems that arise with third party's rights, including intellectual property rights, connection with information contained this document. Products product specifications subject change without notice. Confirm that have received latest product standards specifications before final design, purchase use. Hitachi makes every attempt ensure that products high quality reliability. However, contact Hitachi's sales office before using product application that demands especially high quality reliability where failure malfunction directly threaten human life cause risk bodily injury, such aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment medical equipment life support. Design your application that product used within ranges guaranteed Hitachi particularly maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions other characteristics. Hitachi bears responsibility failure damage when used beyond guaranteed ranges. Even within guaranteed ranges, consider normally foreseeable failure rates failure modes semiconductor devices employ systemic measures such fail-safes, that equipment incorporating Hitachi product does cause bodily injury, fire other consequential damage operation Hitachi product. This product designed radiation resistant. permitted reproduce duplicate, form, whole part this document without written approval from Hitachi. Contact Hitachi's sales office questions regarding this document Hitachi semiconductor products.
Rev. 2.0, 01/01, Page
Rev. 2.0, 01/01, page
Preface
This series high-performance microcontrollers with H8S/2600 core, on-chip supporting modules required system. H8S/2600 compatible with H8/300 H8/300H CPUs. This includes peripheral on-chip functions required system configuration: data transfer controller (DTC), ROM, RAM, break controller, 16-bit timer pulse unit (TPU), motor management timer (MMT), programmable pulse generator (PPG), watchdog timer (WDT), serial communication interface (SCI), Hitachi controller area network (HCAN), converter, ports. These peripheral on-chip functions enable this embedded high-level control system. Single-power-supply flash memory (F-ZTAT available, providing quick flexible response conditions from ramp-up through full-scale volume production, even applications with frequently changing specifications. This manual describes hardware this LSI. Refer H8S/2600 Series H8S/2000 Series Programming Manual detailed description instruction set. Note: F-ZTAT (Flexible-ZTAT) trademark Hitachi, Ltd. Notation this document, when same similar functions, e.g., 16-bit timer pulse unit serial communication interface, implemented multiple channels, suffix added names registers, interrupt requests differentiate channels; channel channel
Rev. 2.0, 01/01, Page
Rev. 2.0, 01/01, page
Revisions Additions This Editions
Page Item Figure2-3 Exception Vector Table(Advanced Mode) 2.4.6 Initial Values Registers Processing States, Reset State Table Exception Handling Vector Table Revisions(See Manual Details) Amended Title amended Description amended Following exception sources amended; Interrupt(direct transitions), Interrupt(NMI), Trap instruction(#0),(#1),(#2),(#3) TGID_3 Vector Address amended
Table Interrupt Sources, Vector Address, Interrupt Priorities
6.2.3 Break Control Register A(BCRA) Table Interrupt Sources, Vector Addresses, Corresponding DTCEs Figure Chain Transfer Operation Table Function Table Function Table Function Table Function Table Function Table Function Port9 Table 9-14 Function Table 9-15 Function Table 9-16 Function Table 9-18 Function Table 9-19 Function Table 9-20 Function Table 9-21 Function 10.3 Register Descriptions 10.3.9 Timer Synchro Register(TSYR) 10.9.14 Interrupts Module Stop Mode Figure 11.8 Count Timing Notes Operation 12.3.1 Next Data Enable Registers L(NDERH, NDERL) 12.4.4 Example Normal Pulse Output(Example Five-Phase Pulse Output) 13.5.6 Flag Clearing Interval Timer Mode
description amended Reserved source vector address amended Title amended Note added Note added Note added Note added Note added Note added Description amended Note added Note added Note added Note added Note added Note added Amended Title amended Bits7 initial value amended Title amended Title amended Title amended Description amended Description amended Section added
Rev. 2.0, 01/01, Page
Page
Item 14.3.7 Serial Status Register(SSR), Smart Card Interface Mode(When SMIF SCMR Table 14-8 Examples Rate Various Settings(Smart Card Interface Mode)(When S=372 14.4.2 Receive Data Sampling Timing Reception Margin Asynchronous Mode Figure 14-4 Relationship between Output Clock Transfer Data Phase(Asynchronous Mode) 14.5 Multiprocessor Communication Function 14.8 Interrupts 15.3.5 Transmit Wait Register(TXPR) 15.3.10 Remote Request Register(RFPR) 15.3.11 Interrupt Register(IRR) 15.3.11 Interrupt Register(IRR) 15.3.16 Unread Message Status Register(UMSR) Table 15-2 Limits Settable Value 15.4.2 Initialization after Hardware Reset, Setting Message Transmission Method 15.5 Interrupts 15.7 Interface 16.1 Features 16.4.1 Single Mode 16.7.2 Permissible Signal Source Impedance 18.1 Features 18.9.3 Error Protection 18.11 Power-Down States Flash Memory 19.6.2 Note Board Design Figure19-7 External Circuitry Recommended Circuit Table 20-1 Internal States Each Mode 20.1 Register Descriptions 20.3.2 Clearing Sleep Mode Table 20-3 Oscillation Stabilization Time Settings Table 21-2 Characteristics Table 21-6 Timing On-Chip Supporting Modules Table 21-8 Flash Memory Characteristics
Revisions(See Manual Details) Bit2 description amended Amended
Description amended Title amended Description amended Title amended Bits15 description amended Bits15 description amended Bit15 description amended Bit8 description amended Bits15 description amended Amended Description amended Title amended Description amended Amended Description amended Description amended Amended Description amended Description amended Description amended Title amended state medium-speed amended Description amended Title amended Amended TBDs current dissipation amended TBDs amended Conditions amended
Rev. 2.0, 01/01, page viii
Contents
Section Overview.1
Overview. Internal Block Diagram. Arrangement Functions
Section CPU.9
Features 2.1.1 Differences between H8S/2600 H8S/2000 2.1.2 Differences from H8/300 2.1.3 Differences from H8/300H CPU. Operating Modes 2.2.1 Normal Mode. 2.2.2 Advanced Mode. Address Space. Register Configuration. 2.4.1 General Registers 2.4.2 Program Counter (PC) 2.4.3 Extended Control Register (EXR) 2.4.4 Condition-Code Register (CCR) 2.4.5 Multiply-Accumulate Register (MAC) 2.4.6 Initial Values Registers Data Formats. 2.5.1 General Register Data Formats 2.5.2 Memory Data Formats Instruction 2.6.1 Table Instructions Classified Function 2.6.2 Basic Instruction Formats Addressing Modes Effective Address Calculation 2.7.1 Register Direct-Rn. 2.7.2 Register Indirect-@ERn 2.7.3 Register Indirect with Displacement-@(d:16, ERn) @(d:32, ERn). 2.7.4 Register Indirect with Post-Increment Pre-Decrement-@ERn+ @-ERn 2.7.5 Absolute Address-@aa:8, @aa:16, @aa:24, @aa:32. 2.7.6 Immediate-#xx:8, #xx:16, #xx:32 2.7.7 Program-Counter Relative-@(d:8, @(d:16, PC). 2.7.8 Memory Indirect-@@aa:8 2.7.9 Effective Address Calculation Processing States.
Rev. 2.0, 01/01, Page
Section Operating Modes
Operating Mode Selection Register Descriptions 3.2.1 Mode Control Register(MDCR) 3.2.2 System Control Register(SYSCR) Functions Each Operating Mode 3.3.1 Functions Address
Section Exception Handling
Exception Handling Types Priority Exception Sources Exception Vector Table Reset 4.3.1 Reset Exception Handling. 4.3.2 Interrupts after Reset. 4.3.3 State On-Chip Supporting Modules after Reset Release Traces. Interrupts Trap Instruction. Stack Status after Exception Handling. Usage Note.
Section Interrupt Controller.61
Features Input/Output Pins Register Descriptions 5.3.1 Interrupt Priority Registers (IPRA IPRH,IPRJ, IPRK, IPRM). 5.3.2 Enable Register (IER) 5.3.3 Sense Control Registers (ISCRH, ISCRL). 5.3.4 Status Register (ISR). Interrupt 5.4.1 External Interrupts 5.4.2 Internal Interrupts. Interrupt Exception Handling Vector Table. Interrupt Control Modes Interrupt Operation 5.6.1 Interrupt Control Mode 5.6.2 Interrupt Control Mode 5.6.3 Interrupt Exception Handling Sequence 5.6.4 Interrupt Response Times 5.6.5 Activation Interrupt. Usage Notes 5.7.1 Contention between Interrupt Generation Disabling. 5.7.2 Instructions that Disable Interrupts
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5.7.3 5.7.4
When Interrupts Disabled Interrupts during Execution EEPMOV Instruction.
Section Break Controller (PBC)
Features Register Descriptions 6.2.1 Break Address Register (BARA) 6.2.2 Break Address Register (BARB). 6.2.3 Break Control Register (BCRA) 6.2.4 Break Control Register (BCRB). Operation 6.3.1 Break Interrupt Instruction Fetch 6.3.2 Break Interrupt Data Access. 6.3.3 Notes Break Interrupt Handling 6.3.4 Operation Transitions Power-Down Modes 6.3.5 When Instruction Execution Delayed State Usage Notes 6.4.1 Module Stop Mode Setting 6.4.2 Break Interrupts. 6.4.3 CMFA CMFB 6.4.4 Break Interrupt when Master. 6.4.5 Break Instruction Fetch Address Following BSR, JSR, JMP, TRAPA, RTE, Instruction 6.4.6 LDC, ANDC, ORC, XORC Instruction 6.4.7 Break Instruction Fetch Address Following Instruction. 6.4.8 Break Instruction Fetch Branch Destination Address Instruction.
Section Controller.91
Basic Timing 7.1.1 On-Chip Memory Access Timing (ROM, RAM) 7.1.2 On-Chip Support Module Access Timing. 7.1.3 On-Chip HCAN Module Access Timing 7.1.4 On-chip Module Access Timing. Arbitration. 7.2.1 Order Priority Masters. 7.2.2 Transfer Timing
Section Data Transfer Controller (DTC)
Features Register Configuration. 8.2.1 Mode Register (MRA) 8.2.2 Mode Register (MRB).
Rev. 2.0, 01/01, Page
8.2.3 Source Address Register (SAR). 8.2.4 Destination Address Register (DAR). 8.2.5 Transfer Count Register (CRA) 8.2.6 Transfer Count Register (CRB). 8.2.7 Enable Registers (DTCER) 8.2.8 Vector Register (DTVECR). Activation Sources Location Register Information Vector Table Operation 8.5.1 Normal Mode. 8.5.2 Repeat Mode 8.5.3 Block Transfer Mode 8.5.4 Chain Transfer 8.5.5 Interrupts. 8.5.6 Operation Timing. 8.5.7 Number Execution States. Procedures Using DTC. 8.6.1 Activation Interrupt. 8.6.2 Activation Software Examples 8.7.1 Normal Mode. 8.7.2 Chain Transfer 8.7.3 Software Activation Usage Notes 8.8.1 Module Stop Mode Setting 8.8.2 On-Chip 8.8.3 DTCE Setting.
Section Ports.119
Port 9.1.1 Port Data Direction Register (P1DDR). 9.1.2 Port Data Register (P1DR). 9.1.3 Port Register (PORT1). 9.1.4 Functions Port 9.2.1 Port Register (PORT4). Port 9.3.1 Port Register (PORT9). Port 9.4.1 Port Data Direction Register (PADDR) 9.4.2 Port Data Register (PADR) 9.4.3 Port Register (PORTA) 9.4.4 Port Pull-Up Control Register (PAPCR)
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9.4.5 Port Open-Drain Control Register (PAODR) 9.4.6 Functions Port 9.5.1 Port Data Direction Register (PBDDR). 9.5.2 Port Data Register (PBDR) 9.5.3 Port Register (PORTB) 9.5.4 Port Pull-Up Control Register (PBPCR). 9.5.5 Port Open-Drain Control Register (PBODR) 9.5.6 Functions Port 9.6.1 Port Data Direction Register (PCDDR). 9.6.2 Port Data Register (PCDR) 9.6.3 Port Register (PORTC) 9.6.4 Port Pull-Up Control Register (PCPCR). 9.6.5 Port Open-Drain Control Register (PCODR) 9.6.6 Functions Port 9.7.1 Port Data Direction Register (PDDDR) 9.7.2 Port Data Register (PDDR) 9.7.3 Port Register (PORTD) 9.7.4 Port Pull-up Control Register (PDPCR) Port 9.8.1 Port Data Direction Register (PFDDR) 9.8.2 Port Data Register (PFDR) 9.8.3 Port Register (PORTF) 9.8.4 Functions
Section 16-Bit Timer Pulse Unit (TPU).149
10.1 Features 10.2 Input/Output Pins 10.3 Register Descriptions 10.3.1 Timer Control Register (TCR) 10.3.2 Timer Mode Register (TMDR) 10.3.3 Timer Control Register (TIOR) 10.3.4 Timer Interrupt Enable Register (TIER) 10.3.5 Timer Status Register (TSR). 10.3.6 Timer Counter (TCNT). 10.3.7 Timer General Register (TGR) 10.3.8 Timer Start Register (TSTR). 10.3.9 Timer Synchro Register (TSYR) 10.4 Operation 10.4.1 Basic Functions. 10.4.2 Synchronous Operation.
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10.5 10.6 10.7 10.8
10.9
10.4.3 Buffer Operation 10.4.4 Cascaded Operation 10.4.5 Modes 10.4.6 Phase Counting Mode Interrupts Activation. Converter Activation Operation Timing. 10.8.1 Input/Output Timing 10.8.2 Interrupt Signal Timing. Usage Notes 10.9.1 Module Stop Mode Setting 10.9.2 Input Clock Restrictions 10.9.3 Caution Period Setting 10.9.4 Contention between TCNT Write Clear Operations. 10.9.5 Contention between TCNT Write Increment Operations. 10.9.6 Contention between Write Compare Match 10.9.7 Contention between Buffer Register Write Compare Match 10.9.8 Contention between Read Input Capture. 10.9.9 Contention between Write Input Capture. 10.9.10 Contention between Buffer Register Write Input Capture 10.9.11 Contention between Overflow/Underflow Counter Clearing. 10.9.12 Contention between TCNT Write Overflow/Underflow. 10.9.13 Multiplexing Pins 10.9.14 Interrupts Module Stop Mode.
Section Motor Management Timer (MMT) .231
11.1 Features 11.2 Input/Output Pins 11.3 Register Descriptions 11.3.1 Timer Mode Register (TMDR) 11.3.2 Timer Control Register (TCNR) 11.3.3 Timer Status Register (TSR). 11.3.4 Timer Counter (TCNT). 11.3.5 Timer Buffer Registers (TBR) 11.3.6 Timer General Registers (TGR). 11.3.7 Timer Dead Time Counters (TDCNT). 11.3.8 Timer Dead Time Data Register (TDDR). 11.3.9 Timer Period Buffer Register (TPBR) 11.3.10 Timer Period Data Register (TPDR). 11.3.11 Control Register (MMTPC) 11.4 Operation 11.4.1 Sample Setting Procedure
Rev. 2.0, 01/01, page
11.4.2 Output Protection Functions 11.5 Interrupts 11.6 Operation Timing. 11.6.1 Input/Output Timing 11.6.2 Interrupt Signal Timing. 11.7 Usage Notes 11.7.1 Module Stop Mode Setting 11.7.2 Notes Operation 11.8 Port Output Enable (POE). 11.8.1 Features. 11.8.2 Input/Output Pins 11.8.3 Register Descriptions 11.8.4 Operation
Section Programmable Pulse Generator (PPG) .261
12.1 Features 12.2 Input/Output Pins 12.3 Register Descriptions 12.3.1 Next Data Enable Registers (NDERH, NDERL). 12.3.2 Output Data Registers (PODRH, PODRL). 12.3.3 Next Data Registers (NDRH, NDRL) 12.3.4 Output Control Register (PCR). 12.3.5 Output Mode Register (PMR). 12.4 Operation 12.4.1 Overview. 12.4.2 Output Timing. 12.4.3 Sample Setup Procedure Normal Pulse Output. 12.4.4 Example Normal Pulse Output (Example Five-Phase Pulse Output). 12.4.5 Non-Overlapping Pulse Output. 12.4.6 Sample Setup Procedure Non-Overlapping Pulse Output 12.4.7 Example Non-Overlapping Pulse Output (Example Four-Phase Complementary Non-Overlapping Output). 12.4.8 Inverted Pulse Output 12.4.9 Pulse Output Triggered Input Capture 12.5 Usage Notes 12.5.1 Module Stop Mode Setting 12.5.2 Operation Pulse Output Pins.
Section Watchdog Timer .281
13.1 Features 13.2 Register Descriptions 13.2.1 Timer Counter (TCNT). 13.2.2 Timer Control/Status Register (TCSR)
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13.2.3 Reset Control/Status Register (RSTCSR) 13.3 Operation 13.3.1 Watchdog Timer Mode 13.3.2 Interval Timer Mode 13.4 Interrupts 13.5 Usage Notes 13.5.1 Notes Register Access. 13.5.2 Contention between Timer Counter (TCNT) Write Increment 13.5.3 Changing Value CKS2 CKS0. 13.5.4 Switching between Watchdog Timer Mode Interval Timer Mode. 13.5.5 Internal Reset Watchdog Timer Mode. 13.5.6 Flag Clearing Intervel Timer Mode
Section Serial Communication Interface (SCI) .289
14.1 Features 14.2 Input/Output Pins 14.3 Register Descriptions 14.3.1 Receive Shift Register (RSR) 14.3.2 Receive Data Register (RDR) 14.3.3 Transmit Data Register (TDR). 14.3.4 Transmit Shift Register (TSR) 14.3.5 Serial Mode Register (SMR). 14.3.6 Serial Control Register (SCR). 14.3.7 Serial Status Register (SSR) 14.3.8 Smart Card Mode Register (SCMR) 14.3.9 Rate Register (BRR) 14.4 Operation Asynchronous Mode 14.4.1 Data Transfer Format. 14.4.2 Receive Data Sampling Timing Reception Margin Asynchronous Mode. 14.4.3 Clock. 14.4.4 Initialization (Asynchronous Mode) 14.4.5 Data Transmission (Asynchronous Mode). 14.4.6 Serial Data Reception (Asynchronous Mode). 14.5 Multiprocessor Communication Function. 14.5.1 Multiprocessor Serial Data Transmission 14.5.2 Multiprocessor Serial Data Reception 14.6 Operation Clocked Synchronous Mode 14.6.1 Clock. 14.6.2 Initialization (Clocked Synchronous Mode) 14.6.3 Serial Data Transmission (Clocked Synchronous Mode) 14.6.4 Serial Data Reception (Clocked Synchronous Mode). 14.6.5 Simultaneous Serial Data Transmission Reception (Clocked Synchronous Mode)
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14.7 Operation Smart Card Interface 14.7.1 Connection Example. 14.7.2 Data Format (Except Block Transfer Mode). 14.7.3 Block Transfer Mode 14.7.4 Receive Data Sampling Timing Reception Margin Smart Card Interface Mode. 14.7.5 Initialization 14.7.6 Data Transmission (Except Block Transfer Mode) 14.7.7 Serial Data Reception (Except Block Transfer Mode) 14.7.8 Clock Output Control. 14.8 Interrupts 14.8.1 Interrupts Normal Serial Communication Interface Mode 14.8.2 Interrupts Smart Card Interface Mode 14.9 Usage Notes 14.9.1 Module Stop Mode Setting 14.9.2 Break Detection Processing 14.9.3 Mark State Break Detection 14.9.4 Receive Error Flags Transmit Operations (Clocked Synchronous Mode Only)
Section Hitachi Controller Area Network (HCAN).353
15.1 Features 15.2 Input/Output Pins 15.3 Register Descriptions 15.3.1 Master Control Register (MCR). 15.3.2 General Status Register (GSR) 15.3.3 Configuration Register (BCR) 15.3.4 Mailbox Configuration Register (MBCR) 15.3.5 Transmit Wait Register (TXPR) 15.3.6 Transmit Wait Cancel Register (TXCR). 15.3.7 Transmit Acknowledge Register (TXACK) 15.3.8 Abort Acknowledge Register (ABACK) 15.3.9 Receive Complete Register (RXPR) 15.3.10 Remote Request Register (RFPR). 15.3.11 Interrupt Register (IRR) 15.3.12 Mailbox Interrupt Mask Register (MBIMR). 15.3.13 Interrupt Mask Register (IMR) 15.3.14 Receive Error Counter (REC) 15.3.15 Transmit Error Counter (TEC). 15.3.16 Unread Message Status Register (UMSR) 15.3.17 Local Acceptance Filter Masks (LAFML, LAFMH). 15.3.18 Message Control (MC0 MC15) 15.3.19 Message Data (MD0 MD15) 15.3.20 HCAN Monitor Register (HCANMON).
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15.4 Operation 15.4.1 Hardware Software Resets 15.4.2 Initialization after Hardware Reset 15.4.3 Message Transmission 15.4.4 Message Reception 15.4.5 HCAN Sleep Mode 15.4.6 HCAN Halt Mode 15.5 Interrupts 15.6 Interface 15.7 Interface. 15.8 Usage Notes 15.8.1 Module Stop Mode Setting 15.8.2 Reset. 15.8.3 HCAN Sleep Mode 15.8.4 Interrupts. 15.8.5 Error Counters. 15.8.6 Register Access. 15.8.7 HCAN Medium-Speed Mode 15.8.8 Register Hold Standby Modes
Section Converter .401
16.1 Features 16.2 Input/Output Pins 16.3 Register Description. 16.3.1 Data Registers (ADDRA ADDRD). 16.3.2 Control/Status Register (ADCSR) 16.3.3 Control Register (ADCR) 16.4 Operation 16.4.1 Single Mode. 16.4.2 Scan Mode 16.4.3 Input Sampling Conversion Time 16.4.4 External Trigger Input Timing. 16.5 Interrupts 16.6 Conversion Precision Definitions. 16.7 Usage Notes 16.7.1 Module Stop Mode Setting 16.7.2 Permissible Signal Source Impedance 16.7.3 Influences Absolute Precision. 16.7.4 Range Analog Power Supply Other Settings 16.7.5 Notes Board Design 16.7.6 Notes Noise Countermeasures
Section .417
Rev. 2.0, 01/01, page xviii
Section .419
18.1 18.2 18.3 18.4 18.5 Features Mode Transitions Block Configuration. Input/Output Pins Register Descriptions 18.5.1 Flash Memory Control Register (FLMCR1). 18.5.2 Flash Memory Control Register (FLMCR2). 18.5.3 Erase Block Register (EBR1) 18.5.4 Erase Block Register (EBR2) 18.5.5 Emulation Register (RAMER). On-Board Programming Modes. 18.6.1 Boot Mode 18.6.2 Programming/Erasing User Program Mode. Flash Memory Emulation Flash Memory Programming/Erasing 18.8.1 Program/Program-Verify 18.8.2 Erase/Erase-Verify. 18.8.3 Interrupt Handling when Programming/Erasing Flash Memory. Program/Erase Protection 18.9.1 Hardware Protection 18.9.2 Software Protection. 18.9.3 Error Protection. Programmer Mode Power-Down States Flash Memory.
18.6
18.7 18.8
18.9
18.10 18.11
Section Clock Pulse Generator .441
19.1 Register Descriptions 19.1.1 System Clock Control Register (SCKCR) 19.1.2 Low-Power Control Register (LPWRCR) 19.2 Oscillator. 19.2.1 Connecting Crystal Resonator. 19.2.2 External Clock Input 19.3 Circuit 19.4 Medium-Speed Clock Divider 19.5 Master Clock Selection Circuit 19.6 Usage Notes 19.6.1 Note Crystal Resonator 19.6.2 Note Board Design.
Section Power-Down Modes .451
20.1 Register Descriptions 20.1.1 Standby Control Register (SBYCR)
Rev. 2.0, 01/01, Page
20.1.2 Module Stop Control Registers (MSTPCRA MSTPCRC). 20.2 Medium-Speed Mode. 20.3 Sleep Mode 20.3.1 Transition Sleep Mode. 20.3.2 Clearing Sleep Mode. 20.4 Software Standby Mode. 20.4.1 Transition Software Standby Mode 20.4.2 Clearing Software Standby Mode 20.4.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode. 20.4.4 Software Standby Mode Application Example. 20.5 Hardware Standby Mode 20.5.1 Transition Hardware Standby Mode 20.5.2 Clearing Hardware Standby Mode. 20.5.3 Hardware Standby Mode Timings 20.6 Module Stop Mode 20.6.1 Module Stop Mode 20.7 Clock Output Disabling Function 20.8 Usage Notes 20.8.1 Port Status. 20.8.2 Current Dissipation during Oscillation Stabilization Wait Period 20.8.3 Module Stop. 20.8.4 On-Chip Supporting Module Interrupt. 20.8.5 Writing MSTPCR
Section Electrical Characteristics (Preliminary).467
21.1 Absolute Maximum Ratings 21.2 Characteristics 21.3 Characteristics 21.3.1 Clock Timing 21.3.2 Control Signal Timing 21.3.3 Timing On-Chip Supporting Modules. 21.4 Conversion Characteristics. 21.5 Flash Memory Characteristics.
Appendix
.483
On-chip Register. Register Addresses. Register Bits. Register States Each Operating Mode Port States Each State. Product Code Lineup Package Dimensions
Rev. 2.0, 01/01, page
Section Overview
Overview
High-speed H8S/2600 central processing unit with internal 16-bit architecture Upward-compatible with H8/300 H8/300H CPUs object level Sixteen 16-bit general registers basic instructions Various peripheral functions break controller Data transfer controller 16-bit timer-pulse unit (TPU) Motor management timer (MMT) Programmable pulse generator (PPG) Watchdog timer Asynchronous clocked synchronous serial communication interface (SCI) Hitachi controller area network (HCAN) 10-bit converter Clock pulse generator On-chip memory
F-ZTAT Version Mask Version Model HD64F2612 HD6432612 HD6432611 128k 128k Remarks Under development planning
General ports pins: Input-only pins: Supports various power-down states Compact package
Package QFP-80 (Code) FP-80A Body Size 14.0 Pitch 0.65
14.0
Rev. 2.0, 01/01, page
Internal Block Diagram
Port
Clock pulse generator
Internal address
Internal data
H8S/2600
controller
EXTAL XTAL PLLVCL PLLCAP PLLVSS
PA3/SCK2/ PA2/RxD2/ PA1/TxD2/ PA0/
Port
Peripheral data
Interrupt controller break controller channels)
PF7/ PF3/ PF0/
Peripheral address
Port Port Port
FWE/NC*
PB7/TIOCB5/PWOB PB6/TIOCA5/PWOA PB5/TIOCB4/PVOB PB4/TIOCA4/PVOA PB3/TIOCD3/PUOB PB2/TIOCC3/PUOA PB1/TIOCB3/PCO PB0/TIOCA3/ PC5/SCK1/ PC4/RxD1 PC3/TxD1 PC2/SCK0/ PC1/RxD0 PC0/TxD0
Port
(Mask ROM, flash memory*) channel
channels
HCAN channel
converter
P93/AN11 P92/AN10 P91/AN9 P90/AN8
Port
P17/PO15/TIOCB2/TCLKD P16/PO14/TIOCA2/ P15/PO13/TIOCB1/TCLKC P14/PO12/TIOCA1/ P13/PO11/TIOCD0/TCLKB P12/PO10/TIOCC0/TCLKA P11/PO9/TIOCB0 P10/PO8/TIOCA0 AVCC AVSS HRxD HTxD
Port
Note: provided only flash memory version. provided only mask version.
Figure Internal Block Diagram
Rev. 2.0, 01/01, Page
Arrangement
FWE/NC* EXTAL XTAL PLLVss PLLVCL PLLCAP
AVcc P93/AN11 P92/AN10 P91/AN9 P90/AN8 P47/AN7 P46/AN6 P45/AN5 P44/AN4 P43/AN3 P42/AN2 P41/AN1 P40/AN0 AVss P10/PO8/TIOCA0 P11/PO9/TIOCB0 P12/PO10/TIOCC0/TCLKA
VIEW (FP-80A)
PA3/SCK2/ PA2/RxD2/ PA1/TxD2/ PA0/ PB7/TIOCB5/PWOB PB6/TIOCA5/PWOA PB5/TIOCB4/PVOB PB4/TIOCA4/PVOA PB3/TIOCD3/PUOB PB2/TIOCC3/PUOA PB1/TIOCB3/PCO PB0/TIOCA3/ PC5/SCK1/
Note: used only flash memory version. used only mask version.
P13/PO11/TIOCD0/TCLKB P14/PO12/TIOCA1/ P15/PO13/TIOCB1/TCLKC P16/PO14/TIOCA2/ P17/PO15/TIOCB2/TCLKD HTxD HRxD PF0/ PF3/ PF7/ PC0/TxD0 PC1/RxD0 PC2/SCK0/ PC3/TxD1 PC4/RxD1
Figure Arrangement
Rev. 2.0, 01/01, page
Type Power Supply
Functions
Symbol Input Function Power supply pins. Connect these pins system power supply. Ground pins. Connect these pins system power supply (0V). External capacitance internal power-down power supply. Connect this 0.1µF capacitor (placed close pins). External capacitance internal power-down power supply on-chip oscillator. Connect this PLLVSS 0.1-µF capacitor (placed close pins). On-chip oscillator ground pin. External capacitance on-chip oscillator. connection crystal resonator. examples crystal resonator connection external clock input, section Clock Pulse Generator. connection crystal resonator.( external clock supplied from EXTAL pin.) examples crystal resonator connection external clock input, section Clock Pulse Generator. Supplies system clock external devices. operating mode. Inputs these pins should changed during operation. Reset input pin. When this low, chip reset. When this low, transition made hardware standby mode. flash memory. This only used flash memory version.
Input
Output
Clock
PLLVCL
Output
PLLVSS PLLCAP XTAL
Input Output Input
EXTAL
Input
Operating mode control System control
Output Input
67%<
Input Input Input
Rev. 2.0, 01/01, Page
Type Interrupts
Symbol
Input Input
Function Nonmaskable interrupt pin. this used, should fixed-high. These pins request maskable interrupt.
16-bit timerpulse unit TCLKA TCLKB TCLKC TCLKD TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 TIOCA3 TIOCB3 TIOCC3 TIOCD3 TIOCA4 TIOCB4 TIOCA5 TIOCB5 Programmable pulse generator (PPG) PO15 PO14 PO13 PO12 PO11 PO10 PUOA PUOB PVOA
Input
These pins input external clock.
Input/ Output
TGRA_0 TGRD_0 input capture input/output compare output/PWM output pins.
Input/ Output Input/ Output Input/ Output
TGRA_1 TGRB_1 input capture input/output compare output/PWM output pins. TGRA_2 TGRB_2 input capture input/output compare output/PWM output pins. TGRA_3 TGRD_3 input capture input/output compare output/PWM output pins.
Input/ Output Input/ Output Output
TGRA_4 TGRB_4 input capture input/output compare output/PWM output pins. TGRA_5 TGRB_5 input capture input/output compare output/PWM output pins. Pulse output pins.
Motor management timer (MMT)
Output Output Output
U-phase output 6-phase non-overlap waveforms.
8-phase output 6-phase non-overlap
waveforms V-phase output 6-phase non-overlap waveforms.
Rev. 2.0, 01/01, page
Type Motor management timer (MMT)
Symbol PVOB PWOA PWOB
Output Output Output Input Output Input
Function
9-phase output 6-phase non-overlap
waveforms. W-phase output 6-phase non-overlap waveforms.
:-phase output 6-phase non-overlap
waveforms. Counter clear input external input. Output toggle synchronized with 6-phase non-overlap waveforms. Input signal requesting waveform output high-impedance state.
Serial communication Interface (SCI)/ smart card interface TxD2 TxD1 TxD0 RxD2 RxD1 RxD0 SCK2 SCK1 SCK0 HTxD HRxD converter AN11 AN10
Output
Data output pins
Input
Data input pins
Input/ Output Output Input Input
Clock input/output pins
HCAN
transmission reception Analog input pins
$'75*
AVCC
Input Input
input external trigger start conversion Power supply converter. When converter used, connect this system power supply (+5V). ground converter. Connect this system power supply (0V).
AVSS
Input
Rev. 2.0, 01/01, Page
Type ports
Symbol
Input/ Output
Function Eight input/output pins
Input
Eight input pins
Input
Four input pins
Input/ Output
Four input/output pins
ports
Input/ Output
Eight input/output pins
Input/ Output
Eight input/output pins
Rev. 2.0, 01/01, page
Type ports
Symbol
Input/ Output
Function Eight input/output pins
Input/ Output
Eight input/output pins
Rev. 2.0, 01/01, Page
Section
H8S/2600 high-speed central processing unit with internal 32-bit architecture that upward-compatible with H8/300 H8/300H CPUs. H8S/2600 sixteen 16-bit general registers, address 16-Mbyte linear address space, ideal realtime control. This section describes H8S/2600 CPU. usable modes address spaces differ depending product. details each product, refer section Operating Modes.
Features
Upward-compatible with H8/300 H8/300H CPUs execute H8/300 H8/300H CPUs object programs General-register architecture Sixteen 16-bit general registers also usable sixteen 8-bit registers eight 32-bit registers Sixty-nine basic instructions 8/16/32-bit arithmetic logic instructions Multiply divide instructions Powerful bit-manipulation instructions Multiply-and-accumulate instruction Eight addressing modes Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:16,ERn) @(d:32,ERn)] Register indirect with post-increment pre-decrement [@ERn+ @-ERn] Absolute address [@aa:8, @aa:16, @aa:24, @aa:32] Immediate [#xx:8, #xx:16, #xx:32] Program-counter relative [@(d:8,PC) @(d:16,PC)] Memory indirect [@@aa:8] 16-Mbyte address space Program: Mbytes Mbytes Data: High-speed operation frequently-used instructions execute states state 8/16/32-bit register-register add/subtract 8-bit register-register multiply states states 8-bit register-register divide 16-bit register-register multiply states 16-bit register-register divide states
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operating modes Normal mode* Advanced mode Power-down state Transition power-down state SLEEP instruction clock speed selection Note:* Normal mode available this LSI. 2.1.1 Differences between H8S/2600 H8S/2000
differences between H8S/2600 H8S/2000 shown below. Register configuration register supported H8S/2600 only. Basic instructions four instructions MAC, CLRMAC, LDMAC, STMAC supported H8S/2600 only. number execution states MULXU MULXS instructions;
Execution States Instruction MULXU Mnemonic MULXU.B MULXU.W MULXS MULXS.B MULXS.W H8S/2600 H8S/2000
addition, there differences address space, register functions, powerdown modes, etc., depending model.
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2.1.2
Differences from H8/300
comparison H8/300 CPU, H8S/2600 following enhancements: More general registers control registers Eight 16-bit expanded registers, 8-bit 32-bit control registers, have been added. Expanded address space Normal mode supports same 64-kbyte address space H8/300 CPU. Advanced mode supports maximum 16-Mbyte address space. Enhanced addressing addressing modes have been enhanced make effective 16-Mbyte address space. Enhanced instructions Addressing modes bit-manipulation instructions have been enhanced. Signed multiply divide instructions have been added. multiply-and-accumulate instruction been added. Two-bit shift instructions have been added. Instructions saving restoring multiple registers have been added. test instruction been added. Higher speed Basic instructions execute twice fast. 2.1.3 Differences from H8/300H
comparison H8/300H CPU, H8S/2600 following enhancements: Additional control register 8-bit 32-bit control registers have been added. Enhanced instructions Addressing modes bit-manipulation instructions have been enhanced. multiply-and-accumulate instruction been added. Two-bit shift instructions have been added. Instructions saving restoring multiple registers have been added. test instruction been added. Higher speed Basic instructions execute twice fast.
Rev. 2.0, 01/01, page
Operating Modes
H8S/2600 operating modes: normal advanced. Normal mode supports maximum 64-kbyte address space. Advanced mode supports maximum 16-Mbyte total address space. mode selected mode pins. 2.2.1 Normal Mode
exception vector table stack have same structure H8/300 CPU. Address Space maximum address space kbytes accessed. Extended Registers (En) extended registers used 16-bit registers, upper 16-bit segments 32-bit registers. When used 16-bit register contain value, even when corresponding general register (Rn) used address register. general register referenced register indirect addressing mode with pre-decrement (@-Rn) post-increment (@Rn+) carry borrow occurs, however, value corresponding extended register (En) will affected. Instruction instructions addressing modes used. Only lower bits effective addresses (EA) valid. Exception Vector Table Memory Indirect Branch Addresses normal mode area starting H'0000 allocated exception vector table. branch address stored bits. exception vector table differs depending microcontroller. details exception vector table, section Exception Handling. memory indirect addressing mode (@@aa:8) employed instructions uses 8-bit absolute address included instruction code specify memory operand that contains branch address. normal mode operand 16-bit word operand, providing 16-bit branch address. Branch addresses stored area from H'0000 H'00FF. Note that this area also used exception vector table. Stack Structure When program counter (PC) pushed onto stack subroutine call, condition-code register (CCR), extended control register (EXR) pushed onto stack exception handling, they stored shown figure 2-2. pushed onto stack interrupt control mode details, section Exception Handling. Note: Normal mode available this LSI.
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H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B
Reset exception vector (Reserved system use)
(Reserved system use)
Exception vector table
Exception vector Exception vector
Figure Exception Vector Table (Normal Mode)
bits)
EXR*1 Reserved*1,*3 CCR*3 bits)
Subroutine Branch Notes: When used stored stack. when used. lgnored when returning.
Exception Handling
Figure Stack Structure Normal Mode 2.2.2 Advanced Mode
Address Space Linear access provided 16-Mbyte maximum address space provided. Extended Registers (En) extended registers used 16-bit registers, upper 16-bit segments 32-bit registers address registers. Instruction instructions addressing modes used.
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Exception Vector Table Memory Indirect Branch Addresses advanced mode, area starting H'00000000 allocated exception vector table units bits. each bits, upper bits ignored branch address stored lower bits (figure 2-3). details exception vector table, section Exception Handling.
H'00000000 Reserved Exception vector H'00000003 H'00000004 Reserved Exception vector H'00000007 H'00000008 Reserved Exception vector table Exception vector H'0000000B H'0000000C Reserved Exception vector H'00000010 Reserved Exception vector
Figure Exception Vector Table (Advanced Mode) memory indirect addressing mode (@@aa:8) employed instructions uses 8-bit absolute address included instruction code specify memory operand that contains branch address. advanced mode operand 32-bit longword operand, providing 32-bit branch address. upper bits these bits reserved area that regarded H'00. Branch addresses stored area from H'00000000 H'000000FF. Note that first part this range also exception vector table. Stack Structure advanced mode, when program counter (PC) pushed onto stack subroutine call, condition-code register (CCR), extended control register (EXR) pushed onto stack exception handling, they stored shown figure 2-4. When invalid, pushed onto stack. details, section Exception Handling.
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Reserved bits)
EXR*1 Reserved*1, bits)
Subroutine Branch Notes: When used stored stack. when used. Ignored when returning.
Exception Handling
Figure Stack Structure Advanced Mode
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Address Space
Figure shows memory H8S/2600 CPU. H8S/2600 provides linear access maximum 64-kbyte address space normal mode, maximum 16-Mbyte (architecturally 4-Gbyte) address space advanced mode. usable modes address spaces differ depending product. details each product, refer section Operating Modes.
H'0000 64-kbyte H'FFFF H'00000000 16-Mbyte Program area
H'00FFFFFF
Data area
H'FFFFFFFF Normal Mode Advanced Mode
Figure Memory
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Register Configuration
H8S/2600 internal registers shown figure 2-6. There types registers; general registers control registers. control registers 24-bit program counter (PC), 8-bit extended control register (EXR), 8-bit condition code register (CCR), 64-bit multiply-accumulate register (MAC).
General Registers (Rn) Extended Registers (En)
(SP)
Control Registers (CR)
Sign extension MACL MACH
Legend
:Stack pointer :Program counter :Extended control register :Trace :Interrupt mask bits :Condition-code register :Interrupt mask :User interrupt mask :Half-carry flag :User :Negative flag :Zero flag :Overflow flag :Carry flag :Multiply-accumulate register
Figure Registers
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2.4.1
General Registers
H8S/2600 eight 32-bit general registers. These general registers functionally identical used both address registers data registers. When general register used data register, accessed 32-bit, 16-bit, 8-bit register. Figure illustrates usage general registers. When general registers used 32-bit registers address registers, they designated letters (ER0 ER7). registers divide into 16-bit general registers designated letters R7). These registers functionally equivalent, providing maximum sixteen 16-bit registers. registers also referred extended registers. registers divide into 8-bit general registers designated letters (R0H R7H) (R0L R7L). These registers functionally equivalent, providing maximum sixteen 8bit registers. usage each register selected independently. General register function stack pointer (SP) addition general-register function, used implicitly exception handling subroutine calls. Figure shows stack.
Address registers 32-bit registers 16-bit registers 8-bit registers
registers (extended registers) registers (ER0 ER7) registers registers (R0L R7L) registers (R0H R7H)
Figure Usage General Registers
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Free area (ER7)
Stack area
Figure Stack 2.4.2 Program Counter (PC)
This 24-bit counter indicates address next instruction will execute. length instructions bytes (one word), least significant ignored. (When instruction fetched, least significant regarded 2.4.3 Extended Control Register (EXR)
8-bit register that manipulates LDC, STC, ANDC, ORC, XORC instructions. When these instructions, except instruction, executed, interrupts including will masked three states after execution completed.
Name Initial Value Description Trace When this trace exception generated each time instruction executed. When this cleared instructions executed sequence.
Reserved They always read
These bits designate interrupt mask level details, refer section Interrupt Controller.
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2.4.4
Condition-Code Register (CCR)
This 8-bit register contains internal status information, including interrupt mask half-carry (H), negative (N), zero (Z), overflow (V), carry flags. Operations performed bits LDC, STC, ANDC, ORC, XORC instructions. flags used branching conditions conditional branch (Bcc) instructions.
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Name
Initial Value
Description Interrupt Mask Masks interrupts other than when accepted regardless setting. hardware start exception-handling sequence. details, refer section Interrupt Controller.
undefined
User Interrupt Mask written read software using LDC, STC, ANDC, ORC, XORC instructions. This cannot used interrupt mask this LSI.
undefined
Half-Carry Flag When ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, NEG.B instruction executed, this flag there carry borrow cleared otherwise. When ADD.W, SUB.W, CMP.W, NEG.W instruction executed, flag there carry borrow cleared otherwise. When ADD.L, SUB.L, CMP.L, NEG.L instruction executed, flag there carry borrow cleared otherwise.
undefined
User written read software using LDC, STC, ANDC, ORC, XORC instructions.
undefined
Negative Flag Stores value most significant data sign bit.
undefined
Zero Flag indicate zero data, cleared indicate non-zero data.
undefined
Overflow Flag when arithmetic overflow occurs, cleared other times.
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Name
Initial Value undefined
Description Carry Flag when carry occurs, cleared otherwise. Used instructions, indicate carry Subtract instructions, indicate borrow Shift rotate instructions, indicate carry
carry flag also used accumulator manipulation instructions.
2.4.5
Multiply-Accumulate Register (MAC)
This 64-bit register stores results multiply-and-accumulate operations. consists 32bit registers denoted MACH MACL. lower bits MACH valid; upper bits sign extension. 2.4.6 Initial Values Registers
Reset exception handling loads CPU's program counter (PC) from vector table, clears trace sets interrupt mask bits other bits general registers initialized. particular, stack pointer (ER7) initialized. stack pointer should therefore initialized MOV.L instruction executed immediately after reset.
Rev. 2.0, 01/01, Page
Data Formats
H8S/2600 process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), 32-bit (longword) data. Bit-manipulation instructions operate 1-bit data accessing byte operand data. decimal-adjust instructions treat byte data digits 4-bit data. 2.5.1 General Register Data Formats
Figure shows data formats general registers.
Data Type
1-bit data
Register Number
Data Format
Don't care
1-bit data Don't care
4-bit data Upper
Lower
Don't care
4-bit data Don't care Upper
Lower
Byte data
Don't care
Byte data
Don't care
Figure General Register Data Formats
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Data Type Word data
Register Number
Data Format
Word data
Longword data
Legend
General register General register General register General register General register Least significant
Most significant
Figure General Register Data Formats
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2.5.2
Memory Data Formats
Figure 2-10 shows data formats memory. H8S/2600 access word data longword data memory, however word longword data must begin even address. attempt made access word longword data address, address error does occur, however least significant address regarded access begins preceding address. This also applies instruction fetches. When used address register access stack, operand size should word longword.
Data Type Address
1-bit data Address
Data Format
Byte data
Address
Word data
Address Address 2M+1
Longword data
Address Address 2N+1 Address 2N+2 Address 2N+3
Figure 2-10 Memory Data Formats
Rev. 2.0, 01/01, page
Instruction
H8S/2600 instructions. instructions classified function table 2-1. Table
Function Data transfer
Instruction Classification
Instructions POP* PUSH* LDM, SMOVFPE* MOVTPE*
Size B/W/L B/W/L B/W/L B/W/L
Types
Arithmetic operations
ADD, SUB, CMP, ADDX, SUBX, DAA, INC, ADDS, SUBS MULXU, DIVXU, MULXS, DIVXS EXTU, EXTS TAS*
MAC, LDMAC, STMAC, CLRMAC Logic operations Shift manipulation Branch System control AND, XOR,
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR B/W/L BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR Bcc* JMP, BSR, JSR,
TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC,
Block data transfer EEPMOV
Total: Notes: B-byte; W-word; L-longword. POP.W PUSH.W identical MOV.W @SP+, MOV.W @-SP. POP.L PUSH.L identical MOV.L @SP+, MOV.L ERn, @-SP. general name conditional branch instructions. Cannot used this LSI. Only register ER0, ER1, ER4, should used when using instruction.
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2.6.1
Table Instructions Classified Function
Tables 2.10 summarizes instructions each functional category. notation used tables 2-10 defined below. Table Operation Notation
Symbol (EAd) (EAs) #IMM disp :8/:16/:24/:32 Description General register (destination)* General register (source)* General register* General register (32-bit register) Multiply-accumulate register (32-bit register) Destination operand Source operand Extended control register Condition-code register (negative) flag (zero) flag (overflow) flag (carry) flag Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division Logical Logical Logical Move (logical complement) 16-, 24-, 32-bit length
Note: General registers include 8-bit registers (R0H R7H, R7L), 16-bit registers E7), 32-bit registers (ER0 ER7).
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Table
Instruction
Data Transfer Instructions
Size* B/W/L Function (EAs) (EAd) Moves data between general registers between general register memory, moves immediate data general register. Cannot used this LSI. Cannot used this LSI. @SP+ Pops general register from stack. POP.W identical MOV.W @SP+, POP.L identical MOV.L @SP+, ERn. @-SP Pushes general register onto stack. PUSH.W identical MOV.W @-SP. PUSH.L identical MOV.L ERn, @-SP. @SP+ (register list) Pops more general registers from stack. (register list) @-SP Pushes more general registers onto stack.
MOVFPE MOVTPE
PUSH
S
Note: Refers operand size. Byte Word Longword
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Table
Instruction
Arithmetic Operations Instructions
Size* B/W/L Function #IMM Performs addition subtraction data general registers, immediate data data general register (immediate byte data cannot subtracted from byte data general register. SUBX instruction.) #IMM Performs addition subtraction with carry byte data general registers, immediate data data general register. Increments decrements general register (Byte operands incremented decremented only.) Adds subtracts value from data 32-bit register. decimal adjust Decimal-adjusts addition subtraction result general register referring produce 4-bit data. Performs unsigned multiplication data general registers: either bits bits bits bits bits bits. Performs signed multiplication data general registers: either bits bits bits bits bits bits. Performs unsigned division data general registers: either bits bits 8-bit quotient 8-bit remainder bits bits 16-bit quotient 16-bit remainder.
ADDX SUBX ADDS SUBS MULXU
B/W/L
MULXS
DIVXU
Note: Refers operand size. Byte Word Longword
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Table
Instruction DIVXS
Arithmetic Operations Instructions
Size*
Function Performs signed division data general registers: either bits bits 8-bit quotient 8-bit remainder bits bits 16-bit quotient 16-bit remainder. #IMM Compares data general register with data another general register with immediate data, sets bits according result. Takes two's complement (arithmetic complement) data general register. (zero extension) Extends lower bits 16-bit register word size, lower bits 32-bit register longword size, padding with zeros left. (sign extension) Extends lower bits 16-bit register word size, lower bits 32-bit register longword size, extending sign bit. @ERd (<bit @ERd) Tests memory contents, sets most significant (bit (EAs) (EAd) Performs signed multiplication memory contents adds result multiply-accumulate register. following operations performed: bits bits bits bits, saturating bits bits bits bits, non-saturating Clears multiply-accumulate register zero. MAC, Transfers data between general register multiply-accumulate register.
B/W/L
B/W/L
EXTU
EXTS
TAS*
CLRMAC LDMAC STMAC Note:
Refers operand size. Byte Word Longword Only register ER0, ER1, ER4, should used when using instruction.
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Table
Instruction
Logic Operations Instructions
Size* B/W/L Function #IMM Performs logical operation general register another general register immediate data. #IMM Performs logical operation general register another general register immediate data. #IMM Performs logical exclusive operation general register another general register immediate data. (Rd) (Rd) Takes one's complement general register contents.
B/W/L
B/W/L
B/W/L
Note: Refers operand size. Byte Word Longword
Table
Instruction SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR
Shift Instructions
Size* B/W/L Function (shift) Performs arithmetic shift general register contents. 1-bit 2-bit shifts possible. (shift) Performs logical shift general register contents. 1-bit 2-bit shifts possible. (rotate) Rotates general register contents. 1-bit 2-bit rotations possible. (rotate) Rotates general register contents through carry flag. 1-bit 2-bit rotations possible.
B/W/L
B/W/L
B/W/L
Note: Refers operand size. Byte Word Longword
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Table
Instruction BSET
Manipulation Instructions
Size* Function (<bit-No.> <EAd>) Sets specified general register memory operand number specified 3-bit immediate data lower three bits general register. (<bit-No.> <EAd>) Clears specified general register memory operand number specified 3-bit immediate data lower three bits general register. (<bit-No.> <EAd>) (<bit-No.> <EAd>) Inverts specified general register memory operand. number specified 3-bit immediate data lower three bits general register. (<bit-No.> <EAd>) Tests specified general register memory operand sets clears flag accordingly. number specified 3-bit immediate data lower three bits general register. (<bit-No.> <EAd>) ANDs carry flag with specified general register memory operand stores result carry flag. (<bit-No.> <EAd>) ANDs carry flag with inverse specified general register memory operand stores result carry flag. number specified 3-bit immediate data. (<bit-No.> <EAd>) carry flag with specified general register memory operand stores result carry flag. (<bit-No.> <EAd>) carry flag with inverse specified general register memory operand stores result carry flag. number specified 3-bit immediate data.
BCLR
BNOT
BTST
BAND
BIAND
BIOR
Note: Refers operand size. Byte
Rev. 2.0, 01/01, Page
Table
Instruction BXOR
Manipulation Instructions
Size*
Function (<bit-No.> <EAd>) XORs carry flag with specified general register memory operand stores result carry flag. (<bit-No.> <EAd>) XORs carry flag with inverse specified general register memory operand stores result carry flag. number specified 3-bit immediate data. (<bit-No.> <EAd>) Transfers specified general register memory operand carry flag. (<bit-No.> <EAd>) Transfers inverse specified general register memory operand carry flag. number specified 3-bit immediate data. (<bit-No.> <EAd>) Transfers carry flag value specified general register memory operand. (<bit-No.> <EAd>) Transfers inverse carry flag value specified general register memory operand. number specified 3-bit immediate data.
BIXOR
BILD
BIST
Note: Refers operand size. Byte
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Table
Instruction
Branch Instructions
Size Function Branches specified address specified condition true. branching conditions listed below. Mnemonic BRA(BT) BRN(BF) BCC(BHS) BCS(BLO) Description Always (true) Never (false) High same Carry clear (high same) Carry (low) equal Equal Overflow clear Overflow Plus Minus Greater equal Less than Greater than Less equal Condition Always Never CZ=0 CZ=1 NV=0 NV=1
Branches unconditionally specified address. Branches subroutine specified address. Branches subroutine specified address. Returns from subroutine
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Table
Instruction TRAPA SLEEP
System Control Instructions
Size* Function Starts trap-instruction exception handling. Returns from exception-handling routine. Causes transition power-down state. (EAs) CCR, (EAs) Moves source operand contents immediate data EXR. Although 8-bit registers, word-size transfers performed between them memory. upper bits valid. (EAd), (EAd) Transfers contents general register memory. Although 8-bit registers, word-size transfers performed between them memory. upper bits valid. #IMM CCR, #IMM Logically ANDs contents with immediate data. #IMM CCR, #IMM Logically contents with immediate data. #IMM CCR, #IMM Logically XORs contents with immediate data. Only increments program counter.
ANDC XORC
Note: Refers operand size. Byte Word Longword
Rev. 2.0, 01/01, page
Table 2-10 Block Data Transfer Instructions
Instruction EEPMOV.B Size* Function then Repeat @ER5+ @ER6+ R4L-1 Until else next; then Repeat @ER5+ @ER6+ R4-1 Until else next; Transfers data block. Starting from address ER5, transfers data number bytes address location ER6. Execution next instruction begins soon transfer completed. Notes: Refers operand size. Byte Word Longword
EEPMOV.W
2.6.2
Basic Instruction Formats
This instructions consist 2-byte (1-word) units. instruction consists operation field field), register field field), effective address extension field), condition field (cc). Figure 2-11 shows examples instruction formats.
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Operation Field Indicates function instruction, addressing mode, operation carried operand. operation field always includes first four bits instruction. Some instructions have operation fields. Register Field Specifies general register. Address registers specified bits, data registers bits bits. Some instructions have register fields. Some have register field. Effective Address Extension bits specifying immediate data, absolute address, displacement. Condition Field Specifies branching condition instructions.
Operation field only NOP, RTS, etc.
Operation field register fields ADD.B etc.
Operation field, register fields, effective address extension EA(disp) MOV.B @(d:16, Rn), etc.
Operation field, effective address extension, condition field EA(disp) d:16, etc.
Figure 2-11 Instruction Formats (Examples)
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Addressing Modes Effective Address Calculation
H8S/2600 supports eight addressing modes listed table 2-11. Each instruction uses subset these addressing modes. Arithmetic logic instructions register direct immediate modes. Data transfer instructions addressing modes except programcounter relative memory indirect. manipulation instructions register direct, register indirect, absolute addressing mode specify operand, register direct (BSET, BCLR, BNOT, BTST instructions) immediate (3-bit) addressing mode specify number operand. Table 2-11 Addressing Modes
Addressing Mode Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect Symbol @ERn @(d:16,ERn)/@(d:32,ERn) @ERn+ @-ERn @aa:8/@aa:16/@aa:24/@aa:32 #xx:8/#xx:16/#xx:32 @(d:8,PC)/@(d:16,PC) @@aa:8
2.7.1
Register Direct-Rn
register field instruction specifies 16-, 32-bit general register containing operand. specified 8-bit registers. specified 16-bit registers. specified 32-bit registers. 2.7.2 Register Indirect-@ERn
register field instruction code specifies address register (ERn) which contains address operand memory. address program instruction address, lower bits valid upper bits assumed (H'00). 2.7.3 Register Indirect with Displacement-@(d:16, ERn) @(d:32, ERn)
16-bit 32-bit displacement contained instruction added address register (ERn) specified register field instruction, gives address memory operand. 16-bit displacement sign-extended when added.
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2.7.4
Register Indirect with Post-Increment Pre-Decrement-@ERn+ @-ERn
Register indirect with post-increment-@ERn+: register field instruction code specifies address register (ERn) which contains address memory operand. After operand accessed, added address register contents stored address register. value added byte access, word transfer instruction, longword transfer instruction. word longword transfer instructions, register value should even. Register indirect with pre-decrement-@-ERn: value subtracted from address register (ERn) specified register field instruction code, result address memory operand. result also stored address register. value subtracted byte access, word transfer instruction, longword transfer instruction. word longword transfer instructions, register value should even. 2.7.5 Absolute Address-@aa:8, @aa:16, @aa:24, @aa:32
instruction code contains absolute address memory operand. absolute address bits long (@aa:8), bits long (@aa:16), bits long (@aa:24), bits long (@aa:32). Table 2-12 indicates accessible absolute address ranges. access data, absolute address should bits (@aa:8), bits (@aa:16), bits (@aa:32) long. 8-bit absolute address, upper bits assumed (H'FFFF). 16-bit absolute address upper bits sign extension. 32-bit absolute address access entire address space. 24-bit absolute address (@aa:24) indicates address program instruction. upper bits assumed (H'00). Table 2-12 Absolute Address Access Ranges
Absolute Address Data address bits (@aa:8) bits (@aa:16) bits (@aa:32) Program instruction address bits (@aa:24) Normal Mode* H'FF00 H'FFFF H'0000 H'FFFF Advanced Mode H'FFFF00 H'FFFFFF H'000000 H'007FFF, H'FF8000 H'FFFFFF H'000000 H'FFFFFF
Note: Normal mode available this LSI.
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2.7.6
Immediate-#xx:8, #xx:16, #xx:32
instruction contains 8-bit (#xx:8), 16-bit (#xx:16), 32-bit (#xx:32) immediate data operand. ADDS, SUBS, INC, instructions contain immediate data implicitly. Some manipulation instructions contain 3-bit immediate data instruction code, specifying number. TRAPA instruction contains 2-bit immediate data instruction code, specifying vector address. 2.7.7 Program-Counter Relative-@(d:8, @(d:16,
This mode used instructions. 8-bit 16-bit displacement contained instruction sign-extended added 24-bit contents generate branch address. Only lower bits this branch address valid; upper bits assumed (H'00). value which displacement added address first byte next instruction, possible branching range -126 +128 bytes (-63 words) -32766 +32768 bytes (-16383 +16384 words) from branch instruction. resulting value should even number. 2.7.8 Memory Indirect-@@aa:8
This mode used instructions. instruction code contains 8-bit absolute address specifying memory operand. This memory operand contains branch address. upper bits absolute address assumed address range (H'0000 H'00FF normal mode, H'000000 H'0000FF advanced mode). normal mode, memory operand word operand branch address bits long. advanced mode, memory operand longword operand, first byte which assumed (H'00). Note that first part address range also exception vector area. further details, refer section Exception Handling. address specified word longword memory access, branch address, least significant regarded causing data accessed instruction code fetched address preceding specified address. (For further information, section 2.5.2, Memory Data Formats.) Note: Normal mode available this LSI.
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Specified @aa:8
Branch address
Specified @aa:8
Reserved Branch address
Normal Mode*
Note: Normal mode available this LSI.
Advanced Mode
Figure 2-12 Branch Address Specification Memory Indirect Mode 2.7.9 Effective Address Calculation
Table 2-13 indicates effective addresses calculated each addressing mode. normal mode upper bits effective address ignored order generate 16-bit address. Note Normal mode available this LSI.
Rev. 2.0, 01/01, page
Table 2-13 Effective Address Calculation
Addressing Mode Instruction Format
Register direct(Rn)
Effective Address Calculation
Effective Address (EA)
Operand general register contents.
General register contents
Register indirect(@ERn)
Don't care
Register indirect with displacement @(d:16,ERn) @(d:32,ERn)
General register contents
disp
Sign extension
Don't care disp
Register indirect with post-increment pre-decrement indirect with post-increment @ERn+
General register contents
Don't care
indirect with pre-decrement @-ERn
General register contents
Don't care
Operand Size Byte Word Longword
Offset
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Table 2-13 Effective Address Calculation
Addressing Mode Instruction Format
Absolute address
Effective Address Calculation
Effective Address (EA)
@aa:8
H'FFFF
Don't care
@aa:16
Don't care Sign extension
@aa:24
Don't care
@aa:32
Don't care
Immediate
#xx:8/#xx:16/#xx:32
Operand immediate data.
Program-counter relative @(d:8,PC) @(d:16,PC)
contents
disp
Sign extension
disp
Don't care
Memory indirect @@aa:8 Normal mode*
H'000000
Memory contents
H'00
Don't care
Advanced mode
Memory contents
H'000000
Don't care
Note: Normal mode available this LSI.
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Processing States
H8S/2600 five main processing states: reset state, exception handling state, program execution state, bus-released state, power-down state. Figure 2-14 shows diagram processing states. Figure 2-13 indicates state transitions. Reset State this state, on-chip peripheral modules initialized operating. When input goes low, current processing stops enters reset state. interrupts masked reset state. Reset exception handling starts when signal changes from high. details, refer section Exception Handling. reset state also entered watchdog timer overflow. Exception-Handling State exception-handling state transient state that occurs when alters normal processing flow exception source, such reset, trace, interrupt, trap instruction. fetches start address (vector) from exception vector table branches that address. further details, refer section Exception Handling. Program Execution State this state, executes program instructions sequence. Bus-Released State product which master other than CPU, such data transfer controller (DTC), bus-released state occurs when been released response request from master other than CPU. While released, halts operations. Program stop state This power-down state which stops operating. program stop state occurs when SLEEP instruction executed enters hardware standby mode. further details, refer section Power-Down Modes.
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Reset state*
Exception handling state
reqterru
Bus-released state
Request exception handling
exception handling
request
request
eque
SLEEP instruction Program halt state
Program execution state
Notes: From state, transition hardware standby mode occurs when goes low. From state except hardware standby mode, transition reset state occurs whenever goes low. transition also made reset state when watchdog timer overflows.
Figure 2-13 State Transitions
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Section Operating Modes
Operating Mode Selection
This supports only operating mode that advanced single-chip mode. operating mode determined setting mode pins (MD2 MD0). Only mode used this LSI. Therefore, mode pins must fixed high, shown table 3-1. change mode settings during operation. Table Operating Mode Selection
External Data On-Chip Initial Width Enabled Max. Width
Operating Operating Mode Mode Description Advanced Single-chip mode mode
Register Descriptions
following registers related operating mode. details register addresses register states during each processing, refer appendix Internal Register. Mode control register(MDCR) System control register(SYSCR) 3.2.1
Mode Control Register(MDCR)
Name Intial Value Descriptions Reserved Only should written this bit. Reserved These bits always read cannot modified. These bits indicate input levels pins (the current operating mode). Bits MDS2 MDS0 correspond MD0. MDS2 MDS0 readonly bits they cannot written mode (MD2 MD0) input levels latched into these bits when MDCR read. These latches canceled reset. These latches canceled reset.
MDS2 MDS1 MDS0
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3.2.2
System Control Register(SYSCR)
SYSCR 8-bit readable/writable register that selects saturating non-saturating calculation instruction, selects interrupt control mode detected edge NMI, enables disables on-chip RAM.
Name MACS Intial Value Descriptions Saturation Selects either saturating non-saturating calculation instruction. Non-saturating calculation instruction Saturating calculation instruction Reserved This always read cannot modified. These bits select control mode interrupt controller. details interrupt control modes, section 5.6, Interrupt Control Modes Interrupt Operation. Interrupt control mode Setting prohibited Interrupt control mode Setting prohibited Edge Select Selects valid edge interrupt input. interrupt requested falling edge input interrupt requested rising edge input Reserved These bits always read cannot modified. Enable Enables disables on-chip RAM. RAME initialized when reset status released. On-chip disabled On-chip enabled
INTM1 INTM0
NMIEG
RAME
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Functions Each Operating Mode
access 16-Mbyte address space advanced mode. on-chip enabled, however external addresses cannot accessed. ports available input-output ports. 3.3.1 Functions
Table shows their functions mode Table
Port Port Port Port Port Port Port Legend port Address output Data Control signals, clock After reset
Functions Each Mode
Mode P*/C
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Address
Figure shows address each operating mode.
H8S/2612 ROM: kbytes, RAM: kbytes Mode Advanced single-chip mode H'000000 H'000000 H8S/2611 ROM: kbytes, RAM: kbytes Mode Advanced single-chip mode
On-chip (MASK ROM*)
H'00FFFF On-chip (F-ZTAT/MASK ROM*)
H'01FFFF
H'01FFFF
H'FFE000 On-chip H'FFEFBF
H'FFE000 On-chip H'FFEFBF
H'FFF800 Internal registers H'FFFF3F
H'FFF800 Internal registers H'FFFF3F
H'FFFF60 Internal registers H'FFFFBF H'FFFFC0 On-chip H'FFFFFF
H'FFFF60 H'FFFFBF H'FFFFC0 On-chip H'FFFFFF Internal registers
Note planning
Figure Address
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Section Exception Handling
Exception Handling Types Priority
table indicates, exception handling caused reset, trap instruction, interrupt. Exception handling prioritized shown table 4-1. more exceptions occur simultaneously, they accepted processed order priority. Exception sources, stack structure, operation vary depending interrupt control mode. details interrupt control mode, refer section Interrupt Controller. Table
Priority High
Exception Types Priority
Exception Type Reset Start Exception Handling Starts immediately after low-to-high transition pin, when watchdog timer overflows. enters reset state when low.
Trace*
Starts when execution current instruction exception handling ends, trace Starts when direction transition occurs result SLEEP instruction execution. Starts when execution current instruction exception handling ends, interrupt request been issued*
Direct transition Interrupt Trap instruction
Started execution trap instruction (TRAPA)
Notes: Traces enabled only interrupt control mode Trace exception handling executed after execution instruction. Interrupt detection performed completion ANDC, ORC, XORC, instruction execution, completion reset exception handling. Trap instruction exception handling requests accepted times program execution state.
Exception Sources Exception Vector Table
Different vector addresses assigned different exception sources. Table lists exception sources their vector addresses. Since usable modes differ depending product, details each product, refer section Operating Modes.
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Table
Exception Handling Vector Table
Vector Address*
Exception Source Power-on reset Manual reset
Vector Number
Normal Mode H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0019 H'000A H'000B H'000C H'000D H'000E H'000F H'0010 H'0011 H'0012 H'0013 H'0014 H'0015 H'0016 H'0017 H'0018 H'0019 H'001A H'001B H'001C H'001D H'001E H'001F H'0020 H'0021 H'0022 H'0023 H'0024 H'0025 H'0026 H'0027 H'0028 H'0029 H'002A H'002B H'002C H'002D H'002E H'002F H'0030 H'0031 H'00FE H'00FF
Advanced Mode H'0000 H'0003 H'0004 H'0007 H'0008 H'000B H'000C H'000F H'0010 H'0013 H'0014 H'0017 H'0018 H'001B H'001C H'001F H'0020 H'0023 H'0024 H'0027 H'0028 H'002B H'002C H'002F H'0030 H'0033 H'0034 H'0037 H'0038 H'003B H'003C H'003F H'0040 H'0043 H'0044 H'0047 H'0048 H'004B H'004C H'004F H'0050 H'0053 H'0054 H'0057 H'0058 H'005B H'005C H'005F H'0060 H'0063 H'01FC H'01FF
Reserved system
Trace
Interrupt (direct transitions)* Interrupt (NMI) Trap instruction (#0) (#1) (#2) (#3) Reserved system External interrupt IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 Reserved system
Internal interrupt*
Notes: Lower bits address. available this LSI. details internal interrupt vectors, section 5.5, Interrupt Exception Handling Vector Table.
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Reset
reset highest exception priority. When goes low, processing halts this enters reset. ensure that this reset, hold least power-up. reset chip during operation, hold least states. reset initializes internal state registers on-chip supporting modules. chip also reset overflow watchdog timer. details section Watchdog Timer. interrupt control mode immediately after reset. 4.3.1 Reset Exception Handling
When goes high after being held necessary time, this starts reset exception handling follows: internal state registers on-chip supporting modules initialized, cleared EXR, CCR. reset exception handling vector address read transferred program execution starts from address indicated
Figures show examples reset sequence.
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Vector fetch
Prefetch first Internal processing program instruction
Internal address
Internal read signal
Internal write signal Internal data
High
(1)(3) Reset exception handling vector address(when reset, (1)=H'000000, (3)=H'000002) (2)(4) Start address (contents reset exception handling vector address) Start address ((5)=(2)(4)) First program instruction
Figure Reset Sequence (Advanced Mode with On-chip Enabled)
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Vector fetch
Internal processing
Prefetch first program instruction
Address
High
(1)(3) Reset exception handling vector address(when reset, (1)=H'000000, (3)=H'000002) (2)(4) Start address (contents reset exception handling vector address) Start address ((5)=(2)(4)) First program instruction Note: Three program wait states inserted.
Figure Reset Sequence (Advanced Mode with On-chip Disabled: Cannot Used this LSI) 4.3.2 Interrupts after Reset
interrupt accepted after reset before stack pointer (SP) initialized, will saved correctly, leading program crash. prevent this, interrupt requests, including NMI, disabled immediately after reset. Since first instruction program always executed immediately after reset state ends, make sure that this instruction initializes stack pointer (example: MOV.L #xx: SP). 4.3.3 State On-Chip Supporting Modules after Reset Release
After reset release, MSTPCRA MSTPCRC initialized H'3F, H'FF, H'FF, respectively, modules except enter module stop mode. Consequently, on-chip supporting module registers cannot read written Register reading writing enabled when module stop mode exited.
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Traces
Traces enabled interrupt control mode Trace mode activated interrupt control mode irrespective state bit. details interrupt control modes, section Interrupt Controller. trace mode activated. trace mode, trace exception occurs completion each instruction. Trace mode affected interrupt masking. Table shows state after execution trace exception handling. Trace mode canceled clearing saved stack retains value when control returned from trace exception handling routine instruction, trace mode resumes. Trace exception handling carried after execution instruction. Interrupts accepted even within trace exception handling routine. Table Status after Trace Exception Handling
Interrupt Control Mode Legend Cleared Retains value prior execution
Trace exception handling cannot used.
Interrupts
Interrupts controlled interrupt controller. interrupt controller interrupt control modes assign interrupts other than eight priority/mask levels enable multiplexed interrupt control. source start interrupt exception handling vector address differ depending product. details, refer section Interrupt Controller. Interrupt exception handling conducted follows: values program counter (PC), condition code register (CCR), extended control register (EXR) saved stack. interrupt mask updated cleared vector address corresponding interrupt source generated, start address loaded from vector table program execution begins from that address.
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Trap Instruction
Trap instruction exception handling starts when TRAPA instruction executed. Trap instruction exception handling executed times program execution state. Trap instruction exception handling conducted follows: values program counter (PC), condition code register (CCR), extended control register (EXR) saved stack. interrupt mask updated cleared. vector address corresponding interrupt source generated, start address loaded from vector table program execution starts from that address. TRAPA instruction fetches start address from vector table entry corresponding vector number from specified instruction code. Table shows status after execution trap instruction exception handling. Table Status after Trap Instruction Exception Handling
Interrupt Control Mode
Legend Cleared Retains value prior execution
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Stack Status after Exception Handling
Figures shows stack after completion trap instruction exception handling interrupt exception handling.
Normal Modes*2
Reserved*1
CCR*1 PC(16 bits)
CCR*1 PC(16 bits)
Interrupt control mode
Interrupt control mode
Advanced Modes
Reserved*1
PC(24 bits)
PC(24 bits)
Interrupt control mode Note: Ignored return. Normal modes available this LSI.
Interrupt control mode
Figure Stack Status after Exception Handling
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Usage Note
When accessing word data longword data, this assumes that lowest address stack should always accessed word transfer instruction longword transfer instruction, value stack pointer (SP, ER7) should always kept even. following instructions save registers:
PUSH.W PUSH.L MOV.W @-SP) MOV.L ERn, @-SP)
following instructions restore registers:
POP.W POP.L MOV.W @SP+, MOV.L @SP+, ERn)
Setting value lead malfunction. Figure shows example what happens when value odd.
Address
H'FFFEFA H'FFFEFB
H'FFFEFC H'FFFEFD H'FFFEFE
H'FFFEFF
H'FFFEFF
TRAP instruction executed Data saved above
MOV.B R1L, @-ER7 executed Contents lost
Legend Condition code register Program counter General register Stack pointer
Note: This diagram illustrates example which interrupt control mode advanced mode.
Figure Operation when Value
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Section Interrupt Controller
Features
interrupt control modes interrupt control modes means INTM1 INTM0 bits system control register (SYSCR). Priorities settable with interrupt priority register (IPR) provided setting interrupt priorities. Eight priority levels each module interrupts except NMI. assigned highest priority level accepted times. Independent vector addresses interrupt sources assigned independent vector addresses, making unnecessary source identified interrupt handling routine. Seven external interrupts highest-priority interrupt, accepted times. Rising edge falling edge selected NMI. Falling edge, rising edge, both edge detection, level sensing, selected IRQ0 IRQ5. control activated interrupt request.
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block diagram interrupt controller shown figure 5-1.
INTM1, INTM0 SYSCR NMIEG input input input unit input unit ISCR Priority determination Interrupt request Vector number
Internal interrupt request SWDTEND TEI2
Interrupt controller Legend ISCR sense control register enable register status register Interrupt priority register SYSCR System control register
Figure Block Diagram Interrupt Controller
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Input/Output Pins
Table summarizes pins interrupt controller. Table
Name
Configuration
Input Input Input Input Input Input Input Function Nonmaskable external interrupt Rising falling edge selected Maskable external interrupts Rising, falling, both edges, level sensing, selected
Register Descriptions
interrupt controller following registers. details register addresses register states during each process, refer appendix Internal Register. System control register (SYSCR) sense control register (ISCRH) sense control register (ISCRL) enable register (IER) status register (ISR) Interrupt priority register (IPRA) Interrupt priority register (IPRB) Interrupt priority register (IPRC) Interrupt priority register (IPRD) Interrupt priority register (IPRE) Interrupt priority register (IPRF) Interrupt priority register (IPRG) Interrupt priority register (IPRH) Interrupt priority register (IPRJ) Interrupt priority register (IPRK) Interrupt priority register (IPRM)
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5.3.1
Interrupt Priority Registers (IPRA IPRH,IPRJ, IPRK, IPRM)
registers eleven 8-bit readable/writable registers that priorities (levels interrupts other than NMI. correspondence between interrupt sources settings shown table (Interrupt Sources, Vector Addresses, Interrupt Priorities). Setting value range from 3-bit groups bits sets priority corresponding interrupt.
Name Initial Value Description Reserved These bits always read IPR6 IPR5 IPR4 Sets priority corresponding interrupt source. 000: Priority level (Lowest) 001: Priority level 010: Priority level 011: Priority level 100: Priority level 101: Priority level 110: Priority level 111: Priority level (Highest)
IPR2 IPR1 IPR0
Reserved These bits always read Sets priority corresponding interrupt source. 000: Priority level (Lowest) 001: Priority level 010: Priority level 011: Priority level 100: Priority level 101: Priority level 110: Priority level 111: Priority level (Highest)
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5.3.2
Enable Register (IER)
8-bit readable/writable register that controls enabling disabling interrupt requests IRQ0 IRQ5.
Name Initial Value Description Reserved Only should written these bits. IRQ5 Enable IRQ5 interrupt request enabled when this IRQ4E IRQ4 Enable IRQ4 interrupt request enabled when this IRQ3E IRQ3 Enable IRQ3 interrupt request enabled when this IRQ2E IRQ2 Enable IRQ2 interrupt request enabled when this IRQ1E IRQ1 Enable IRQ1 interrupt request enabled when this IRQ0E IRQ0 Enable IRQ0 interrupt request enabled when this
IRQ5E
5.3.3
Sense Control Registers (ISCRH, ISCRL)
ISCR registers 16-bit readable/writable registers that select source that generates interrupt request pins ,54.
Rev. 2.0, 01/01, page
Name
Initial Value
Description Reserved Only should written these bits.
IRQ5SCB IRQ5SCA
IRQ5 Sense Control IRQ5 Sense Control Interrupt request generated input level Interrupt request generated falling edge input Interrupt request generated rising edge input Interrupt request generated both falling rising edges input
IRQ4SCB IRQ4SCA
IRQ4 Sense Control IRQ4 Sense Control Interrupt request generated input level Interrupt request generated falling edge input Interrupt request generated rising edge input Interrupt request generated both falling rising edges input
IRQ3SCB IRQ3SCA
IRQ3 Sense Control IRQ3 Sense Control Interrupt request generated input level Interrupt request generated falling edge input Interrupt request generated rising edge input Interrupt request generated both falling rising edges input
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Name IRQ2SCB IRQ2SCA
Initial Value
Description IRQ2 Sense Control IRQ2 Sense Control Interrupt request generated input level Interrupt request generated falling edge input Interrupt request generated rising edge input Interrupt request generated both falling rising edges input
IRQ1SCB IRQ1SCA
IRQ1 Sense Control IRQ1 Sense Control Interrupt request generated input level Interrupt request generated falling edge input Interrupt request generated rising edge input Interrupt request generated both falling rising edges input
IRQ0SCB IRQ0SCA
IRQ0 Sense Control IRQ0 Sense Control Interrupt request generated input level Interrupt request generated falling edge input Interrupt request generated rising edge input Interrupt request generated both falling rising edges input
5.3.4
Status Register (ISR)
8-bit readable/writable register that indicates status IRQ0 IRQ5 interrupt requests.
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Name
Initial Value
Description Reserved Only should written these bits. [Setting conditions] When interrupt source selected ISCR registers occurs [Clearing conditions] Cleared reading IRQnF flag when IRQnF then writing IRQnF flag When interrupt exception handling executed when low-level detection ,54Q input high When IRQn interrupt exception handling executed when falling, rising, both-edge detection When activated IRQn interrupt, DISEL cleared (n=5
IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F
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5.4.1
Interrupt
External Interrupts
There seven external interrupts: IRQ0 IRQ5. These interrupts used restore this from software standby mode. Interrupt: highest-priority interrupt, always accepted regardless interrupt control mode status interrupt mask bits. NMIEG SYSCR used select whether interrupt requested rising edge falling edge pin. IRQ0 IRQ5 Interrupts: Interrupts IRQ0 IRQ5 requested input signal pins ,54. Interrupts IRQ0 IRQ5 have following features: Using ISCR, possible select whether interrupt generated level, falling edge, rising edge, both edges, pins ,54. Enabling disabling interrupt requests IRQ0 IRQ5 selected with IER. interrupt priority level with IPR. status interrupt requests IRQ0 IRQ5 indicated ISR. flags cleared software. detection IRQ0 IRQ5 interrupts does depend whether relevant been input output. However, when used external interrupt input pin, clear corresponding another function. block diagram interrupts IRQ0 IRQ5 shown figure 5-2.
IRQnE IRQnSCA, IRQnSCB IRQnF Edge level detection circuit input IRQn interrupt request
Clear signal Note:
Figure Block Diagram Interrupts IRQ0 IRQ5
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5.4.2
Internal Interrupts
sources internal interrupts from on-chip supporting modules have following features: each on-chip supporting module there flags that indicate interrupt request status, enable bits that select enabling disabling these interrupts. both these particular interrupt source, interrupt request issued interrupt controller. interrupt priority level means IPR. activated TPU, SCI, other interrupt request. When activated interrupt request, affected interrupt control mode interrupt mask bit.
Interrupt Exception Handling Vector Table
Table shows interrupt exception handling sources, vector addresses, interrupt priorities. default priorities, lower vector number, higher priority. Priorities among modules means IPR. Modules same priority will conform their default priorities. Priorities within module fixed.
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Table
Interrupt Sources, Vector Addresses, Interrupt Priorities
Vector Address*
Interrupt Source External
Origin Interrupt Source IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5
Vector Number
Advanced Mode H'001C H'0040 H'0044 H'0048 H'004C H'0050 H'0054 H'0058 H'005C H'0060 H'0064 H'006C H'0070 H'0080 H'0084 H'0088 H'008C H'0090 H'00A0 H'00A4 H'00A8 H'00AC H'00B0 H'00B4 H'00B8 H'00BC
IPRA6 IPRA4 IPRA2 IPRA0 IPRB6 IPRB4 IPRB2 IPRB0
Priority High
Reserved system Reserved system
Watchdog timer break channel
SWDTEND WOVI0 break TGIA_0 TGIB_0 TGIC_0 TGID_0 TCIV_0
IPRC2 IPRC0 IPRD6 IPRD4 IPRE6 IPRE4 IPRE2 IPRE0 IPRF6 IPRF4
channel
TGIA_1 TGIB_1 TCIV_1 TCIU_1
IPRF2 IPRF0
channel
TGIA_2 TGIB_2 TCIV_2 TCIU_2
IPRG6 IPRG4
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Vector Address* Interrupt Source channel Origin Interrupt Source TGIA_3 TGIB_3 TGIC_3 TGID_3 TCIV_3 channel TGIA_4 TGIB_4 TCIV_4 TCIU_4 channel TGIA_5 TGIB_5 TCIV_5 TCIU_5 channel ERI_0 RXI_0 TXI_0 TEI_0 channel ERI_1 RXI_1 TXI_1 TEI_1 channel ERI_2 RXI_2 TXI_2 TEI_2 HCAN ERS0, OVR0 SLE0 TGIMN TGINN POEIN Reserved system Vector Number Advanced Mode H'00C0 H'00C4 H'00C8 H'00CC H'00D0 H'00E0 H'00E4 H'00E8 H'00EC H'00F0 H'00F4 H'00F8 H'00FC H'0140 H'0144 H'0148 H'014C H'0150 H'0154 H'0158 H'015C H'0160 H'0164 H'0168 H'016C H'01A0 H'01A4 H'01A8 H'01AC H'01B0 H'01B4 H'01B8 H'01BC IPRM2 IPRM0 IPRM6 IPRM4 IPRK2 IPRK0 IPRK6 IPRK4 IPRJ2 IPRJ0 IPRH2 IPRH0 IPRH6 IPRH4 IPRG2 IPRG0 Priority High
Note: Lower bits start address. Rev. 2.0, 01/01, Page
Interrupt Control Modes Interrupt Operation
interrupt controller modes: interrupt control mode interrupt control mode Interrupt operations differ depending interrupt control mode. interrupt control mode selected SYSCR. Table shows differences between interrupt control mode interrupt control mode Table
Interrupt
Interrupt Control Modes
Priority Setting Interrupt Mask Bits Description priorities interrupt sources fixed default settings. Interrupt sources, except NMI, masked bit. priority levels other than with IPR. 8-level interrupt mask control performed bits
Control Mode Registers Default
5.6.1
Interrupt Control Mode
interrupt control mode interrupt requests other than masked CPU. Figure shows flowchart interrupt acceptance operation this case. interrupt source occurs when corresponding interrupt enable interrupt request sent interrupt controller. only interrupt accepted, other interrupt requests held pending. cleared, interrupt request accepted. Interrupt requests sent interrupt controller, highest-ranked interrupt according priority system accepted, other interrupt requests held pending. When accepts interrupt request, starts interrupt exception handling after execution current instruction been completed. saved stack area interrupt exception handling. saved stack shows address first instruction executed after returning from interrupt handling routine. Next, This masks interrupts except NMI. generates vector address accepted interrupt starts execution interrupt handling routine address indicated contents vector address vector table.
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Program execution status
Interrupt generated?
Hold pending
IRQ0 IRQ1
TEI_2
Save
Read vector address
Branch interrupt handling routine
Figure Flowchart Procedure Interrupt Acceptance Interrupt Control Mode
Rev. 2.0, 01/01, Page
5.6.2
Interrupt Control Mode
interrupt control mode mask control applied eight levels interrupt requests other than comparing interrupt mask level bits) setting. Figure shows flowchart interrupt acceptance operation this case. interrupt source occurs when corresponding interrupt enable interrupt request sent interrupt controller. When interrupt requests sent interrupt controller, interrupt with highest priority according interrupt priority levels selected, lower-priority interrupt requests held pending. number interrupt requests with same priority generated same time, interrupt request with highest priority according priority system shown table selected. Next, priority selected interrupt request compared with interrupt mask level EXR. interrupt request with priority higher than mask level that time held pending, only interrupt request with priority higher than interrupt mask level accepted. When accepts interrupt request, starts interrupt exception handling after execution current instruction been completed. CCR, saved stack area interrupt exception handling. saved stack shows address first instruction executed after returning from interrupt handling routine. cleared interrupt mask level rewritten with priority level accepted interrupt. accepted interrupt NMI, interrupt mask level H'7. generates vector address accepted interrupt starts execution interrupt handling routine address indicated contents vector address vector table.
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Program execution status
Interrupt generated?
Level interrupt? Mask level below?
Level interrupt?
Level interrupt? Mask level below? Mask level
Save CCR,
Hold pending
Clear
Update mask level
Read vector address
Branch interrupt handling routine
Figure Flowchart Procedure Interrupt Acceptance Control Mode 5.6.3 Interrupt Exception Handling Sequence
Figure shows interrupt exception handling sequence. example shown case where interrupt control mode advanced mode, program area stack area on-chip memory.
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Interrupt acceptance Internal operation stack Vector fetch Internal operation
Interrupt level determination Instruction Wait instruction prefetch
Interrupt service routine instruction prefetch
Interrupt request signal
Internal address
(11)
(13)
Internal read signal
Internal write signal (10) (12) (14)
Figure Interrupt Exception Handling
(11) (10) (12) (13) (14)
Internal data
Rev. 2.0, 01/01, page
Instruction prefetch address (Not executed. This contents saved return address.) Instruction code (Not executed.) Instruction prefetch address (Not executed.) SP-2 SP-4
Saved saved Vector address Interrupt handling routine start address (Vector address contents) Interrupt handling routine start address ((13) (10)(12)) First instruction interrupt handling routine
5.6.4
Interrupt Response Times
Table shows interrupt response times interval between generation interrupt request execution first instruction interrupt handling routine. execution status symbols used table explained table 5-5. This capable fast word transfer on-chip memory, program area on-chip stack area on-chip RAM, enabling high-speed processing. Table Interrupt Response Times
Normal Mode* Interrupt control mode
Advanced Mode Interrupt control mode Interrupt control mode
Execution Status Interrupt priority determination*
Interrupt control mode
Number wait states until executing instruction ends* CCR, stack save Vector fetch Instruction fetch*
Internal processing*
Total (using on-chip memory) Notes:
states case internal interrupt. Refers MULXS DIVXS instructions. Prefetch after interrupt acceptance interrupt handling routine prefetch. Internal processing after interrupt acceptance internal processing after vector fetch. available this LSI.
Rev. 2.0, 01/01, Page
Table
Number States Interrupt Handling Routine Execution Status
Object Access External Device 3-State Access 6+2m 2-State Access 3-State Access
Symbol Instruction fetch Branch address read Stack manipulation
Internal Memory
2-State Access
Legend Number wait states external device access. Note:* Cannot used this LSI.
5.6.5
Activation Interrupt
activated interrupt. details, section Data Transfer Controller.
5.7.1
Usage Notes
Contention between Interrupt Generation Disabling
When interrupt enable cleared disable interrupts, disabling becomes effective after execution instruction. When interrupt enable cleared instruction such BCLR MOV, interrupt generated during execution instruction, interrupt concerned will still enabled completion instruction, interrupt exception handling that interrupt will executed completion instruction. However, there interrupt request higher priority than that interrupt, interrupt exception handling will executed higher-priority interrupt, lower-priority interrupt will ignored. same also applies when interrupt source flag cleared Figure shows example which TGIEA TP'U's TIER_0 register cleared above contention will occur enable interrupt source flag cleared while interrupt masked.
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TIER_0 write cycle
TCIVexception handling
Internal address
TIER_0 address
Internal write signal
TCIEV
TCFV
TCIV interrupt signal
Figure Contention between Interrupt Generation Disabling 5.7.2 Instructions that Disable Interrupts
instructions that disable interrupts LDC, ANDC, ORC, XORC. After these instructions executed, interrupts including disabled next instruction always executed. When these instructions, value becomes valid states after execution instruction ends. 5.7.3 When Interrupts Disabled
There times when interrupt acceptance disabled interrupt controller. interrupt controller disables interrupt acceptance 3-state period after updated mask level with LDC, ANDC, ORC, XORC instruction.
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5.7.4
Interrupts during Execution EEPMOV Instruction
Interrupt operation differs between EEPMOV.B instruction EEPMOV.W instruction. With EEPMOV.B instruction, interrupt request (including NMI) issued during transfer accepted until move completed. With EEPMOV.W instruction, interrupt request issued during transfer, interrupt exception handling starts break transfer cycle. value saved stack this case address next instruction. Therefore, interrupt generated during execution EEPMOV.W instruction, following coding should used.
EEPMOV.W MOV.W R4,R4
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Section Break Controller (PBC)
break controller (PBC) provides functions that simplify program debugging. Using these functions, easy create self-monitoring debugger, enabling programs debugged with chip alone, without using in-circuit emulator. block diagram break controller shown figure 6-1.
Features
break channels 24-bit break address masking possible Four types break compare conditions Instruction fetch data read data write data read/write master Either CPU/DTC selected timing break exception handling after occurrence break condition follows: Immediately before execution instruction fetched address (instruction fetch) Immediately after execution instruction that accesses data address (data access) Module stop mode
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BARA
BCRA
Output control
Mask control
Comparator
Internal address
Control logic
Access status
break interrupt
Comparator
Match signal
Control logic
Output control
Mask control
BARB
BCRB
Figure Block Diagram Break Controller
Register Descriptions
break controller following registers. details register addresses register states during each process, refer appendix Internal Register. Break address register (BARA) Break address register (BARB) Break control register (BCRA) Break control register (BCRB) 6.2.1 Break Address Register (BARA)
BARA 32-bit readable/writable register that specifies channel break address.
Name Initial Value Undefined Description Reserved These bits read undefined value cannot modified. BAA23 BAA0 H'000000 These bits channel break address.
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6.2.2
Break Address Register (BARB)
BARB channel break address register. configuration same BARA. 6.2.3 Break Control Register (BCRA)
BCRA controls channel breaks. BCRA also contains condition match flag.
Name CMFA Initial Value Description Condition Match Flag [Setting condition] When condition channel satisfied [Clearing condition] When written CMFA after reading CMFA Cycle/DTC Cycle Select Selects channel break condition master. BAMRA2 BAMRA1 BAMRA0 Break Address Mask Register These bits specify which bits break address BARA masked. 000: BAA23-0 (All bits unmasked) 001: BAA23-1 (Lowest masked) 010: BAA23-2 (Lower bits masked) 011: BAA23-3 (Lower bits masked) 100: BAA23-4 (Lower bits masked) 101: BAA23-8 (Lower bits masked) 110: BAA23-12 (Lower bits masked) 111: BAA23-16 (Lower bits masked) CSELA1 CSELA0 Break Condition Select Selects break condition channel Instruction fetch used break condition Data read cycle used break condition Data write cycle used break condition Data read/write cycle used break condition BIEA Break Interrupt Enable When this break interrupt request channel enabled.
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6.2.4
Break Control Register (BCRB)
BCRB channel break control register. configuration same BCRA.
Operation
operation flow from break condition setting break interrupt exception handling shown section 6.3.1, Break Interrupt Instruction Fetch, 6.3.2, Break Interrupt Data Access, taking example channel 6.3.1 Break Interrupt Instruction Fetch
break address BARA. break caused instruction fetch, address first instruction byte break address. break conditions BCR. (CDA) select because master must break caused instruction fetch. address bits masked bits (BAMA2-0). bits (CSELA1-0) specify instruction fetch break condition. (BIEA) enable break interrupts. When instruction address fetched, break request generated immediately before execution fetched instruction, condition match flag (CMFA) set. After priority determination interrupt controller, break interrupt exception handling started. 6.3.2 Break Interrupt Data Access
break address BARA. break caused data access, target ROM, RAM, I/O, external address space address break address. Stack operations branch address reads included data accesses. break conditions BCRA. Select master with (CDA). address bits masked bits (BAMA2-0). bits (CSELA1-0) specify data access break condition. (BIEA) enable break interrupts. After execution instruction that performs data access address, break request generated condition match flag (CMFA) set. After priority determination interrupt controller, break interrupt exception handling started.
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6.3.3
Notes Break Interrupt Handling
When break interrupt generated transfer address EEPMOV.B instruction break exception handling executed after data transfers have been completed EEPMOV.B instruction ended. When break interrupt generated transfer address break exception handling executed after completed specified number data transfers, after data which DISEL been transferred. 6.3.4 Operation Transitions Power-Down Modes
operation when break interrupt instruction fetch address after SLEEP instruction shown below. When SLEEP instruction causes transition from high-speed (medium-speed) mode sleep mode: After execution SLEEP instruction, transition made sleep mode, break interrupt handling executed. After execution break interrupt handling, instruction address after SLEEP instruction executed (figure (A)). When SLEEP instruction causes transition software standby mode: After execution SLEEP instruction, transition made respective mode, break interrupt handling executed. However, CMFA CMFB flag (figure (B)).
SLEEP instruction execution SLEEP instruction execution
break exception handling
Transition respective mode
Execution instruction after sleep instruction
Figure Operation Power-Down Mode Transitions
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6.3.5
When Instruction Execution Delayed State
While break interrupt enable instruction execution state later than usual. 1-word branch instructions (Bcc d:8, BSR, JSR, JMP, TRAPA, RTE, RTS) on-chip RAM. When break interruption instruction fetch set, address indicates on-chip space, that address used data access, instruction that executes data access state later than normal operation. When break interruption instruction fetch break interrupt generated, executing instruction immediately preceding instruction addressing modes shown below, that address indicates on-chip RAM, instruction will state later than normal operation. Addressing modes: @ERn, @(d:16,ERn), @(d:32,ERn), @-ERn/ERn+, @aa:8, @aa:24, @aa:32, @(d:8,PC), @(d:16,PC), @@aa:8 When break interruption instruction fetch break interrupt generated, executing instruction immediately preceding instruction SLEEP, #xx,Rn addressing mode, that instruction located on-chip RAM, instruction will state later than normal operation.
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6.4.1
Usage Notes
Module Stop Mode Setting
operation disabled enabled using module stop control register. initial setting operation halted. Register access enabled clearing module stop mode. details, refer section Power-Down Modes. 6.4.2 Break Interrupts
break interrupt shared channels channel from which request issued must determined interrupt handler. 6.4.3 CMFA CMFB
CMFA CMFB flags automatically cleared must written CMFA CMFB after first reading flag while flag left another interrupt will requested after interrupt handling ends. 6.4.4 Break Interrupt when Master
break interrupt generated when master accepted after been transferred controller. 6.4.5 Break Instruction Fetch Address Following BSR, JSR, JMP, TRAPA, RTE, Instruction When break instruction fetch address following BSR, JSR, JMP, TRAPA, RTE, instruction: Even instruction address following BSR, JSR, JMP, TRAPA, RTE, instruction fetched, executed, break interrupt generated instruction fetch next address. 6.4.6 LDC, ANDC, ORC, XORC Instruction
When LDC, ANDC, ORC, XORC instruction, break interrupt becomes valid states after executing instruction. break interrupt instruction following these instructions, since interrupts, including NMI, disabled 3-state period case LDC, ANDC, ORC, XOR, next instruction always executed. details, section Interrupt Controller.
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6.4.7
Break Instruction Fetch Address Following Instruction
When break instruction fetch address following instruction: break interrupt generated instruction next address executed accordance with branch condition, generated instruction next address executed. 6.4.8 Break Instruction Fetch Branch Destination Address Instruction When break instruction fetch branch destination address instruction: break interrupt generated instruction branch destination executed accordance with branch condition, generated instruction branch destination executed.
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Section Controller
H8S/2600 driven system clock, denoted symbol controller controls memory cycle cycle. Different methods used access on-chip memory on-chip support modules. controller also arbitration function, controls operation internal masters: data transfer controller (DTC).
Basic Timing
period from rising edge next referred "state." memory cycle cycle consists one, two, three, four states. Different methods used access on-chip memory, on-chip support modules, external address space. 7.1.1 On-Chip Memory Access Timing (ROM, RAM)
On-chip memory accessed state. data bits wide, permitting both byte word transfer instruction. Figure shows on-chip memory access cycle.
cycle Internal address Address
Read access
Internal read signal Internal data Read data
Write access
Internal write signal Internal data Write data
Figure On-Chip Memory Access Cycle
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7.1.2
On-Chip Support Module Access Timing
on-chip support modules, except HCAN, MMT, POE, accessed states. data either bits bits wide, depending particular internal register being accessed. details, refer appendix Internal Register. Figure shows access timing on-chip supporting modules.
cycle Internal address Address
Read access
Internal read signal Internal data Read data
Write access
Internal write signal Internal data Write data
Figure On-Chip Support Module Access Cycle
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7.1.3
On-Chip HCAN Module Access Timing
On-chip HCAN module access performed four states. data width bits. Wait states inserted means wait request from HCAN. On-chip HCAN module access timing shown figures 7-3.
cycle Internal address Address
HCAN read signal Read Internal data Read data
HCAN write signal Write Internal data Write data
Figure On-Chip HCAN Module Access Cycle (Wait States Inserted) 7.1.4 On-chip Module Access Timing
On-chip module access performed three states. data width bits. On-chip module access timings shown figure 7-4.
cycle Internal address Address
read signal Read Internal data Read data
write signal Write Internal data Write data
Figure On-chip Module Access Cycle
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Arbitration
Controller arbiter that arbitrates master operations. There masters, DTC, which perform read/write operations when they control bus. 7.2.1 Order Priority Masters
Each master requests means request signal. arbiter detects masters' request signals, requested, sends request acknowledge signal master making request. there requests from more than master, request acknowledge signal sent with highest priority. When master receives request acknowledge signal, takes possession until that signal canceled. order priority masters follows: (High) 7.2.2 (Low)
Transfer Timing
Even request received from master with higher priority than that master that acquired currently operating, necessarily transferred immediately. lowest-priority master, request received from DTC, arbiter transfers master that issued request. timing transfer follows: transferred break between cycles. However, cycle executed discrete operations, case longword-size access, transferred between such operations. details, refer section 2.7, States During Instruction Execution, H8S/2600 Series, H8S/2000 Series Programming Manual. sleep mode, transfers immediately. release after vector read, register information read states), single data transfer, register information write states). does release during register information read states), single data transfer, register information write states).
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Section Data Transfer Controller (DTC)
This includes data transfer controller (DTC). activated interrupt software, transfer data. Figure shows block diagram DTC. DTC's register information stored on-chip RAM. When used, RAME SYSCR must 32-bit connects on-chip kbyte), enabling 32-bit/1-state reading writing register information.
Features
Transfer possible over number channels Three transfer modes Normal, repeat, block transfer modes available activation source trigger number data transfers (chain transfer) direct specification 16-Mbyte address space possible Activation software possible Transfer byte word units interrupt requested interrupt that activated Module stop mode
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Internal address On-chip
Interrupt controller
DTCERA DTCERG
Control logic
Interrupt request
interrupt request Legend MRA, CRA, DTCERA DTCERG DTVECR
service request
mode registers transfer count registers source address register destination address register enable registers vector register
Figure Block Diagram
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Internal data
Register information
DTVECR
Register Configuration
following registers. mode register (MRA) mode register (MRB) source address register (SAR) destination address register (DAR) transfer count register (CRA) transfer count register (CRB) These registers canno
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