DSP56F805 Chip Errata DSP56F805 16-Bit Signal Processor

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DSP56F805 Chip Errata DSP56F805 16-Bit Signal Processor

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DSP56F805E/D Rev. 2.0, 12/15/2000
DSP56F805
Chip Errata
DSP56F805 16-Bit Signal Processor
This document reports errata information chip revision second digit Errata Number identifies document revision number. This document pre-publication draft.
Chip Revision Errata Information:
following errata items apply only Revision 56F805 devices. These parts marked "Prague_B"
Errata Number Description Low-Voltage interrupt samples VDDA instead pin. Impact Work Around Impact: voltage interrupt monitors analog power supply instead digital power supplies. Work Around: Connect VDDA voltage interrupts. Quad Time, when Pulse Output Mode, clock rate yields pluses. Impact: clock rate creates extra pulse. Work Around: Program pulses only when operating Maximum clock rate. outputs disabled during DEBUG mode. Impact: Safety considerations outputs disabled prior entering DEBUG mode. Work Around: Disable outputs prior entering DEBUG mode. module will continue operate while DEBUG mode unless explicitly disabled. Program Flash Interface Unit (PFIU) address register read returns wrong value when writing out-of-row address. yields incorrect data. VDDA 3.15 volts. Impact: When verifying out-of-row write, PFIU returns address applied Flash pins, which concatenation register ADDRESS[4:0] bits. Work Around: None Impact: voltage VDDA cause inaccurate measurement. Work Around: Keep VDDA greater than 3.15 volts. Keep VREF less than VDDA.
Motorola, Inc., 2000. rights reserved.
Chip Revision Errata Information:
following errata items apply only Revision 56F805 devices. These parts marked "Prague_B"
Errata Number Description Analog input voltages measured properly. Impact Work Around Impact: Inputs yield measurements Work Around: Bias Analog inputs above Noisy measurements. Impact: Same Description Work Around: Recommended values ADCDIV Register: register available cycle immediately after value change. Impact: case index+ offset move into register, available cycle immediately following change value. Example: move (R2) Work Around: no-operation (NOP) will need inserted between statements. assembler will modified flag this problem. Timer GPIO interrupts cleared when clearing other interrupts. Impact: timer GPIO modules have several interrupts cleared writing same register. Unfortunately, clearing interrupt unintentionally result clearing interrupt that occurred between time status register read written back. This problem will show both Revision devices. Work Around: enable multiple interrupts single register. 10.2 Device meet Flash data retention specification years. Impact: Random, single data retention failures have been observed product reliability testing. This problem will corrected prior production release. Work Around: None
DSP56F805 Preliminary Technical Data
Chip Revision Errata Information:
following errata items apply only Revision 56F803 devices. These parts marked with date codes between 0012 0039 inclusive (bottom line marking).
Errata Number Description Corrupted register accesses using Core Global Data (CGDB). Impact Work Around Impact: Accessing memory-mapped register (via IPBus) result corrupted data being read. Work Around: indirect addressing when accessing registers located IPBus. Inaccurate analog-to-digital converter saturation when analog input goes range (observed VDD=3.0 Improper recovery from STOP/Wait modes. Impact: Inaccurate results will observed when inputs range. Work Around: Ensure that analog inputs remain Ground range. Impact: Device come from STOP/WAIT mode designed. Work Around: Customer should STOP WAIT instructions. These modes should disabled using SYS_CNTL register. Low-Voltage interrupt samples VDDA instead pin. 2.0, added Work Arounds. Updates Pulse Width Modulator fault inputs clocked. Impact: Fault processing work properly when clock signal interrupted. Work Around: generated clock. outputs disabled during STOP mode. Impact: Safety considerations outputs disabled prior entering STOP mode. Work Around: Customer should STOP instruction. This mode should disabled using SYS_CNTL register. outputs disabled during DEBUG mode. Impact: Safety considerations outputs disabled prior entering DEBUG mode. Work Around: Disable outputs prior entering DEBUG mode. module will continue operate while DEBUG mode unless explicitly disabled. Impact: voltage interrupt work properly separate analog digital power supplies utilized. Work Around: Connect VDDA voltage interrupts.
DSP56F805 Preliminary Technical Data
Chip Revision Errata Information:
following errata items apply only Revision 56F803 devices. These parts marked with date codes between 0012 0039 inclusive (bottom line marking).
Errata Number Description Reset status bits SYS_STS register provide accurate information. INDEX pulses increment revolution counter quadrature decoder. Impact Work Around Impact: Cause last system reset accurately determined. Work Around: None Impact: Inaccurate count revolution counter. Work Around: Divide value 32-bit position counter number "tics" revolution (assumption: position counter reset after each revolution). Impact: Same description. Work Around: read-modify-write instructions this register. Quadrature decoder bypass mode does execute designed. Glitch observed timer module's output clock pulses when using gated clock output mode. Glitches observed only high speeds. Device properly come from Power-OnReset (POR) state. Impact: Same description. Work Around: quad-timer perform this function. Impact: Minimal. Feature intended speeds only. Work Around: feature speeds. Impact: Same description. Work Around: external circuit. 12.0 Program Flash Interface Unit (PFIU) address register read returns wrong value when writing out-of-row address. Loss-of-lock interrupts occur randomly. Impact: When verifying out-of-row write, PFIU returns address applied Flash pins, which concatenation register ADDRESS[4:0] bits. Work Around: None Impact: Same description Work Around: Disable loss-of-lock interrupts.
(ENHA) Channel Control Register always reads zero.
10.0
11.0
13.0
DSP56F805 Preliminary Technical Data
Chip Revision Errata Information:
following errata items apply only Revision 56F803 devices. These parts marked with date codes between 0012 0039 inclusive (bottom line marking).
Errata Number 14.0 Description Writes internal XRAM during first cycle reset work properly. Impact: Same description. Work Around: Insert no-operation (NOP) instruction application's entry point. Place instruction that does write internal XRAM application's entry point. 15.0 Flash endurance specification 10,000 cycles revision Impact: Revision devices only meet endurance specification cycles. Work Around: None. Impact Work Around
Errata information since this document.
16.1 register available cycle immediately after value change. Impact: case index+ offset move into register, available cycle immediately following change value. Example: move (R2) Work Around: no-operation (NOP) will need inserted between statements. assembler will modified flag this problem. 17.2 Timer GPIO interrupts cleared when clearing other interrupts. 2.0, removed word "not" description. Impact: timer GPIO modules have several interrupts cleared writing same register. Unfortunately, clearing interrupt unintentionally result clearing interrupt that occurred between time status register read written back. This problem will show both Revision devices. Work Around: enable multiple interrupts single register. 18.1 Problem reading correct value registers. Impact: module VLMODE other than (bits PMCCR register), reading Value registers will give incorrect value register (PMVAL0) value 0x0000 will read out. Work Around: read correct value PMVAL0, VLMODE must switched back 0x0. value register (PMVAL0) affected wrong value muxed data read bus.
DSP56F805 Preliminary Technical Data
Chip Revision Errata Information:
following errata items apply only Revision 56F803 devices. These parts marked with date codes between 0012 0039 inclusive (bottom line marking).
Errata Number Description Impact Work Around
Errata information since this document.
19.2 Device meet Flash data retention specification years. Impact: Random, single data retention failures have been observed product reliability testing. flash reprogrammed periodically (once/week), data loss could result. Work Around: None 20.2 Noisy measurements. Impact: Same Description Work Around: Recommended values ADCDIV Register:
NOTES:
DSP56F805 Preliminary Technical Data
DSP56F805 Preliminary Technical Data
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DSP56F805E/D

DSP56F805 Chip Errata DSP56F805 16-Bit Signal Processor

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