184pin Registered SDRAM MODULE 256MB SDRAM MODULE (32Mx72 ba
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M383L3310BT1
184pin Registered SDRAM MODULE
256MB SDRAM MODULE
(32Mx72 based 32Mx4 SDRAM)
Registered 184pin DIMM 72-bit ECC/Parity
Revision Nov. 2000
Rev. Nov. 2000
M383L3310BT1
Revision History
Revision (Aug 1998)
First release internal usage
184pin Registered SDRAM MODULE
Revision (May. 1999)
Changed revision from B-die C-die Changed DC/AC characteristics item from version.
Revision (Aug. 1999)
Changed revision from C-die B-die Modified binning policy From (133Mhz) (133Mhz/266Mbps@CL=2) (125Mhz) (133Mhz/266Mbps@CL=2.5) (100Mhz) (100Mhz/200Mbps@CL=2) 3.Modified following spec values From. tDQSCK tDQSQ tDS/tDH tCDLR*1 tPRE*1 tRPST*1 tHZQ*1
0.75ns 0.75 0.75ns 0.75ns 0.5ns 1tCK 0.9/1.1 0.4/0.6 0.75ns 0.75ns 0.75ns 0.5ns 1tCK 0.9/1.1 0.4/0.6 0.75ns 0.8ns 0.8ns 0.6ns 1tCK 0.9/1.1 0.4/0.6 +/-0.8ns
0.75ns 0.75ns 0.5ns 2.5tCK-tDQSS 1tCK 0.75ns tCK/2 0.75ns tCK/2 0.75ns
2.5tCK-tDQSS 1tCK tCK/2 tCK/2
Changed description method same functionality. This means difference from previous version. 4.Changed following parameter symbol From tDQCK Output data access time from CK/CK
Revision (Sept. 1999)
Changed odering information. 1-1. Exclude mark. From KMM383. 1-2. Revison From Blank: generation generation generation Example:KMM383L3310BT 1-3. Modified binning policy From (100Mhz/200Mbps@CL=2) (133Mhz/266Mbps@CL=2) (133Mhz/266Mbps@CL=2.5)
M383. gernation generation generation M383L3310BT0 (100Mhz/200Mbps@CL=2) (133Mhz/266Mbps@CL=2) (133Mhz/266Mbps@CL=2.5)
Rev. Nov. 2000
M383L3310BT1
Revision (December. 1999)
184pin Registered SDRAM MODULE
Changed from 3.3V 2.5V VDDSPD power.
Revision (April. 2000)
Page Changed from configuration table. Removed description. Page Changed bypassing reflect common Vdd/Vddq plane. Added A12, BA1. Removed from serial
Page
Changed Power operating condition. From
Reference voltage Input logic high voltage Input logic voltage Input leakage current Output High Current 1.95V) Output Current (VOUT 0.35V) VREF VIH(DC) VIL(DC) 1.15 VREF+0.18 -0.3 -15.2 15.2
Parameter
Symbol
1.35 VDDQ+0.3
0.49*VDDQ VREF +0.15 -0.3 -16.8 16.8
0.51*VDDQ VDDQ +0.3 VREF-0.15
VREF-0.18
Page Added Overshoot/Undershoot spec Vih(max) 4.2V, overshoot voltage duration VDD. Vil(min) 1.5V, overshoot voltage duration VSS. Page Changed operating conditions follows. Parameter/Condition Symbol Input High (Logic Voltage, signals VIH(AC) Input (Logic Voltage, signals. VIL(AC) Input Differential Voltage, inputs VID(AC) VREF 0.35 VREF 0.35 VDDQ+0.6 0.62 From VREF 0.31 VREF 0.31 VDDQ+0.6
page
Changed parameters follows. Parameter tDQSQ from 0.5(PC266), 0.6(PC200) 0.35tCK +0.5(PC266), +0.6(PC200) Removed Comments
Rev. Nov. 2000
M383L3310BT1
Added parameters follows
184pin Registered SDRAM MODULE
-A2(PC266@CL=2) Parameter Symbol Output valid window tHPmin -0.75ns tCLmin tCHmin
-B0(PC266@CL=2.5) tHPmin -0.75ns tCLmin tCHmin
-A0(PC200@CL=2) tHPmin -1.0ns tCLmin tCHmin
Clock half period setup first edge reads hold after last edge reads Write command delay write Write burst delay write Write burst delay write interrupted Precharge
tQCS tDQCH tQCSW tQCHW tQCHWI
1.25ns 1.25ns
0.5tCK 1.5tCK
1.25ns 1.25ns
0.5tCK 1.5tCK
1.25ns 1.25ns
0.5tCK 1.5tCK
Revision (June. 2000)
Changed version from
Revision (October. 2000)
1.Added target spec values. 2.Deleted tDAL parameter
Revision (November. 2000)
1.Changed component placement module package dimesions.
Rev. Nov. 2000
M383L3310BT1
184pin Registered SDRAM MODULE
M383L3310BT1 SDRAM 184pin DIMM
32Mx72 SDRAM 184pin DIMM based 32Mx4 GENERAL DESCRIPTION
Samsung M383L3310BT1 Double Data Rate SDRAM high density memory modules based first generation 128Mb SDRAM respectively. Samsung M383L3310BT1 consists eighteen CMOS with 4banks Double Data Rate SDRAMs 66pin TSOP-II(400mil) packages, mounted 184pin glass-epoxy substrate. Four 0.1uF decoupling capacitors mounted printed circuit board parallel each SDRAM. M383L3310BT1 Dual In-line Memory Modules intended mounting into 184pin edge connector sockets. Synchronous design allows precise cycle control with system clock. Data transactions possible both edges DQS. Range operating frequencies, programmable latencies burst lengths allow same device useful variety high bandwidth, high performance memory system applications.
FEATURE
Performance range Part Freq. Interface SSTL_2 M383L3310BT1-C(L)A2 133MHz(7.5ns@CL=2) M383L3310BT1-C(L)B0 133MHz(7.5ns@CL=2.5) M383L3310BT1-C(L)A0 100MHz(10ns@CL=2) Power supply Vdd: 2.5V 0.2V Power: normal, power cycle with address programs Latency (Access from column address):2,2.5 Burst length Data scramble :Sequential Interleave Serial presence detect with EEPROM Height 1700 (mil), double sided component
CONFIGURATIONS (Front side/back side)
Front Front DQ24 DQ25 DQS3 DQ26 DQ27 DQS8 Front VDDQ DQ41 /CAS DQS5 DQ42 DQ43 DQ48 DQ49 VDDQ DQS6 DQ50 DQ51 VDDID DQ56 DQ57 DQS7 DQ58 DQ59 Back VDDQ DQS9 *A13 VDDQ DQ12 DQ13 DQS10 DQ14 DQ15 *CKE1 VDDQ *BA2 DQ20 *A12 DQ21 DQS11 DQ22 DQ23 Back DQ28 DQ29 VDDQ DQS12 DQ30 DQ31 VDDQ /CK0 DQS17 VDDQ Back VREF DQS0 /RESET DQS1 VDDQ DQ10 DQ11 CKE0 VDDQ DQ16 DQ17 DQS2 DQ18 VDDQ DQ19 /RAS DQ45 VDDQ /CS0 */CS1 DQS14 DQ46 DQ47 VDDQ DQ52 DQ53 NC,FETEN DQS15 DQ54 DQ55 VDDQ DQ60 DQ61 DQS16 DQ62 DQ63 VDDQ VDDSPD
DESCRIPTION
Name DQ63 DQS0 DQS17 CK0,CK0 CKE0 VDDQ VREF VDDSPD VDDID RESET FETEN Function Address input (Multiplexed) Bank Select Address Data input/output Check bit(Data-in/data-out) Data Strobe input/output Clock input Clock enable input Chip select input address strobe Column address strobe Write enable Power supply (2.5V) Power Supply DQs(2.5V) Ground Power supply reference Serial EEPROM Power Supply (2.5V) Serial data Serial clock Address EEPROM identification flag Reset enable Enable connection
DQ32 VDDQ DQ33 DQS4 DQ34 DQ35 DQ40
DQ36 DQ37 DQS13 DQ38 DQ39 DQ44
These pins used this module.
SAMSUNG ELECTRONICS CO., Ltd. reserves right change products specifications without notice.
Rev. Nov. 2000
M383L3310BT1
Functional Block Diagram
184pin Registered SDRAM MODULE
RS0B RS0A DQS0
DQS9
DQS1
DQ10 DQ11
DQS10
DQ12 DQ13 DQ14 DQ15
DQS2
DQ16 DQ17 DQ18 DQ19
DQS11
DQ20 DQ21 DQ22 DQ23
DQS3
DQ24 DQ25 DQ26 DQ27
DQS12
DQ28 DQ29 DQ30 DQ31
DQS4
DQ32 DQ33 DQ34 DQ35
DQS13
DQ36 DQ37 DQ38 DQ39
DQS5
DQ40 DQ41 DQ42 DQ43
DQS14
DQ44 DQ45 DQ46 DQ47
DQS6
DQ48 DQ49 DQ50 DQ51
DQS15
DQ52 DQ53 DQ54 DQ55
Serial /VDDQ
DQS7
DQ56 DQ57 DQ58 DQ59
DQS16
DQ60 DQ61 DQ62 DQ63
DQS8
DQS17
0.1uF 0.1uF 0.1uF
VREF VDDID
Strap: Note
BA0-BAN A0-A12 CKE0
RS0A RS0B RBA0 RBAn RA12 RRAS RCAS RCKE0A RCKE0B RESET -BAn SDRAMs SDRAMs SDRAMs SDRAMs SDRAMs SDRAMs SDRAMs
PLL* CK0,CK0 Wire Clock Loading table/wiring Diagrams
Notes: DQ-to-I/O wiring shown recommended changed. DQ/DQS/DM/CKE/S relationships must maintained shown. DQS, resistors: Ohms. VDDID strap connections (for memory device VDD, VDDQ): STRAP (OPEN): VDDQ STRAP (VSS): VDDQ.
Rev. Nov. 2000
M383L3310BT1
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage relative Voltage supply relative Voltage VDDQ supply relative Storage temperature Power dissipation Short circuit current
184pin Registered SDRAM MODULE
Symbol VIN, VDDQ TSTG
Value -0.5 -1.0 -0.5 +150
Unit
Note Permanent device damage occur ABSOLUTE MAXIMUM RATINGS exceeded. Functional operation should restricted recommended operating condition. Exposure higher than recommended voltage extended periods time could affect device reliability.
POWER OPERATING CONDITIONS (SSTL_2 In/Out)
Recommended operating conditions(Voltage referenced VSS=0V, TA=0 70°C)
Parameter
Supply voltage(for device with nominal 2.5V) Supply voltage Reference voltage Termination voltage(system) Input logic high voltage Input logic voltage Input Voltage Level, inputs Input Differential Voltage, inputs Input leakage current Output leakage current Output High Current (VOUT 1.95V) Output Current (VOUT 0.35V)
Symbol
VDDQ VREF (DC) VIL(DC) (DC) (DC)
0.49*VDDQ VREF-0.04 VREF+0.15 -0.3 -0.3 -16.8 16.8
0.51*VDDQ VREF +0.04 VDDQ+0.3 VREF-0.15 VDDQ+0.3 VDDQ+0.6
Unit
Note
Notes VREF expected equal 0.5*V transmitting device, track variations level same. Peakto-peak noise VREF exceed value applied directly device. system supply signal termination resistors, expected equal VREF, must track variations level magnitude difference between input level input level
Rev. Nov. 2000
M383L3310BT1
184pin Registered SDRAM MODULE
SDRAM SPEC Items Test Conditions
Recommended operating conditions Unless Otherwise Noted, TA=0
Conditions Operating current bank Active-Precharge; tRC=tRCmin;tCK=100Mhz DDR200, 133Mhz DDR266A DDR266B; DQ,DM inputs changing twice clock cycle; address control inputs changing once clock cycle Operating current bank operation bank open, BL=4, Reads Refer following page detailed test condition Percharge power-down standby current; banks idle; power down mode; <VIL(max); tCK=100Mhz DDR200, 133Mhz DDR266A DDR266B; Vref DQ,DQS Precharge Floating standby current; =VIH(min);All banks idle; VIH(min); tCK=100Mhz DDR200, 133Mhz DDR266A DDR266B; Address other control inputs changing once clock cycle; Vref DQ,DQS Precharge Quiet standby current; VIH(min); banks idle; VIH(min); 100Mhz DDR200, 133Mhz DDR266A DDR266B; Address other control inputs stable with keeping VIH(min) =<VIL(max); Vref ,DQS Active power down standby current bank active; power-down mode; CKE=< (max); 100Mhz DDR200, 133Mhz DDR266A DDR266B; Vref DQ,DQS Active standby current; VIH(min); CKE>=VIH(min); bank active; active precharge; tRC=tRASmax; 100Mhz DDR200, 133Mhz DDR266A DDR266B; inputs changing twice clock cycle; address other control inputs changing once clock cycle Operating current burst read; Burst length reads; continguous burst; bank active; address control inputs changing once clock cycle; CL=2 100Mhz DDR200, CL=2 133Mhz DDR266A, CL=2.5 133Mhz DDR266B data changing every burst; lout Operating current burst write; Burst length writes; continuous burst; bank active address control inputs changing once clock cycle; CL=2 100Mhz DDR200, CL=2 133Mhz DDR266A, CL=2.5 133Mhz DDR266B inputs changing twice clock cycle, input data changing every burst Auto refresh current; tRFC(min) 8*tCK DDR200 100Mhz, 10*tCK DDR266A DDR266B 133Mhz; distributed refresh Self refresh current; 0.2V; External clock should 100Mhz DDR200, 133Mhz DDR266A DDR266B Orerating current Four bank operation Four bank interleaving with BL=4 -Refer following page detailed test condition Typical case: 2.5V, Worst case 2.7V, Symbol IDD0 Typical Worst
IDD1 IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5 IDD6 IDD7
Rev. Nov. 2000
M383L3310BT1
SDRAM spec table
Symbol IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 Normal power IDD7 Module A2(DDR266@CL=2) typical 2030 2750 1220 1040 1130 3020 2750 3830 5000 worst 2210 3020 1310 1130 1040 1220 3290 3020 4100 5270
184pin Registered SDRAM MODULE
B0(DDR266@CL=2.5) typical 2030 2750 1220 1040 1130 3020 2750 3830 5000 worst 2210 3020 1310 1130 1040 1220 3290 3020 4100 5270 A0(DDR200@CL=2) typical 1850 2660 1130 1040 2570 2300 3650 4820 worst 2030 2840 1220 1040 1130 2840 2570 3920 5090
Unit
Notes
Optional
calculated basis component
differently measured according loading cap.
Detailed test conditions SDRAM IDD1 IDD7
IDD1 Operating current: bank operation Typical Case 2.5V, T=25'C Worst Case 2.7V, 10'C Only bank accessed with tRC(min), Burst Mode, Address Control inputs edge changing once clock cycle. lout Timing patterns DDR200(100Mhz, CL=2) 10ns, CL2, BL=4, tRCD 2*tCK, tRAS 5*tCK Read repeat same timing with random address changing *50% data changing every burst DDR266B(133Mhz, CL=2.5) 7.5ns, CL=2.5, BL=4, tRCD 3*tCK, 9*tCK, tRAS 5*tCK Read repeat same timing with random address changing *50% data changing every burst DDR266A (133Mhz, CL=2) 7.5ns, CL=2, BL=4, tRCD 3*tCK, 9*tCK, tRAS 5*tCK Read repeat same timing with random address changing *50% data changing every burst Legend A=Activate, R=Read, W=Write, P=Precharge, N=NOP
Rev. Nov. 2000
M383L3310BT1
IDD7 Operating current: Four bank operation
184pin Registered SDRAM MODULE
Typical Case 2.5V, T=25'C Worst Case 2.7V, 10'C Four banks being interleaved with tRC(min), Burst Mode, Address Control inputs edge changing. lout Timing patterns DDR200(100Mhz, CL=2) 10ns, CL2, BL=4, tRRD 2*tCK, tRCD= 3*tCK, Read with autoprecharge Read repeat same timing with random address changing *50% data changing every burst DDR266B(133Mhz, CL=2.5) 7.5ns, CL=2.5, BL=4, tRRD 2*tCK, tRCD 3*tCK Read with autoprecharge Read repeat same timing with random address changing *50% data changing every burst DDR266A (133Mhz, CL=2) 7.5ns, CL2=2, BL=4, tRRD 2*tCK, tRCD 3*tCK Read repeat same timing with random address changing *50% data changing every burst Legend A=Activate, R=Read, W=Write, P=Precharge, N=NOP
Operating Conditions
Parameter/Condition Input High (Logic Voltage, signals Input (Logic Voltage, signals. Input Differential Voltage, inputs Input Crossing Point Voltage, inputs Symbol VIH(AC) VIL(AC) VID(AC) VIX(AC) 0.62 0.5*VDDQ-0.2 VREF 0.31 VREF 0.31 VDDQ+0.6 0.5*VDDQ+0.2 Unit Note
Note Vih(max) 4.2V. overshoot voltage duration VDD. Vil(min) -1.5V. undershoot voltage duration VSS. magnitude difference between input level input value expected equal 0.5*VDDQ transmitting device must track variations level same.
Rev. Nov. 2000
M383L3310BT1
184pin Registered SDRAM MODULE
OPERATING TEST CONDITIONS (VDD=2.5V, VDDQ=2.5V, 70°C)
Parameter Input reference voltage Clock Input signal maximum peak swing Input signal minimum slew rate Input Levels(VIH/VIL) Input timing measurement reference level Output timing measurement reference level Output load condition Value VREF+0.31/VREF-0.31 VREF Load Circuit Unit V/ns Note
Vtt=0.5*VDDQ
T=50 Output Z0=50 CLOAD=30pF VREF =0.5*V
Output Load Circuit (SSTL_2)
Input/Output CAPACITANCE (VDD=2.5, VDDQ=2.5V, 25°C, f=1MHz)
Parameter Input capacitance(A0 A11, 1,RAS,CAS, Input capacitance(CKE0) Input capacitance( CS0) Input capacitance( CLK0, CLK0) Input capacitance(DM0~DM8) Data input/output capacitance(DQ0~DQ63) Data input/output capacitance(CB0~CB7) Symbol CIN1 CIN2 CIN3 CIN4 CIN5 COUT1 COUT2 Unit
Rev. Nov. 2000
M383L3310BT1
184pin Registered SDRAM MODULE
Timming Parameters Specifications (These charicteristics were tested Component)
Parameter cycle time Refresh cycle time active time delay precharge time active active delay Write recovery time Last data Read command Col. address Col. address delay Clock cycle time CL=2.0 CL=2.5 Clock high level width Clock level width DQS-out access time from CK/CK Output data access time from CK/CK Data strobe edge ouput data edge Read Preamble Read Postamble Data high impedence time from CK/CK valid DQS-in DQS-in setup time DQS-in hold time DQS-in high level width DQS-in level width DQS-in cycle time Address Control Input setup time Address Control Input hold time Mode register cycle time setup time hold time input pulse width Power down exit time Exit self refresh write command tDQSCK tDQSQ tRPRE tRPST tHZQ tDQSS tWPRES tWPREH tDQSH tDQSL tDSC tMRD tDIPW tPDEX tXSW 0.45 0.45 -0.75 -0.75 -0.75 0.75 0.25 1.75 Symbol tRFC tRAS tRCD tRRD tCDLR tCCD K4H281638B -TCA2 (DDR266A) 0.55 0.55 +0.75 +0.75 +0.5 +0.75 1.25 120K K4H281638B -TCB0 (DDR266B) 0.45 0.45 -0.75 -0.75 -0.75 0.75 0.25 1.75 0.55 0.55 +0.75 +0.75 +0.5 +0.75 1.25 0.45 0.45 -0.8 -0.8 -0.8 0.75 0.25 120K K4H281638B -TCA0 (DDR200) 0.55 0.55 +0.8 +0.8 +0.6 +0.8 1.25 120K Unit Note
Rev. Nov. 2000
M383L3310BT1
184pin Registered SDRAM MODULE
-A2(PC266@CL=2) -B0(PC266@CL=2.5) -A0(PC200@CL=2) 15.6 tHPmin -0.75ns tCLmin tCHmin 0.25 15.6 tHPmin -0.75ns tCLmin tCHmin 0.25 15.6 tHPmin -1.0ns tCLmin tCHmin 0.25
Parameter Exit self refresh bank active command Exit self refresh read command Refresh interval time 128Mb
Symbol tXSA tXSR tREF
Unit Cycle
Note
Output valid window
Clock half period write postamble time setup first edge reads hold after last edge reads Write command delay write Write burst delay write Write burst delay write interrupted Precharge
tWPST tQCS tQCH tQCSW tQCHW tQCHWI
1.25ns
0.5tCK 1.5tCK
1.25ns
0.5tCK 1.5tCK
1.25ns
0.5tCK 1.5tCK
Note Maximum burst refresh tHZQ transitions occurs same access time windows valid data transitions. These parameters referenced specific voltage level, specify when device output longer driving. specific requirement that valid(High Low) before this edge. case shown(DQS going from High_Z logic Low) applies when writes were previously progress bus. previous write progress, could High this time, depending tDQSS. maximum limit this parameter device limit. device will operate with great value this parameter, system performance (bus turnaround) will degrade accordingly. value tQCSW min. 1.25ns from last going data strobe edge high. value tQCSW max. 0.5tcK from first high going clock edge after last going data strobe edge high. value tQCSWI max. 1.5tcK from first high going clock edge after last going data strobe edge high. write command applied with tRCD satisfied after this command.
Rev. Nov. 2000
M383L3310BT1
Command Truth Table
COMMAND Register Register Extended Mode Register Auto Refresh Refresh Entry Self Refresh Exit
184pin Registered SDRAM MODULE
(V=Valid, X=Dont Care, H=Logic High, L=Logic Low)
CKEn-1 CKEn BA0,1 A10/AP Note
CODE CODE
Address
Column Address (A0~A9, A11) Column Address (A0~A9, A11)
Bank Active Addr. Read Column Address Write Column Address Burst Stop Precharge Bank Selection Banks Entry Exit Entry Precharge Power Down Mode Exit operation (NOP) defined Auto Precharge Disable Auto Precharge Enable Auto Precharge Disable Auto Precharge Enable
Active Power Down
Note Code Operand Code. Program keys. (@EMRS/MRS) 2.EMRS/ issued only banks precharge state. command issued clock cycles after EMRS MRS. Auto refresh functions same refresh DRAM. automatical precharge without precharge command meant "Auto". Auto/self refresh issued only banks precharge state. Bank select addresses. both "Low" read, write, active precharge, bank selected. both "High" "Low" read, write, active precharge, bank selected. both "Low" "High" read, write, active precharge, bank selected. both "High" read, write, active precharge, bank selected. A10/AP "High" precharge, ignored banks selected. During burst write with auto precharge, read/write command issued. Another bank read/write command issued after burst. active associated bank issued after burst. Burst stop command valid every burst length. sampled rising falling edges Data-in masked both edges (Write latency This combination defined function, which means Operation(NOP)" SDRAM.
Rev. Nov. 2000
M383L3310BT1
PACKAGE DIMENSIONS
184pin Registered SDRAM MODULE
Units Inches (Millimeters)
5.25 0.006 (133.350 0.15) 5.171 (131.350) 5.077 (128.950)
0.089 (2.26)
0.100 (2.30 Min)
0.393 (10.00)
0.78 (19.80)
2.500
0.10
(17.80)
(0.167) (4.24)
(2.50
0.26 (6.62)
0.100
0.250 (6.350)
0.157 (4.00) 0.1496 (3.80)
0.039 0.002 (1.000 0.050) 0.0787 (2.00) 0.0078 ±0.006 (0.20 ±0.15) 0.050 (1.270) 0.1575 (4.00)
0.118 (3.00)
2.175 Detail
0.071 (1.80)
Detail
0.10
Tolerances 0.005(.13) unless otherwise specified used device 32Mx4 SDRAM, TSOP SDRAM Part K4H280438B-TC
Rev. Nov. 2000
(43.33) 0.150 (3.81 Max) 0.050 0.0039 (1.270 0.10)
M383L3310BT1
184pin Registered SDRAM MODULE
(nominal)
Registered DIMM Clock Topolgy
SDRAM stack OUT1 R=120
feedback R=240 Reg1 SDRAM stack Reg2 R=240 Note Lenghts inches Note Z0=60 tD=2.2ns/ft Probe point
Clock Reference
1.5pF 0.266
Notes* Clock delay from input clock input SDRAM register will 0ns(nominal). Input,output, feedback clock lines terminated from line leine shown, from line ground. Only output shown output type. addtional outputs will wired similar maner. termination resistors feedback path clocks loacted after pins PLL.
Rev. Nov. 2000
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