T-0911/0912 V0.4 Zoom Engine TFT-LCD Monitor AUTO inOSD

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T-0911/0912 V0.4 Zoom Engine TFT-LCD Monitor AUTO inOSD

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T-0911/0912 V0.4
Zoom Engine TFT-LCD Monitor
AUTO
inOSD exOSD
Preliminary specification
Mar. 2000
T-0911/T-0912
trumpion
microelectronics, Inc.
Preliminary Spec.
trumpion
T-0911/0912 V0.4
TABLE Version
Date
Oct. 1999 Dec. 1999 Jan. 2000 Mar. 2000
Author
Gene Chuang Gene Chuang Gene Chuang Gene Chuang
Description
preliminary release preliminary release selected customers with only preliminary release zuracII selected customers with only preliminary release zuracII first-silicon promotion (selected customers with only.)
trumpion microelectronics, inc. believes information contained this document accurate. However, this information subject change without notice. trumpion microelectronics does assume responsibility use, infringement patents other rights third parties. This document implies license under patents copyrights. Trademarks this document belong their respective companies.
Copyright Notice
This manual copyright protected. rights reserved. This document not, whole part, copied, photocopied, reproduced, translated, reduced electronic medium machine-readable form without prior written consent from trumpion microelectronics, Inc. Copyright1999-trumpion microelectronics, Inc.All rights reserved.
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Introduction
T-0911/0912 V0.4
ZURACII/III (Zoom Up/down RAte Converter III) chip converts PC/Mac video signals TFT-LCD monitor display. performs image scaling 24-bit data stream feeds scaled pixels panel. chip embeds line buffers that scaling needs external memory ICs. Screen Display) logic embedded supporting user interface, besides, there overlay port external signals interface. auto adjustment function provides automatic frequency, phase, position, white balance tuning. chip includes also contrast/brightness circuit gamma tables color correction. ZURACII chips drop-in replacements trumpion Zurac scaler. ZURACII targeted XGA/SVGA TFT-LCD panel, while ZURACIII intended primarily SXGA applications. registers Zurac ZURACII/III compatible unless high-lighted.
Additional ZURACII/III Features beyond ZURAC
Scale (same Zurac) down. Besides Bresenham Linear Zurac, B-cubic Bresenham Sinc scaling algorithms also available. Improved auto function, full screen input format detection best phase searching. input digital (e.g. DDWG OpenLDI) interface. Hardware mode detection both sync only mode. Composite sync (H+V) input coast signal output ADC. Programming viewing window PC/TV, programmable Href/Vref delays video overscan. Sync processing wrap effect. Improved resolution scaling factor). Improved resolution contrast adjusting each R/G/B. Color (alpha) blending video. Interlaced field detection programmable display area. default state (immediately after system reset) free-run mode. 10-bit Gamma table. panel support SXGA@75Hz.
scaler
Scale down available ZuracII/ZuracIII. Besides Bresenham Linear Zurac, B-cubic Bresenham Sinc (sin scaling algorithms also available. Scale algo programmed sharpness/smoothness text graphics display.
TABLE scaling factor each display mode Zoom 800*600 SXGA 1280*1024
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Input mode
Zoom 1024*768 0.75
Zoom 1280*1024
Resolution
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Input mode Resolution 1152*864 1024*768 25/36 25/32
T-0911/0912 V0.4
Zoom 800*600 (576) (576)
Zoom 1024*768 =0.8888
Zoom 1280*1024 11/10 (1267) 32/27
other display modes same Zurac
.General Features
Single-chip video scaling solution. external memory required. Programmable independent horizontal vertical zoom down. input digital (e.g. OpenLDI) interface. Hardware display mode detection both sync only mode. Composite sync (H+V) input coast signal (synchronized with rising falling Hsync, programmable delay) output ADC. chip programmable monitor user interface. Enhanced auto adjustment frequency, phase, position, white balance. chip brightness, contrast gamma correction. Enhanced dithering with feedback error diffusion 0.25 CMOS technology with tolerance input pads. 160-pin PQFP package.
Input
Single port mode: 24-bit 1-pixel/transfer (max.) Single-port input from either input port. Dual port mode: 48-bit 2-pixel/transfer pixel rate 135MHz) 8-bit 4:2:2 (CCIR 656), 16-bit 4:2:2 video input. Glue-less connection video sources from MPEGII decoder video decoder, e.g. SAA7113. Build-in color space converter. tolerant input pads support 5V/3.3V interface.
Gamma correction
10-bit Gamma table. Downloadable true-color gamma correction table. Downloadable font fonts with 20x12 font size internal OSD. Overlay port interface color look-up table with color indices from external OSD. Color blending video. Improved range location.
Output
Single pixel/clock bit) double pixel/clock bit) digital output.
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Maximum resolution 1280x1024x75Hz. Output size: 800*600, 1024*768, 1280*1024, 1400x1050 scale up). Compliant with proposed VESA FPDI-2 standard direct connect LVDS transceivers.
Display Synchronization Modes
Input output frames have equal frame rate vertical active periods synchronized.
Applications
TFT-LCD monitors. NTSC/PAL projection systems office presentation home theater. Image scaling video format conversions.
FIGURE Typical application monitor NTSC
Video decoder
Additional VGAHS ICLK RGHS HS/VS ICLK
TDA8752 THS8083 AD9884
TFT-LCD Display Panel
TMDS
ZuracII/III
CSYNC SYNC Slicer Legend: optional block
Block Diagram
hardware block diagram chip following:
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FIGURE Block Diagram ZURAC chip
T-0911/0912 V0.4
PC(RGB) Input Horizontal scaling Scale down
Video(YUV) Input
Line buffers control
Horizontal scaling scale
Vertical scaling
Brightness &contrast control
Gamma correct
Source Mixer
Output format
Auto function mode detection
sync, Generator
Internal Downloadable Font panel
Host Interface
External (option) Micro controller
Supported Display Modes
TABLE supported scaling each display mode Zoom 800*600 HQscaledown HQscaledown HQscaledown HQscaleup scaleup scaleup scaleup
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Input mode SXGA SVGA DOS(TEXT) DOS(EGA) TEXT
Resolution 1280*1024 1152*864 1024*768 800*600 640*480 640*400 640*350 720*400
Zoom 1024*768 HQscaledown HQscaledown HQscaleup HQscaleup scaleup scaleup scaleup
Zoom 1280*1024
HQscaleup HQscaleup HQscaleup HQscaleup scaleup scaleup scaleup
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Input mode NTSC Resolution 832*624 720*(240*2) 720*(288*2)
T-0911/0912 V0.4
Zoom 800*600 scaledown De-interlaced De-interlaced Zoom 1024*768 HQscaleup De-interlaced De-interlaced
Zoom 1280*1024 HQscaleup De-interlaced De-interlaced
Without external frame buffers, scaling performed under condition that output frame-rate same input frame-rate. example, with frame-rate 60Hz (640*480*60Hz) scaled 800*600*60Hz 1024*768*60Hz. Legend: HQscaleup means High Quality scale supported, De-interlaced means interlaced video signal scaled panel resolution starting lines panel different compensate offset even fields. means available.
Chip Characteristics
Recommended Operating Conditions
ABSOLUTE MAXIMUM RATINGS Item
Operating voltage Operating chassis temperature Total power dissipation
Value
2.5V 3.3V plus/minus 80oC 0.5W (estimated panel)
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Pinning
T-0911/0912 V0.4
ADCCLKP (out) COAST (out), ADCCLKN (out) RGHS (out) VGAHS (in) SCSN (in) (in), SDAI (in) CSYNC (in), SDAO renamed PCLK PACLK PBCLK VDDPP which internally tied together with VDDAP) VDD3 (out), PCLKIN (in) VERSION ONLY) FIGURE assignment ZuracII/ZuracIII
IABLU1 IABLU0 IACLK IBCLK (YUVLLC) COAST VDD2 RGHS PCLKIN IAVSYNC IAHSYNC IBRED7 (YIN7/YUV7) IBRED6 (YIN6/YUV6) IBRED5 (YIN5/YUV5) IBRED4 (YIN4/YUV4) IBRED3 (YIN3/YUV3) IBRED2 (YIN2/YUV2) IBRED1 (YIN1/YUV1) IBRED0 (YIN0/YUV0) VDD2 IBGRN7 (YUVLLC2) IBGRN6 (YUVVS) IBGRN5 (YUVHS) IBGRN4 IBGRN3 IBGRN2 (YUVVREF) IBGRN1 (YUVHREF) IBGRN0 (YUVCREF) CLAMP IBBLU7 (UVIN7) IBBLU6 (UVIN6) IBBLU5 (UVIN5) IBBLU4 (UVIN4) VDD3 IBBLU3 (UVIN3) IBBLU2 (UVIN2) IBBLU1 (UVIN1) IBBLU0 (UVIN0)
IABLU2 IABLU3 IABLU4 IABLU5 IABLU6 IABLU7 VDD3 IAGRN0 IAGRN1 IAGRN2 IAGRN3 IAGRN4 IAGRN5 IAGRN6 IAGRN7 IARED0 IARED1 IARED2 VDD2 IARED3 IARED4 IARED5 IARED6 IARED7 PARED7 PARED6 PARED5 PARED4 PARED3 PARED2 VDD3 PARED1 PARED0 PAGRN7 PAGRN6 PAGRN5
Graphics Input Port
Panel Interface Port
Graphics Video Input Port
Host Overlay Port Panel Interface Port
PAGRN4 PAGRN3 PAGRN2 PAGRN1 PAGRN0 VDD2 PABLU7 PABLU6 PABLU5 PABLU4 PABLU3 PABLU2 PABLU1 PABLU0 PHSYNC VDD3 PVSYNC VDD2 PBRED7 PBRED6 PBRED5 PBRED4 PACLK PBCLK VDDAP VSSAP VSSPP VDD3 PBRED3 PBRED2 PBRED1 PBRED0 PBGRN7
VGAHS INTN RSTN VDD3 CSYNC POWERDN OVCLK OVFB VDD2 PBBLU0 PBBLU1 PBBLU2 PBBLU3 PBBLU4 PBBLU5 PBBLU6 PBBLU7 VDD3 PBGRN0 PBGRN1 PBGRN2 PBGRN3 PBGRN4 PBGRN5 PBGRN6
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95-99, 101-103 104-107, 109-112 114-119, 122-123 (drive) Name
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TABLE Input Ports (RGB Data, pins)
Description IACLK IAVSYNC IAHSYNC IARED[7:0] IAGRN[7:0] IABLU[7:0] IBRED[7:0] YIN[7:0]/ YUV[7:0] IBCLK/YUVLLC COAST RGHS VGAHS Clock port input (single/double pixel clock). Vertical Sync video port. Horizontal Sync video port input data video port. numbers listed from LSB. Green input data video port. Blue input data video port video port input data 16-bit YUV422 8-bit YUV422 Clock port input. Also used signal when mode selected. COAST signal (regenerated VS). Regenerated input Display enable signal from digital flat panel interface This signal should tied high function used CSYNC IBGRN[7:0] Composite sync signal that includes Green input data video port YUVLLC2 YUVVS YUVHS YUVVREF YUVHREF YUVCREF 151-154, IBBLU[7:0] UVIN[7:0] CLAMP Blue video port input data 16-bit YUV422 Clamp pulse Pulse width modulation output (NOTE: VDD3 Zurac)
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Name PACLK
T-0911/0912 V0.4
TABLE Panel interface Display Port) (RGB Data, pins)
Description Display port clock panel (capability (This clock generated from internal PLL) Display port clock panel (capability 16mA) This clock generated from internal PLL) Display data control signals will synchronized this external clock source. Display enable (active area display) Display Vertical Sync Display Horizontal Sync Display port data. Display port green data. numbers listed from Display port blue data Display port data. Display port green data Display port blue data Reference frequency output internal oscillator Reference frequency input internal oscillator (should connected 14.31818MHz crystal)
PBCLK
93-88, 86-85 84-82, 79-75 73-66 59-56, 46-43, 39-33 31-24
PCLKIN PVSYNC PHSYNC PARED[7:0] PAGRN[7:0] PABLU[7:0] PBRED[7:0] PBGRN[7:0] PBBLU[7:0]
TABLE Host Interface Signals pins)
Name INTN RSTN POWERDN Description Interrupt host (active low) Device reset (active low) Serial data in/out Serial clock Power Down, normal, 1:Powerdown
TABLE Overlay Port (External OSD) pins)
Name OVCLK OVFB Description Clock external overlay circuit Overlay color select Overlay color select Overlay color select Overlay intensity select Overlay color enable
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Name
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Description Overlay sync signal Overlay sync signal
TABLE Testing pins)
Name Description Action testing (should grounded) Shift testing (should grounded)
TABLE Power Ground Signals pins include pins)
100, 128, 113, 130, 108, 120, 126, Name VDD2 VDD3 VSS2 (GND) VSS3 (GND) VSS3 (GND) VDDPP VDDAP VSSAP VSSPP Description Digital power supply (for core cells) Digital power supply (for cells) Digital ground (for core cells) Digital ground (for cells) Digital ground (for cells) Digital power PCLK Analog digital powers PCLK Analog ground PCLK Digital ground PCLK
PBLCK VDDPP which internally tied together with VDDAP) VGAHS GND) VDD3) PCLKIN GND)
name
VGAHS INTN RSTN VDD3 CSYNC POWERDN OVCLK
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name
PBGRN7 PBRED0 PBRED1 PBRED2 PBRED3 VDD3 VSSPP VSSAP VDDAP PBCLK PACLK
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T-0911/0912 V0.4
name
OVFB VDD2 PBBLU0 PBBLU1 PBBLU2 PBBLU3 PBBLU4 PBBLU5 PBBLU6 PBBLU7 VDD3 PBGRN0 PBGRN1 PBGRN2 PBGRN3 PBGRN4 PBGRN5 PBGRN6
name
PBRED4 PBRED5 PBRED6 PBRED7 VDD2 PVSYNC VDD3 PHSYNC PABLU0 PABLU1 PABLU2 PABLU3 PABLU4 PABLU5 PABLU6 PABLU7 VDD2 PAGRN0 PAGRN1 PAGRN2 PAGRN3 PAGRN4
name
PAGRN5 PAGRN6 PAGRN7 PARED0 PARED1 VDD3 PARED2 PARED3 PARED4 PARED5 PARED6 PARED7
name
IABLU1 IABLU0 IACLK IBCLK (YUVLLC) COAST VDD2 RGHS PCLKIN IAVSYNC IAHSYNC IBRED7 (YIN7/YUV7) IBRED6 (YIN6/YUV6)
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name
IARED7 IARED6 IARED5 IARED4 IARED3 VDD2 IARED2 IARED1 IARED0 IAGRN7 IAGRN6 IAGRN5 IAGRN4 IAGRN3 IAGRN2 IAGRN1 IAGRN0 VDD3 IABLU7 IABLU6 IABLU5 IABLU4 IABLU3 IABLU2
name
IBRED5 (YIN5/YUV5) IBRED4 (YIN4/YUV4) IBRED3 (YIN3/YUV3) IBRED2 (YIN2/YUV2) IBRED1 (YIN1/YUV1) IBRED0 (YIN0/YUV0) VDD2 IBGRN7 (YUVLLC2) IBGRN6 (YUVVS) IBGRN5 (YUVHS) IBGRN4 IBGRN3 IBGRN2 (YUVVREF) IBGRN1 (YUVHREF) IBGRN0 (YUVCREF) CLAMP IBBLU7 (UVIN7) IBBLU6 (UVIN6) IBBLU5 (UVIN5) IBBLU4 (UVIN4) VDD3 IBBLU3 (UVIN3) IBBLU2 (UVIN2) IBBLU1 (UVIN1) IBBLU0 (UVIN0)
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input port
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Functional description Blocks
input port supports interlaced video streams provides connection most common decoder ICs. This chip supports 8-bit 4:2:2 (CCIR 656), 16-bit 4:2:2 video input. Each input format binary offset complement. input formats tabulated below. selection inputs activated setting YUVF (bit INCTR1 hex) bit.
TABLE Signal
YIN7 YIN6 YIN5 YIN4 YIN3 YIN2 YIN1 YIN0 UVIN7 UVIN6 UVIN5 UVIN4 UVIN3 UVIN2 UVIN1 UVIN0
16-bit 4:2:2
8-bit 4:2:2 (CCIR-656)
timing format shown below: FIGURE INPUT format timing. YUV422 BCLK HREF CREF BR_Y BB_UV CCIR-656 BCLK HREF CREF BR_Y
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input format timing
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chip supports bits bits input. bits input, there four formats chosen INCTR1(3:2) when IRGBEN=1, IRGB24=0. RGB24 bits, IREGBEN=1 IRGB24=1. single port input from either port. Here format timing. FIGURE INPUT format timing:
RGB24 ACLK RGB0 ARED,AGRN,ABLU RGB48-00 INCTR1(3:2)=00 135MHz ACLK RGB0 ARED,AGRN,ABLU BCLK RGB1 BRED,BGRN,BBLU RGB48-01 INCTR1(3:2)=01 135MHz ACLK RGB1 ARED,AGRN,ABLU BCLK RGB0 BRED,BGRN,BBLU RGB48-10 INCTR1(3:2)=10 135MHz ACLK RGB0 ARED,AGRN,ABLU BCLK RGB1 BRED,BGRN,BBLU RGB48-11 INCTR1(3:2)=11 135MHz ACLK RGB1 ARED,AGRN,ABLU BCLK BRED,BGRN,BBLU
RGB1
RGB2
RGB3
RGB4
RGB2 RGB3
RGB4 RGB5
RGB6 RGB7
RGB8 RGB9
RGB3 RGB2
RGB5 RGB4
RGB7 RGB6
RGB9 RGB8
RGB2 RGB3
RGB4 RGB5
RGB6 RGB7
RGB8 RGB9
RGB3 RGB0 RGB2
RGB5 RGB4
RGB7 RGB6
RGB9 RGB8
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Input/output window definition
This section describes input window. signals IH_PULW, IH_ASTART IH_TOTAL count from falling edge. IH_ASTART= IH_AWIDTH then first last active data respectively. IV_ASTART=n IV_ACTIVE then fist active line last active line Ln+w-1 FIGURE INPUT WINDOW PARAMETER:
Dn+1Dn+2.Dn+w
IH_active
IH_AWIDTH IH_ASTART IH_PULW IH_TOTAL
L1L2L3.Ln-1Ln.Ln+w-1 IV_active IV_AWIDTH IV_TOTAL
IV_ASTART IV_AODDS IV_ASTART
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FIGURE Output Window parameters.
T-0911/0912 V0.4
Output window parameter shown following figure.
PH_ACTIVE
UNIT ICLK PHS_PWIDTH BH_START PH_ASTART
BH_END PH_TOTAL
PH_AWIDTH
PVS_PWIDTH UNIT LINE
BV_START
PV_ASTART
PV_TOTAL
BV_END
PV_AWIDTH
OUTPUT ACTIVE WINDOW
Hardware Mode Detection (HMD)
Hardware mode detection detects presences frequencies
PVDE
Background Color defined BKCOL
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ZuracII/ZuracIII
Sync Green IAHSYNC VGAHS RGHS Panel
CSYNC Sync Slicer
HMD_EN
Scaler output format
Serial Note: IAHSYNC line-locked generated
Scaling
Zurac performs scaling function without extra frame buffers. Based chosen scaling factor, order calculate output panel Hsync from input Hsync, have program some parameters such SPH_EMU SIH_EMU. formula SPH_EMU[10:0] value IH_TOTAL/VSf where vertical scaling factor. better understanding obtained following example: with input that IH_TOTAL pixels 1.6, SPH_EMU 800/1.6 500. ZURAC also provides free running mode setting BYPASS this mode, without referring input Hsync, output panel Hsync generated setting SIH_EMU. formula SIH_EMU[11:0] value (PH_TOTAL*VSf) where vertical scaling factor. example output mode, PH_TOTAL 1344 pixels vertical scaling factor 1.6, then register SIH_EMU 1344*1.6 2150. detail description scaler-related registers, please refer registers Hex.
TABLE scaling factor each display mode Zoom 800*600 SXGA SVGA 1280*1024 1152*864 1024*768 800*600 640*480 25/36 25/32 (576) (576) =1.25
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Input mode
Zoom 1024*768 32/25 0.75 =0.8888 =1.28 =1.6
Zoom 1280*1024 11/10 (1267) 32/27 17/10 (1020) 32/15
Resolution
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Input mode Resolution TEXT 640*400 640*350 720*400 1.25 1.25 10/9
T-0911/0912 V0.4
Zoom 800*600 12/7 1.25 64/45 <-7/5 (1008) 16/13
Zoom 1024*768 48/25 17/8 (743.75) (760) 16/13
Zoom 1280*1024 16/9 (1000) 29/10 (1015) 64/25 <-2.5 (1000) 64/39 <-1.6 (998.4) 32/15 16/9
832*624
25/26
25/26
20/13
NTSC
720*(240*2) 720*(288*2)
10/9 10/9
10/9 (533.3) 25/24
36/25 (1036) 36/25 (1036)
16/9 16/9
REGISTER FUNCTION
SDnAHhinc
Addr (hex)
SALGO[1:0]
HSD_EN
VSD_EN
SAHhinc[3:0]
Brightness contract control
FIGURE Function contrast followed brightness control each RGB.
scaled video R/G/B
limiter
video R/G/B gamma correction)
contrast[7:0] brightness[7:0]
scaled signals sent contrast followed brightness correction circuit each R/G/B channel. contrast control uses 8-bit signal multiply value from fact, choices 255/128, 254/128,
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128/128, 1/128, brightness correction uses 8-bit signal offset value from -128 (the choices 127, 126, -127, -128). control signals BRIGHTNESS[7:0] CONTRAST[7:0] programmable serial interface. formula CONTRAST[7:0] value ((CONTRAST+128) 256)/128 where CONTRAST range [255,0]. brightness control, signal BRIGHTNESS[7:0] interpreted complement value. These settings tabulated
TABLE Contrast correction MSB=0
contrast[7:0] multiply value contrast[7:0] multiply value 7f(hex)
255/128
ff(hex) 127/128
254/128
126/128
130/128
2/128
129/128
1/128
128/128
0/128
Contrast correction MSB=1
Brightness correction MSB=0 brightness[7:0] offset value brightness[7:0] offset value 7f(hex) ff(hex) -126 -127 -128
Brightness correction MSB=1
contrast=255/128 contrast=1
contrast=64/128
contrast=1/128 contrast=0/128
Gamma Correction Tables
Gamma correction tables implemented after Brightness/Contrast block provide color-mapping data. tables activated setting GAMMAUSE (MSB MISCTR0 hex) also by-pass gamma correction function resetting GAMMAUSE Through three gamma table registers (GRWADDR, GGWADDR GBWADDR) data representing gamma curves into RAMs sequentially. These 10-bit gamma tables programmed writing first bits high byte eight
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bits byte first entity then second repeatedly program register GRWADDR times (high bytes entities). This will gamma curve into table (the first 10-bit data written into address 256th data written into address 255). similar way, program tables Green Blue channels.
OSD, CLUT, Dithering
chip t0911/0912 embeds Screen Display function human interfacing. designed display colored patterns, icons characters onto screen. character fonts (downloadable from MCU) provided application Multi-language TV/Monitor. Graphic Character Fonts produce effect pixel based graphic display, which allows impressive display customized pattern. symbols logos. provides plentiful features enhance appearance displayed character fonts. Each character have colors colors) blinking option. shadowing modes (including bordering, boxing etc.) provided together with background colors. Multiple overlapping windows, wipe-in wipe-out from directions create more flexible user interface. versatile choice display font color, background/shadow/window color, shadow modes (including bordering graphic character mode) leads unique style. Some dynamic features, such built-in see-through curtain effect, two-direction wipe in/out, character basis blinking, hardware overlapping windows etc. also enhance image menu. There 16x16 CLUT (color look-up table) which provides programmable color palette internal/external background color. color index bus, namely R/G/B/I, used address CLUT which defines colors background color. content index selection CLUT programming serial interface. mapping 16-bit RGB565 color 24-bit true color depicted following figure. format converter function panel also supports dithering function that programmed DITHER_ON (bit OUTCTR0, i.e. Hex)
FIGURE Color look-up table internal, external, background color
10-bit gamma correct table
R/G/B/I
Dithering
External
R/G/B/I
Internal Background color
16x16 CLUT
Format Converter Panel (with alpha blending)
programming serial interface
CLUT_ALPHA[3]=1, readout= means alpha_blending means alpha_blending
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Clock system
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t0911/0912 takes clocks from external ADCs video decoder: namely IACLK/IBCLK. default condition that input video data will latched rising edges IACLK/IBCLK. There control INCTR1(7) which invert phase IACLK/IBCLK. sense, when INCTR1(7) high, input data latched falling edge IACLK/IBCLK. output PACLK/PBCLK also similar function. OUTCTR0(4) used control phase PACLK/PBCLK called PHCLK). addition this phase tuning, OUTCTR0(3:2) choose different phases PHCLK (the delays around 6ns). panel interface choose either PACLK PBCLK different driving capabilities, namely 16mA. pclk obtained either from external source (from PCLKIN pin) generated from internal PLL. This that synthesizes clock panel programmed 2-wire serial bus. There registers that programmed generates clocks different display modes. registers block diagram depicted follows:
FIGURE Block diagram control registers that generates clock
14.31818
Xtal Osc.
Input Divider (NR)
Output Divider (NO)
PCLK
R[4:0]
Feedback Divider (NF) F[8:0]
OD[1:0]
PLLPSET0 hex)
PLLPSET1 hex) PLLCNTL hex)
BACLK_SEL
program parameter PLLPSET0 FI(7 downto
F7(MSB), (LSB) feedback 9-bit divider default value will PCLK 65MHz
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PLLPSET1 FI(8) ODI(1 downto RI(4 downto
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F8(MSB), OD1, OD0, (LSB) feedback 9-bit divider, (MSB) (LSB) control pins output divider, pins input 5-bit divider
PLLCNTL Output enable bypass control Pclk Mclk PLL. IBCLK IACLK selection
POE(MSB), PBP, MOE, MBP, BACLK_SEL (LSB) where freq Output Enable Pclk (default ByPass control Pclk (default MOE/MBP Mclk PLL, care. will power down mode external POWERDN activated. BACLK_SEL IBCLK IACLK selection. ICLK IBCLK/2 (for LLC2) ICLK IACLK control BACLK_SEL moved MISCTR1.
Note: frequency derived from frequency synthesizer formulated follows: PCLK NF/(NR*NO). Where Fin*NF/NR, output freq VCO, should range MHz. freq PCLK modified programming register values divider should substrating actual value i.e. divided what want, then binary values input control register should (e.g. 000000110). output divider (NO) control register following. (bypass) will being tested, otherwise reset normal function.
TABLE Output Divider
OD1=0 OD0=0 OD1=0 OD0=1 OD1=1 OD0=0 OD1=1 OD0=1
Divided
example, want output freq clock Fin=14.31818 MHz, need NF/NR 140/10, OD=2. sense, NF=010001010(bin), NR=01000, OD=10. Another example, want output freq clock panel Fin=14.31818 MHz, need NF/NR 227/25, OD=2. sense, NF=227-2=e1(hex), NR=25-2=17(hex), OD=10(bin).Therefore, need program register PLLPSET0 (BA) with value e1(hex) PLLPSET0 (BB) with
5.10 Power down
chip enters into power down status setting POWERDN pins high. system returns normal after POWERDN low.
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5.11 Communication Protocol
T-0911/0912 V0.4
power down status, circuits except mode detection circuit which always working.
control t0911/0912 achieved through kinds serial transfer, namely, 2-wire serial interface. selection between kinds interface done automatically hardware. 2-wire serial interface also supports read back some control registers. communication between t0911/0912 performed 2-wire serial interface interface. industrial standard 2-wire serial interface supports bidirectional transfer (READ WRITE) with baud rate bps. 3-wire interface provide baud rate.
5.11.1 2-wire serial interface
t0911/0912 supports industrial standard 2-wire serial interface, which consists bidirectional data line clock line. 2-wire serial slave address this chip 1111000(binary). definition basic 2-wire serial interface protocol illustrated follows. detailed timing operation protocol, please refer standard 2-wire serial specification.
START RESTART)
(LOW) (HIGH) DATA SUBADDRESS
STOP
2-WIRE SERIAL DEVICE ADDRESS WRITE; READ)
Fig.11 definition basic 2-wire serial timing protocol
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5.12 Mode detection
T-0911/0912 V0.4
hardware mode detection circuit functions mode detection blocks monitor micro-controllers. example, detect presences, polarities, frequencies sends interrupt certain programmable events, etc. Besides, there Vsync separation that handles types Csync inputs (depicted following figure) generate corresponding Vsync pulse which used COAST signal into chips. Generally, these Csync signals come from Hsync plus Vsync Hsync exclusively Vsync added serration pulse. Composite sync coast signal generation depicted following figure.
Hsync Vsync Csync Csync Csync Csync Csync Csync
5.13 Auto-Adjustment
These functions will supported Zurac: Searching line H-start, H-end line designation entire screen searched) segment (including full-line) line frozen values read host. Optimum phase searching calculation difference pixels window (including entire screen) which defined (for each RGB, RGB, frame, some frames) pixels window (including entire screen) defined (for each RGB, RGB, frame, some frames) will also performed. While only difference operation (selected programming) available intra-frame operation, difference operations simultaneous available inter-frame operations.
Besides, there four functions supported Zurac, namely, line frozen, line-edge (high-low-high low-high-low), start-end, start-end searching. procedure follows: Define compare window: When value color channel (designated AACMP[1:0]) greater than ARGB_MIN, valid data found. parameter AH_START define starting location searching window horizontal direction. vertical searching, start point first line counted from rising edge
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IVS. Check Vstart Vend: When line contain greater then valid data. first valid line named Vstart last valid line Vend. Check Hstart Hend: parameter AMLNUM designates line perform position searching Hstart Hend. Hstart first valid data Hend last valid data AMLNUM line. values Hstart Hend also stored that value accessed host micro-controller FIGURE Parameters definition auto adjustment.
AH_START AH_ACT Hstart Vstart AMLNUM Hend
2000
AXLNUM
Vend
Check LHL: pixel data chosen AACMP(1:0) greater than ARGB_MAX called H-data, lower then ARGB_MIN called L-data. AXLNUM define which line check sequential data H-L-H L-H-L, record pixels position data. freeze line buffer read content, should designate line address (counted from first active line) starting pixel (counted from active region) then read same address AFZREAD sequentially. data updated frame check continuously.
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APNUM0 with AXP0R, AXP0G, AXP0B
T-0911/0912 V0.4
FIGURE Auto adjustment circuits that search high-low-high low-high-low along line:
APNUM2 with AXP2R, AXP2G, AXP2B
APNUM1 with AXP1R, AXP1G, AXP1B
DATA
DATA
pixel
ARGB_MAX
ARGB_MAX
ARGB_MIN
APNUM1 with AXP1R, AXP1G, AXP1B
ARGB_MIN
pixel
APNUM0 with AXP0R, AXP0G, AXP0B
pixel
APNUM2 with AXP2R, AXP2G, AXP2B
CASE1 :HLH
CASE2 :LHL
Inter intra-frame (sum difference) calculations
AWHSTART
window (range intra-frame calculation. Selection sum-of-diff SOD_INTRA bit.)
SOD_FRAME_NO (range inter-frame calculation. Both sum-of-diff always calculated.)
2000
AWVEND
AWVSTART
AWHEND
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Register Definition:
T-0911/0912 V0.4
2-wire serial slave address this chip 1111000 (bin): TABLE PANORAMA SUB-ADDRESS REGISTER
NIBBLE SUBADDRESS
Addr (hex)
ID_V
TUS0
TUS1
INTC
FBC_
IN_CTR
OUT_CTR
FB_CTR
MISCTR
INPUT WINDOW PARAMETERS
IVS_
AUTO ADJUST PARAMETERS OUTPUT WINDOW PARAMETERS BACKGROUND WINDOW PARAMETERS WINDOW PARAMETERS PARAMETERS SCALING PARAMETERS SCALING PARAMETERS AUTO ADJUST PARAMETERS
MISC (CLAMP)
IHV_DELAY4WRAP
AUTO ADJUST PARAMETERS AUTO ADJUST PARAMETERS AUTO ADJUST PARAMETERS
AUTO ADJUST PARAMETERS AUTO ADJUST PARAMETERS PARAMETERS PARAMETERS
BRIGHTNESS, CONTRAST
BRIGHTNESS, CONTRAST, GAMMA, CLUT, ALPHA BLENDING
freq
HARDWARE MODE DETECTOR PARAMETERS
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TABLE CONTROL REGISTER
REGISTER FUNCTION
Chip Version (ID_VER) Input Control Register0 (INCTR0) Input Control Register1 (INCTR1) Output Control Register0 (OUTCTR0) Output Control Register1 (OUTCTR1) Output Control Register2 (OUTCTR2) control register0 (OSDCTR0) control register1 (OSDCTR1) control register0 (FBCTR0) control register1 (FBCTR1) control register2 (FBCTR2) Misc. Control Register (MISCTR0) Misc. Control Register (MISCTR1) Status Register (STATUS0)/RE Status Register (STATUS1) Interrupt Control Register (INTCTR) test pattern (FBC_PAT) MPAT_R2 MPAT_R1 INTEN AACMP(1) AACMP(0)
GAMMAUSE
T-0911/0912 V0.4
Addr (hex)
DIS_IHSPOL
IHS_POL
IRGB24AB
DEINTERL ACE_ON
DE_ONLY
DE_DELA Y(2)
DE_DELA Y(1)
DE_DELAY
ICLK_INV
ODD_POL
INCODE
YUVF
IRGB48(1)
IRGB48(0)
IRGB24
IRGBEN
RELD_FH
DITHER_ON PHS_POL
DITHER_ON POUT_OFF
PCLK_INV/ PHCLK_INV
PCLK_OP BKCOL
PCLK_OP BKCOL DITH ER_FDBK_
PDE_POL
PRGB48
PVS_POL
BKFRC
BKCOL
BKCOL PABCLK_E
PCLKI N_EXT
OVS_ VACTIVE
VITORENDL
VINT
TEST0
SPLIT
HTONE
MONITOR
IODS_EN
FILL_PAT
LMR_REQ
IFIFO_COF
IFIFO_COF REF_CYC MCLKPH FREEZE
FBDB
RAMOD
RAMOD REF_RASL ACKPH BYPASS
RAMOD REF_RASL ACKPH DE_DIM_E
REF_CYC
REF_CYC MCLKPH
REF_RASL MCLKPH EOSD_EN
REF_RASL MCLKPH EOSDFR
CREF_INV
VHSYN_SEL
DITHE R_RNG(1)
DITHE R_RNG(0)
EOSD_SYN
CLAMP_O
BACLK_S ADCLKEN
IIC_ACT_DI RECT
OFUDF
IFOVF
LBUDF
LBOVF
AXL_RDY
AFREEZE _RDY
ASOD_RD
AML_RDY
OFUDFEN
IFOVFEN
LBUDFEN
LBOVFEN
IRQEN
MPAT_R0
MPAT_G2
MPAT_G1
MPAT_G0
MPAT_B1
MPAT_B0
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REGISTER FUNCTION
Control Register (SODCTR) Mask Register (SODMASK) Addr (hex)
T-0911/0912 V0.4
SOD_FRAME_NO[3:0]
SOD_INTR
SOD_MASK_BIT[2:0]
SOD_R_M
SOD_G_M
SOD_B_MA
TABLE ADDR (HEX) REGISTER FUNCTION INPUT WINDOW PARAMETER Input Horizontal Active Start(IH_ASTART[10:0]) Input Horizontal Active Width (IH_AWIDTH[10:0]) Input Hsync TOTAL (IH_TOTAL[10:0]) Input Vertical Active Start (IV_ASTART[10:0]) Input Vertical Active Width (IV_AWIDTH[10:0]) Input Vsync TOTAL (IV_TOTAL[10:0]) Input Hsync Pulse Width (IH_PULW[7:0])
MSB:ODD LSB:EVEN
RESET VALUE
01,28
Description This value should least larger than six. default values setting 1024*768@60Hz
04,00
15,14
05,40
17,16
00,23
19,18
03,00
1B,1A
03,26
This register specifies pulse width input Hsync. Within this region input video data forced zero internal circuit. max. allowed value unit iclk). delay input. 4-bit defined VREF_DELAY[3:0] 4-bit HREF_DELAY[3:0]. programming this byte, display video signals have VREF_DELAY*2 lines HREF_DELAY*4 pixels offsets respectively. word, unit VREF delay 2*H-line unit HREF delay pixels 6.75MHz). VREF delay, VREF_DELAY=00 (default) means delay. HREF delay, HREF_DELAY=00 (default) means delay.
Input VREF HREF Delay (IVHREF_DELAY[7:0])
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TABLE
T-0911/0912 V0.4
ADDR (HEX) REGISTER FUNCTION Input Delay (IVS_DELAY[3:0])
MSB:ODD LSB:EVEN
RESET VALUE
Description input delay. 4-bit used. programming these bits, input signal will delayed IVS_DELAY*16 IVS_DELAY*32 pixels (depends IRGB24=1 INCTR1 register 02H). IVS_DELAY=00 (default) means delay.
Input Vsync Delay Wrap Around (IV_DELAY4WRAP[10:0])
7D,7C
00,02
delay input. value (default) means delay means line delay, allowed.)
Input Hsync Delay Wrap Around (IH_DELAY4WRAP[10:0])
7F,7E
00,01
delay input. value (default) means delay means pixel delay, allowed.)
OUTPUT WINDOW PARAMETER Panel Horizontal Active Start (PH_ASTART[10:0]) Panel Horizontal Active Width(PH_AWIDTH[10:0]) Panel Vertical Active EVEN Start (PV_ASTART_EVEN[10:0])
31,30 01,28
Please refer figure Output Window
33,32
04,00
35,34
00,23
This 10-bit register defines Panel Vertical Active Start non-interlaced video Even Field Active Start interlaced video.
Panel Vertical Active Width (PV_AWIDTH[10:0]) Panel Vsync EVEN TOTAL (PV_TOTAL_EVEN[10:0])
37,36
03,00
39,38
03,26
This 10-bit register defines Panel Vertical Active Total Lines non-interlaced video Even Field Active Total Lines interlaced video.
Panel Hsync Pulse Width (PH_PULW[7:0]) Panel Vsync Pulse Width (PV_PULW[7:0]) Panel Vertical Active Start (PV_ASTART_ODD[10:0]) Panel Vsync TOTAL (PV_TOTAL_ODD[10:0])
3D,3C
This register defines Field Active Start interlaced video. This register defines Field Active Total Lines interlaced video.
3F,3E
BACKGROUND WINDOW PARAMETER
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TABLE
T-0911/0912 V0.4
ADDR (HEX) REGISTER FUNCTION Background Horizontal Start (BH_START[10:0]) Background Horizontal (BH_END[10:0]) Background Vertical Start (BV_START[10:0]) Background Vertical (BV_END[10:0]) DE_DIM Horizontal Start (DMH_START[10:0]) DE_DIM Horizontal (DMH_END[10:0]) DE_DIM Vertical Start (DMV_START[10:0]) DE_DIM Vertical (DMV_END[10:0]) DE_LIGHT[15:12]
4F,4E
MSB:ODD LSB:EVEN
RESET VALUE
01,28
Description Please refer figure Output Window default values setting 1024*768@60Hz
41,40
43,42
05,28
45,44
00,23
47,46
03,23
49,48
00,00
This parameter used DE_DIM_EN start points counted from display active region. Please refer figure Output Window default values setting 1024*768 4-bit 4F,4E register will used lightness control function under condition that DE_DIM_EN (Bit MISCTR1) DE_LIGHT[15:12] used adjust contrast area.
4B,4A
04,00
4D,4
00,00
03,00
control register Font address [5:0]
Font write address (auto increment). There address downloadable fonts Font LSB, each font composed 20x12 bits Font Attribute Font code Font code Display RAM, address range (0-255) Display RAM, high address range (256-511) (LSB) bits rate selection
FONT [5:0] FONT [11:6] attribute FONT Code(OSD_AT[4:0]) FONT code address(OSD_DT[7:0]) Display address LSB(0~255) (OSD_ADL[7:0]) Display address MSB(256-511) (OSD_ADM[7:0]) freq default setting background color (OSD_SPDEF[3:0]) first display ROW(OSD_SROW[3:0])
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TABLE
T-0911/0912 V0.4
ADDR (HEX) REGISTER FUNCTION Horizontal Start Window(OSD_HPOS[6:0]) Vertical Start Window(OSD_VPOS[5:0]) control register2 (OSD_CTRL2) control register (OSD_CTRL) SCALING PARAMETER Emulated period ICLK (SPH_EMU[11:0])
61,60
MSB:ODD LSB:EVEN
RESET VALUE
Description
please refer more detailed description registers
05,40
period panel counted input clock ICLK. This value calculated input H_TOTAL/Vsf where vertical scaling factor. period input counted panel clock PCLK. This value calculated output H_TOTAL*Vsf where vertical scaling factor. Note that PCLK time fast PHCLK PRGB48 (Please refer OUTCTR0)
Emulated period PCLK (SIH_EMU[11:0])
63,62
05,40
2000
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TABLE
T-0911/0912 V0.4
ADDR (HEX) REGISTER FUNCTION SAHdx[6:0], SAHdy[6:0], SDnAHhinc[7:0]
MSB:ODD LSB:EVEN
RESET VALUE
01,00,
Description AHhinc= floor(8*Hsf), AHdy/AHdx= 8*Hsf AHhinc. 2-bit SDnAHhinc defined SALGO scaling algorithm selection, where SALGO chooses BCubic (default), SALGO selects SINC, SALGO selects SINC, SALGO chooses BLinear interpolation. algorithms order sharpness smoothness SINC, BCubic, SINC, BLinear. bits SDnAHhinc, H_SD_ON V_SD_ON, used enabling scaledown operations, i.e. SD_ON=0 (default) scaling SD_ON=1 scaling down,
6C,6D
Vertical Nume(SV_NUME[5:0]) Vertical Deno(SV_DENO[5:0])
Vnume/Vdeno (scaling factor direction) Vnume/Vdeno (scaling factor direction) scaling down, SDNHhinc= floor(8/Hsf), SDNHdy/SDNHdx= 8/Hsf SDNHhinc. Note that should SHdx[6:0]=01, SHdy[6:0]=00, SHhinc[3:0]=10 scaling down operation. Also note that SDNHdx[6:0]=01, SDNHdy[6:0]=00, SDNHhinc[3:0]=08 should scaling operation. (pulse width modulated) signal used backlight control.The default value means output while value (hex) integrated capacitor almost high signal.
71,72,
01,00,
MISC PWM[7:0]
2000
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TABLE
T-0911/0912 V0.4
ADDR (HEX) REGISTER FUNCTION Clamp pulse starting setting register (CLAMP_STA) Clamp pulse width setting register (CLAMP_WIDTH) AUTO Adjust Register
MSB:ODD LSB:EVEN
RESET VALUE
Description starting point clamp pulse setting. Counted from falling edge sync pulse IACLK. width clamp pulse IACLK (1.2us suggested) Please refer AACMP(1:0), which MISCTR1, functions apply
line window calculation (AWVSTART[10:0]) last line window calculation (AWVEND[10:0]) pixel window calculation (AWHSTART[11:0]) last pixel window calculation (AWHEND[11:0]) resulting value calculation (ASUM[31:0]) resulting value difference calculation (ASOD[31:0])
21,20
00,00
Define range intra-frame operation.
23,22
00,00
25,24
00,00
27,26
00,00
2B,2A ,29,28 2F,2E ,2D,2C
00,00
00,00
Check status (ASOD_RDY STATUS1, ready not) before reading results inter-frame operation. Note that results both difference simultaneously available.
resulting value calculation boundaries (ABDSUM[23:0]) Control Register (SODCTR[7:0])
76,75,
00,00
Check status (AML_RDY STATUS1, ready not) before reading results this operation. SODCTR[7:0], SOD_FRAME_NO[3:0], used designate number frames involved inter-frame operations. actual number frame SOD_FRAME_NO e.g. SOD_FRAME_NO=0 means only frame involved. SOD_FRAME_NO=0f (hex) means frames involved. SODCTR[7:0], SOD_INTRA, used select intra-frame operation sum, (sum difference).
2000
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TABLE
T-0911/0912 V0.4
ADDR (HEX) REGISTER FUNCTION Mask Register(SODMASK[7:0])
MSB:ODD LSB:EVEN
RESET VALUE
Description SODMASK[7:0], SOD_MASK_BIT[2:0], used select number bits operation. There five possibilities. SOD_MASK_BIT=000, bits calculated. SOD_MASK_BIT=001, cared. While SOD_MASK_BIT=1xx, bits cared. SODMASK[7:0], SOD_R_MASK, SOD_G_MASK, SOD_B_MASK, used select color channels operation, e.g. SOD_R_MASK=1, channel involved calculation. default state channels calculated.
Maximum Threshold (ARGB_MAX[7:0]) Minimum Threshold (ARGB_MIN[7:0]) Freeze line address(AFZLADDR[10:0]) Freeze line pixel start address(AFZHSTART[10:0])
Designate threshold value either Designate threshold value either Designate line frozen read host. line number counted from active region. Designate line frozen read host. pixel number counted from active region. Please refer
OUTCTR0 register
83,82
00,00
85,84
00,00
Freeze line read address (AFZREAD[7:0])
After registers AFZLADDR AFZHSTART designated, this register read sequentially content frozen line buffer.
2000
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TABLE
T-0911/0912 V0.4
ADDR (HEX) REGISTER FUNCTION line chosen check horizontal start (AMLNUM[10:0])
MSB:ODD LSB:EVEN
RESET VALUE
00,00
Description Designated host, auto adjust function searches (horizontally) starting ending pixels along line. programmed, entire screen covered H_start H_end points searching. After AMLNUM=00 searching, this address will filled with line number line maximum length. there more than one, line will recorded.) word, AMLNUM=00 searching will require writing this address every operation.
89,88
line exceeds ARGB_MIN (AVSTART[10:0]) last line exceeds ARGB_MIN (AVEND[10:0]) pixel exceeds ARGB_MIN position line (AMLHSTA[10:0]) last pixel line exceeds ARGB_MIN position (AMLHEND[10:0]) value pixel line that exceeds ARGB_MIN value last pixel line that exceeds ARGB_MIN Line number (AXNUM[10:0]) low-high-low high-low-high searching pixel position (AXPNUM0[10:0])
8B,8A
00,00
8D,8C
00,00
8F,8E
00,00
91,90
00,00
SOD_INTRA (SOD, difference), number read should minus one. SOD_INTRA (SOD, difference), values available.
92,93,
00,00,
95,96,
00,00,
SOD_INTRA (SOD, difference), values available.
99,9
00,0
00,0
pixel low-high-low high-low-high (please refer figures low-high-low high-low-high searching) pixel low-high-low high-low-high pixel low-high-low high-low-high
pixel position (AXPNUM1[10:0]) pixel position (AXPNUM2[10:0])
9F,9
00,0 00,0
2000
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TABLE
T-0911/0912 V0.4
ADDR (HEX) REGISTER FUNCTION pixel value pixel value pixel value PX_AS_ALINE[3:0]
MSB:ODD LSB:EVEN
RESET VALUE
00,00,
Description SOD_INTRA (SOD, difference), values available. SOD_INTRA (SOD, difference), values available. SOD_INTRA (SOD, difference), values available. threshold number pixels that will treated active line. 4-bit will used. default number least pixels will treated active line. leading edge searching window (counted from leading edge sync pulse). trailing edge pixels before next sync pulse. value AH_START should least larger than six. overflow hex) color value been detected line.
A0,A 1,A2
A3,A 4,A5
00,00,
A6,A 7,A8
00,00,
START point AUTO ADJUST compare (AH_START[10:0])
00,10
overflow been detected line (AML_OVERFLOW) channel, channel, channel, other bits reserved) Brightness, Contrast, Gamma, CLUT, ALPHA BLENDING RCONTRAST[7:0]
level contrast control input signal multiplied value ((CONTRAST+128) 256)/128 where CONTRAST range [255,0].
RBRIGHTNESS[7:0]
level brightness control ->127,., -1,., -128 i.e. input data added complement value.
GCONTRAST[7:0] GBRIGHTNESS[7:0]
level contrast control level brightness control
2000
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TABLE
T-0911/0912 V0.4
ADDR (HEX) REGISTER FUNCTION GAMMA table write address(GRWADDR[7:0]) GAMMA table write address(GGWADDR[7:0]) GAMMA table write address(GBWADDR[7:0]) (The table write address will auto increased upon each writing)
MSB:ODD LSB:EVEN
RESET VALUE
Description Each gamma-correction table 256x10 (look-up table) which updated writing these ports. Each entity composed high bytes which share same write address. byte content written followed high byte content. Lower entity data sent certain channel (e.g. followed next higher entity. word, channel updated sending data entity till final entity 255. Then channel followed channel
CLUT write address (CLUTWADDR[7:0])
This 16x16 Color written host from this port. First lower byte data sent entity, then followed higher byte data, color index filled followed color index until color index final one. 16-bit output this color will interpreted RGB565 format, i.e. bits middle bits bits
2000
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TABLE
T-0911/0912 V0.4
ADDR (HEX) REGISTER FUNCTION CLUT alpha blending (CLUT_ALPHA[3:0])
MSB:ODD LSB:EVEN
RESET VALUE
Description CLUT_ALPHA used indirectly interpretation signal OSD, while CLUT_ALPHA[2:0] used select blending factor between output CLUT output dithered video. CLUT_ALPHA[3]= content CLUT RGB565. content CLUT RGB555. will interpreted CLUT read means alpha_blending off. means alpha_blending alpha_blending internal/external OSD/background color activated, final video panel will equal Video*CLUT_ALPHA[2:0]/8+CLUT* (1-CLUT_ALPHA[2:0]/8). case that CLUT_ALPHA[2:0]=0, final video panel directly from output CLUT. CLUT_ALPHA[2:0]=7, final video Video*7/8+CLUT*1/8.
BCONTRAST[7:0]
level contrast control input signal multiplied value ((CONTRAST+128) 256)/128 where CONTRAST range [255,0].
BBRIGHTNESS[7:0]
level brightness control ->127,., -1,., -128 i.e. input data added complement value.
program parameter PLLPSET0 FI(7 downto
F7(MSB), (LSB) feedback 9-bit divider default value will PCLK 65/2
2000
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TABLE
T-0911/0912 V0.4
ADDR (HEX) REGISTER FUNCTION PLLPSET1 FI(8) ODI(1 downto RI(4 downto
MSB:ODD LSB:EVEN
RESET VALUE
Description F8(MSB), OD1, OD0, (LSB) feedback 9-bit divider, (MSB) (LSB) control pins output divider, pins input 5-bit divider
PLLCNTL Output enable bypass control Pclk Mclk PLL. IBCLK IACLK selection
POE(MSB), PBP, MOE, MBP, BACLK_SEL (LSB) where freq Output Enable Pclk (default ByPass control Pclk (default MOE/MBP Mclk PLL, care. will power down mode external POWERDN activated. BACLK_SEL IBCLK IACLK selection. ICLK IBCLK/2 (for LLC2) ICLK IACLK control BACLK_SEL moved MISCTR1.
ID_VER (Chip Version, 00H)
ID_VER 10110010 (bin)
Default
INCTR0(INput ConTrol Register 01H)
DIS_IHSP Auto detecting function polarity input video will checked automatically Auto detecting function polarity input video will disabled Note: polarity input video will checked automatically DEINTER LACE_ON IHS_POL IRGB24A rising edge input will used start sync pulse falling edge input will used start sync pulse Input 24-bit data port Input 24-bit data port Deinterlace function Deinterlace function Note: Panel Vertical Active EVEN Start, Panel Vertical Active Start, Panel Vertical EVEN
Total, Panel Vertical Total should defined before Deinterlace function
Default
DE_ON
sync signals used synchronizing display data. (Display Enable) signal used synchronizing display data.
2000
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INCTR0(INput ConTrol Register 01H)
DE_DEL AY[2:0]
T-0911/0912 V0.4
Default
signal delayed advanced matching display data enable signal. This signal valid only DE_ON=1. 0xx: delay means care) 100: clock delay. 101: clock delay. 110: clock delay. 111: clock delay.
TABLE INCTR1(INput ConTrol Register 02H)
ODD_POL INCLK_IN INCLK invert enable normal input clock invert input clock indicate polarity (inside only) field ACTIVE HIGH field ACTIVE input video code binary offset input video code complement YUV422 YUV422 (CCIR 656) RGB48 input offset RGB48 input offset RGB48 input offset RGB48 input offset (See attached graphic explanation)
Default
INCODE YUVF IRGB48(1:
IRGB24 IRGBEN
bits input bits input input input
TABLE OUTCTR0(Output ConTrol Register 03H)
RELD_FHADR Reload Freeze Address starting address frozen line which will reloaded high transient detected. Please refer register more detail. dithering (for panel with color depth R/G/B) dithering (for panel with color depth R/G/B) dithering (for panel with color depth R/G/B) dithering Normal PHCLK clock output panel Inverted PHCLK clock output panel (The relationship PHCLK PCLK also defined PHCLK_OP(1:0) PRGB48)
Default
DITHER_ON(1:0
PHCLK_INV
2000
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TABLE OUTCTR0(Output ConTrol Register 03H)
PHCLK_OP(1:0)
T-0911/0912 V0.4
Default
Phase deviation PHCLK with respect PCLK delay Delay unit Delay unit Delay unit (The relationship PHCLK PCLK also defined PHCLK_INV PRGB48. This control delay inversion applies both PACLK PBCLK.) active High display data enable output panel active display data enable output panel Single pixel output panel clock (the frequency PHCLK equal PCLK, phase defined PHCLK_INV PHCLK_OP(1:0)) Double pixel output panel clock (the frequency PHCLK equal half PCLK, phase defined PHCLK_INV PHCLK_OP(1:0))
PDE_POL PRGB48
TABLE OUTCTR1 (OUTput ConTrol Register 04H)
PVS_POL output polarity (inside active High) Negative polarity (active Low) Positive polarity (active High) output polarity (inside active High) Negative polarity (active Low) Positive polarity (active High) Panel output control data disable PHS, PVS,DEN,DAR,DAG,DAB,DBR,DBG,DBB output enabled PHS, PVS,DEN,DAR,DAG,DAB,DBR,DBG,DBB output zero Panel output Force Background color Normal Panel output Output Panel forced Background color, color selected BKCOL[3:0] Panel output Background color select signals. These signals share look-up table with generate colors.
PHS_POL
POUT_OFF
BKFRC
BKCOL[3:
TABLE OUTCTR2 (OUTput ConTrol Register 05H)
reserved PCLKIN_ OVS_VAC TIVE DITHER_ FDBK_O PCLK, panel clock, generated. PCLK generated internal PLL. PCLK from PCLKIN external source). output generated using Overlay Zurac1. Vertical display active signal. error resolution change back dithering feedback path disconnected. feedback path connected dithering.
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TABLE
reserved PABCLK_
T-0911/0912 V0.4
OUTCTR2 (OUTput ConTrol Register 05H)
PACLK PBCLK output will enabled PACLK, which drive capability 8mA, enabled. (PBCLK disabled) PBCLK, which drive capability 16mA, enabled. (PACLK disabled)
TABLE MISCTR0(Misc. ConTrol Register 0AH)
GAMMAUSE CREF_INV GAMMA correction table each R,G, Bypass GAMMA table GAMMA look-up table CREF invert enable Normal logic polarity (clock enable CREF=1) inverted CREF (clock enable CREF=0) Port synchronization edge ACLK rising edge ACLK falling edge Normal function Freeze function External will disabled External will enabled (The internal enabled IOSD_EN OSDCTR1 register) EOSDFR case EOSD_EN (bit Internal will front external External will front internal (Default) Panel free running sync master. this mode, input output frames synchronized. sense, input sync master that generate Panel Note: order activate free-run mode, micro-controller should choose BYPASS this, input data ignored, necessary, setting BKFRC= background colors sent panel. DE_DIM_ area (defined DMH_START, DMH_END, DMV_START, DMV_END) display enabled this
Default
VHSYN_S
FREEZE EOSD_EN
BYPASS
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TABLE MISCTR1(Misc. ConTrol Register hex)
AACMP(1:
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Default
Choose compare. This setting applicable Auto Adjust functions (please refer AUTO Adjust registers detail description). reserved compare compare compare DITHER choices. EOSD data latch uses OVCLK EOSD data latch uses inverse OVCLK CLAMP pulse will generated according register (hex) clamp pulse sent out. clamp tri-state Output clock ADCCLKP ADCCLKN disable. this case, input data synchronized IACLK IBCLK input clocks Output clock ADCCLKP ADCCLKN enable external double ADCs (ADCCLKP IACLK divided while ADCCLKN inversed ADCCLKP)
DITHER_ RNG(1:0)
EOSD_SY NSEL CLAMP_O ADCLKEN
BACLK_
BACLK_SEL IBCLK IACLK selection. ICLK IBCLK/2 (for LLC2) ICLK IACLK
2-wire serial parameters activated until next retrace period. 2-wire serial parameters activated upon data received
IIC_ACT_ DIRECT
TABLE STATUS0 (Status Register 0CH)
reserved LBUDF LBOVF Normal Line Buffer underflow. Normal Line Buffer overflow Normal Internal Interrupt
Default
STATUS1 (Status Register 0DH)
reserved AXL_RDY AFREEZE_ auto adjustment, setting line function will performed. This status will function completed. This RD/WR bit. auto adjustment, this status will freeze function completed.This only status bit.
2000
Default
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STATUS1 (Status Register 0DH)
AML_RDY ASOD_RD
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Default
auto adjustment, setting (sum difference) function will performed. This status will function completed. This RD/WR bit. auto adjustment, setting line function will performed. This status will function completed. This RD/WR bit.
TABLE INTCTR (Interrupt Control Register, 0EH)
INTEN reserved LBUDFEN LBOVFEN IRQEN Disable LBUDF interrupt Enable LBUDF interrupt Disable LBOVF interrupt Enable LBOVF interrupt Disable interrupt Enable interrupt Disable interrupt Enable interrupt
Default
Please refer register INTSRC (D1H, Section Hardware Mode Detector) interrupt control interrupt source identification.
Register Hardware Mode Detector
TABLE register Hardware Mode Detector Zurac Name: HWDCNT (D0H) IntSrc (D1H) SyncStatus (D2H) HperHigh (D3H) VHperLow (D4H) VperHigh (D5H) Enhwd Hper11 Vper3 Vper11 SelDE Falt Hper10 Vper2 Vper10 Hwd_i nten Vint_R FwHalf Hper9 Vper1 Vper9 Vint_re Vint_F Odd_E Hper8 Vper0 Vper8 Vint_fe VfCha nged Vpresence Hper7 Hper3 Vper7 VcntSel Vpolcha Hpresence Hper6 Hper2 Vper6 HVsep HfCha nged Vpolarity Hper5 Hper1 Vper5 HVsep Hpolcha Hpolarity Hper4 Hper0 Vper4
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Name: PulCnt (D6H) HVPwth (D7H) PoutPolPos (D8H) HfpHigh (D9H) HVfpLow (DAH) VfpHigh (DBH) VCoast Delay1
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TABLE register Hardware Mode Detector Zurac EnVout EnHout VPW3
VCoast Delay0
VoutM ode1 VPW2 Vshift3 Hfp7 Vfp3 Vfp9
VoutM ode0 VPW1 Vshift2 Hfp6 Vfp2 Vfp8
HoutM ode1 VPW0 Vshift1 Hfp5 Vfp1 Vfp7
HoutM ode0 HPW2 Vshift0 Hfp4 Vfp0 Vfp6
Htolera nce1 HPW1 VoutPol Hfp3 Hfp1 Vfp5
Htolera nce0 HPW0 HoutPol Hfp2 Hfp0 Vfp4
-R/W Hfp9 Vfp11
-R/W Hfp8 Vfp10
HWDCNT (Hardware Mode Detector Control Register)
(HVsep1 HVsep0): Multiplexer select Vsync source: Csync/DE VsyncSep Hsync VsyncSep Hsync VsyncSep Vsync Hsync Vsync SelDE chosen, i.e. treated kind Csync) (VcntSel): Select Vperiod count time line number time; i.e. Vclk (Hclk/88) line (Vint_fen): Enable interrupt Vsync trailing edge Disabled Enabled (Vint_ren):
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Enable interrupt Vsync leading edge Disabled Enabled (HWD_inten): Enable interrupt from Sync signal changes: frequency Polarity change Disabled Enabled (SelDE): Selection between Csync input Csync mutually exclusive) SelDE HVsep automatically Csync selected selected (EnHWD): Enable Hardware mode detector Disabled; (clock sleeping also save power) Enabled
IntSrc (Interrupt Source; NOTE: flags this register will cleared automatically after read)
(HpolCha): Interrupt caused polarity change polarity changed polarity changed (HfChanged): Interrupt caused frequency change frequency changed frequency changed (VpolCha): Interrupt caused polarity change polarity changed polarity changed (VfChanged): Interrupt caused frequency change frequency changed frequency changed (Vint_F):
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Vsync trailing edge happened (Vint_R):
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Interrupt caused Vsync trailing edge Vsync trailing edge happened
Interrupt caused Vsync leading edge Vsync leading edge happened Vsync leading edge happened
SyncStatus (H/V sync signals status)
(Hpolarity): polarity Hsync Positive polarity (Pulse width smaller than Hperiod) Negative polarity (Pulse width larger than Hperiod) (Vpolarity): polarity Vsync Positive polarity (Pulse width smaller than Vperiod) Negative polarity (Pulse width larger than Vperiod) (Hpresence): presence status Hsync/Csync present Present (Vpresence): presence status Vsync present Present (Odd_Even): Indicate current field field Even field
field/1st field; with earlier sync even field/2nd field; with lagged sync
(FwHalf): Indicate whether Field contains n+1/2 lines (half line) this format (Falt): Indicate whether Field contains alternating lines this format
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HperHigh
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(Hperiod11 Hperiod4): high nibble Hperiod
VHperLow
(Hperiod3 Hperiod0): nibble Hperiod (Vperiod3 Vperiod0): nibble Vperiod
VperHigh
(Vperiod11 Vperiod4): high nibble Vperiod counted clock (Hclk/88) line, depending VcntSel
PulCnt (H/V output pulse control register)
(Htolerance1 Htolerance0): definition frequency/count deviation programmable: counts counts counts counts (HoutMode1 HoutMode0): FreeRun): period HsyncOut programmed 10-bit counter, Hfper. pulse width programmed 3-bit register, (0->0.28us, 1->0.59us, 1.12us, 3->1.40us, 4->1.68us, 5->1.96us, 6->2.23us, ->2.51us) 01(Loopth_st): HsyncOut will snapped rising/falling edge incoming Hsync; pulse incoming Hsync missing, artificial pulse will inserted with pulse width defined HPW. serration pulses still kept incoming Hsync. artificial pulse will inserted after Hperiod/4 counted tolerance parameter) 10(R_aligned): leading edge outputed Hsync aligned with incoming Hsync. However, pulse width defined HPW. pulse occurred midway Hsync during serration period
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suppressed (Hperiod/8 threshold). artificial pulse will inserted while incoming pulse missing 11(Loopth): completely copy shape incoming Hsync (VoutMode1 VoutMode0):
00(FreeRun): period VsyncOut programmed 12-bit counter, Vfper. pulse width programmed register, Vpw, extended bits lines; should able cover back period). output waveform certainly phase with HsyncOut 01(Loopth_st): leading edge VsyncOut will roughly close incoming Vsync, however, snapped leading edge incoming HsyncOut; pulse incoming Vsync missing, artificial pulse will inserted with pulse width defined VPW. tailing edge VsyncOut also close tailing edge inputted Vsync snapped leading edge HsyncOut 10(R_aligned): leading edge VsyncOut will shifted ahead after leading edge Vsync based programmed value, however, snapped leading edge incoming HsyncOut; pulse incoming Vsync missing, artificial pulse will inserted with pulse width defined VPW. pulse width this mode also programmable 11(Loopth): completely copy shape incoming Vsync
(EnHout): Enable HsyncOut pulse Disabled; HsyncOut kept Enabled (EnVout): Enable VsyncOut pulse Disabled; VsyncOut kept Enabled
HVPwth (The Pulse Width sync output)
(Hpw2 Hpw0): pulse width Hsync Output: 000: 4(0.28us) 001: 8(0.59us) 010: 16(1.12us) 011: 20(1.40us) 100: 24(1.68us) 101: 28(1.96us) 110: 32(2.23us) 111: 36(2.51us) (Vpw3 Vpw0):
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T-0911/0912 V0.4
There programmable values pulse width VsyncOut 2*(Vpw lines
PoutPolPos (The polarity sync output position VsyncOut)
(HoutPol): polarity HsyncOut Positive polarity (Pulse width smaller than HsyncOut) Negative polarity (Pulse width larger than HsyncOut) (VoutPol): polarity VsyncOut Positive polarity (Pulse width smaller than VsyncOut) Negative polarity (Pulse width larger than VsyncOut) (Vshift3 Vshift0): Vshift(3) (Leading edge VsyncOut ahead incoming Vsync): 000: Ahead line 001: Ahead lines 010: Ahead lines 011: Ahead lines 100: Ahead lines 101: Ahead lines 110: Ahead lines 111: Ahead lines Vshift(3) (Leading edge VsyncOut after incoming Vsync): 000: Kept same position incoming Vsync 001: After line 010: After lines 011: After lines 100: After lines 101: After lines 110: After lines 111: After lines
VCoastDelay1 VCoastDelay0) When VsyncOut signal going scaler sync signal internally, this signal called VCoast. This control register will generate VCoastDelay delaying designated numbers Hsync rising edge VsyncOut. falling edge almost same VsyncOut.
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VCoast same VsyncOut VCoast rising edge delayed Hsync from VsyncOut VCoast rising edge delayed Hsync from VsyncOut VCoast rising edge delayed Hsync from VsyncOut Make sure VsyncOut width larger number Hsync delay, otherwise VCoast have correct falling edge.
7.10 HfpHigh
(Hfperiod9 Hfperiod2): high nibble free period
7.11 HVfpLow
(Hfperiod1 Hfperiod0): nibble free period (Vfperiod3 Vfperiod0): nibble free period
7.12 VfpHigh
(Vfperiod11 Vfperiod4): high nibble free period
OSDCTR0(OSD control0, CEH)
VINTORENDL VINT then will send pulse upon vertical leading edge will send (active low) pulse when activated vertically normal mode color will defined VINTORENDL test disable test font enable test font Color index background color look-up table Color index background color look-up table Color index background color look-up table Color index background color look-up table
Default
VINT TEST0 CLUT_R CLUT_G CLUT_B CLUT_I
Note that external selection MISCTR0 (Misc. ConTrol Register 0AH) register.
2000
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TABLE OSDCTR1(OSD control1, CFH)
IOSD_EN OSD_RGBI _NEG OSD_BLIN OSD_V_N SPLIT HTONE MONITOR OSD_H_N
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Default
(Space code) spite (Space code) spite Half Tone effect enable BOXING mode Half Tone effect enable BOXING mode mode (Video background overlaid) Monitor mode (Non-OSD part overlaid preset background color) positive polarity negative polarity positive polarity negative polarity positive polarity RGBI negative polarity RGBI Blinking rate, displaying displaying toggled Vsync pulse Blinking rate, displaying displaying toggled Vsync pulse Internal disabled Internal enabled (The external enabled EOSD_EN MISCTR0 register, priorities both OSDs defined EOSDFR MISCTR0)
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FIGURE PQFP160 package range dimensions
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T-0911/0912 V0.4
Copyright trumpion microelectronics inc. 1999
more information Send your e-mail gene.chuang@trumpion.com.tw
trumpion microelectronics inc. reserves right change products specifications without notice.
trumpion microelectronics inc.
12F-5 Sec. Cheng-Teh Taipei, Taiwan, R.O.C. Tel: 886-2-2558-7855 Fax: 886-2-2558-7850
ZURAC
trumpion
microelectronics, Inc.
2000

T-0911/0912 V0.4 Zoom Engine TFT-LCD Monitor AUTO inOSD

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