Programmable Zero Delay Clock Driver clock distribution optimized
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PLL102-108
Programmable Zero Delay Clock Driver
clock distribution optimized Double Data Rate SDRAM application 266Mhz. Distributes clock Input bank differential outputs. Track spread spectrum clocking reduction. Programmable delay between CLK_INT CLK[T/C] from -0.8ns +3.1ns programming CLKINT FBOUT skew channel, from -1.1ns +3.5ns additional skew channels enabled. Four independent programmable skew channels from -0.3ns +0.4ns with step size ±100ps. Support 2-wire serial interface. 2.5V Operating Voltage. Available 48-Pin 300mil SSOP.
CONFIGURATION
CLKC0 CLKT0 CLKT1 CLKC1 CLKC2 CLKT2 SCLK CLK_INT AVDD AGND CLKC3 CLKT3 CLKT4 CLKC4 CLKC5 CLKT5 CLKT6 CLKC6 CLKC7 CLKT7 SDATA FB_INT FB_OUTT CLKC8 CLKT8 CLKT9 CLKC9
PLL102-108
DESCRIPTIONS
PLL102-108 zero delay buffer that distributes single-ended clock input pairs differential clock outputs feedback clock output. Output signal duty cycles adjusted 50%, independent duty cycle CLK_INT. bypassed test purposes strapping ground.
BLOCK DIAGRAM
Programmable Skew Channel -600~+800ps ±200ps step -300~+400ps ±100ps step
Programmable Delay Channel CLK_INT (0~2.5ns) +170ps step
Control Logic
FB_OUTT CLKT0 CLKC0 CLKT1 CLKC1 CLKT5 CLKC5 CLKT2 CLKC2 CLKT3 CLKC3 CLKT4 CLKC4 CLKT7 CLKC7 CLKT8 CLKC8 CLKT9 CLKC9 CLKT6 CLKC6
FB_INT
-300~+400ps ±100ps step
-300~+400ps ±100ps step -300~+400ps ±100ps step
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
03/29/02 Page
PLL102-108
Programmable Zero Delay Clock Driver
DESCRIPTIONS
Name
AVDD AGND CLKT(0:9) CLKC(0:9) CLK_INT FB_OUTT FB_INT SDATA SCLK
Number
4,11,15,21,28,34, 38,45 1,7,8,18,24, 25,31,41,42,48 3,5,10,20,22,46, 44,39,29,27 2,6,9,19,23,47, 43,40,30,26 14,32,36
Type
2.5V power supply. Ground Analog power supply (2.5V). Analog ground.
Description
"True" clocks differential pair outputs. "Complementary" clocks differential pair outputs. Single-ended 3.3V tolerant input. connected. "True" feedback output. Dedicated external feedback. switches same frequency CLK_INT. "True" feedback input, provides feedback signal internal synchronization with CLK_INT eliminate phase error. Serial data input serial interface port.
Functionality
INPUTS AVDD 2.5V (Nom) 2.5V (Nom) CLK_INT CLK_INC CLKT OUTPUTS CLKC FB_OUTT State Bypass/Off Bypass/Off
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
03/29/02 Page
PLL102-108
Programmable Zero Delay Clock Driver
CONFIGURATION SETTING
Address Assignment Slave Receiver/Transmitter Data Transfer Rate
Provides both slave write readback functionality Standard mode 100kbits/s This serial protocol designed allow both blocks write read from controller. bytes must accessed sequential order from lowest highest byte. Each byte transferred must followed acknowledge bit. byte transferred without acknowledged will terminate transfer. write read block both begins with master sending slave address write condition (0xD4) read condition (0xD5). Following acknowledge this address byte, Write Mode: Command Byte Byte Count Byte must sent master ignored slave, Read Mode: Byte Count Byte will read master then other Data Byte. Byte Count Byte default power-up (0x09).
Data Protocol
CONTROL REGISTERS
BYTE Outputs Register (1=Enable, 0=Disable)
Pin#
39,40 43,44 46,47 22,23 19,20 9,10
Default
Description
CLKT7, CLKC7 active, 0=inactive) CLKT6, CLKC6 active, 0=inactive) CLKT5, CLKC5 active, 0=inactive) CLKT4, CLKC4 active, 0=inactive) CLKT3, CLKC3 active, 0=inactive) CLKT2, CLKC2 active, 0=inactive) CLKT1, CLKC1 active, 0=inactive) CLKT0, CLKC0 active, 0=inactive)
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
03/29/02 Page
PLL102-108
Programmable Zero Delay Clock Driver
TABLE Output Signals SKEW Programming Summary: Bit<2:0>
Skew Setting 100ps/step)
+400ps +300ps +200ps +100ps Default -100ps -200ps -300ps Setting applies following outputs: DDRA: CLK0, CLK1, CLK5 DDRB: CLK7, CLK8, CLK9 DDRC: CLK2, CLK3, CLK4 DDRD: CLK6
FBOUT Skew Setting 200ps/step)
+800ps +600ps +400ps +200ps Default -200ps -400ps -600ps Setting applies following outputs: FB_OUTT
BYTE SKEW Register (1=Enable, 0=Disable)
Skew DDRB Skew DDRA
Name
26,27 29,30
Default
Description
CLKT9, CLKC9 active, 0=inactive) CLKT8, CLKC8 active, 0=inactive) These three bits will adjust timing DDRA signals (CLK0, CLK1, CLK5) either positive negative delay +400ps -300ps with ±100ps step. (see Table These three bits will adjust timing DDRB signals (CLK7, CLK8, CLK9) either positive negative delay +400ps -300ps with ±100ps step. (see Table
BYTE SKEW Register (1=Enable, 0=Disable)
Skew DDRD
Name
DDR-SKEWEN FBOUT-SKEWEN Skew DDRC
Default
disable, enable disable, enable
Description
These three bits will adjust timing DDRC signals (CLK2, CLK3, CLK4) either positive negative delay +400ps -300ps with ±100ps step. (see Table These three bits will adjust timing DDRD signals (CLK6) either positive negative delay +400ps -300ps with ±100ps step. (see Table
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
03/29/02 Page
PLL102-108
Programmable Zero Delay Clock Driver
BYTE Outputs Register (1=Enable, 0=Disable)
Delay CLKINT Skew FBOUT
Name
Default
Reserved
Description
These three bits will adjust timing FBOUTT signal either positive negative delay +800ps -600ps with ±200ps step. (see Table
These four bits will program propagation delay from CLK_INT input within range between 2.5ns with 170ps step size. (see Table
TABLE CLK_INT Delay Programming Summary: Bit<3:0>
1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000
CLK_INT Delay
+2,550 +2,380 +2,210 +2,040 +1,870 +1,700 +1,530 +1,360 +1,190 +1,020 +850 +680 +510 +340 +170 Default
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
03/29/02 Page
PLL102-108
Programmable Zero Delay Clock Driver
TABLE Output Drive Strength Programming Summary: Bit<2:0>
Programming Setting
+40% +30% +20% +10% Default -10% -20% -30% Setting applies following outputs DDRA (CLK0, CLK1, CLK5) DDRB (CLK7, CLK8, CLK9) DDRC (CLK2, CLK3, CLK4) DDRD (CLK6) FBOUT
Byte Buffer Drive Strength Control Register
DDRB Strength DDRA Strength
Name
Default
Reserved. Reserved.
Description
These three bits will program drive strength CLK0, CLK1 CLK5 output clocks (see Table
These three bits will program drive strength CLK7, CLK8 CLK9 output clocks (see Table
Byte Buffer Drive Strength Control Register
DDRD Strength DDRC Strength
Name
Default
Reserved. Reserved.
Description
These three bits will program drive strength CLK2, CLK3 CLK4 output clocks (see Table
These three bits will program drive strength CLK6 output clock (see Table
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
03/29/02 Page
PLL102-108
Programmable Zero Delay Clock Driver
Byte Buffer Drive Strength Control Register
FBOUT Strength
Name
Default
Reserved. Reserved. Reserved. Reserved. Reserved.
Description
These three bits will program drive strength FBOUTT output clock (see Table
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
03/29/02 Page
PLL102-108
Programmable Zero Delay Clock Driver
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings PARAMETERS
Supply Voltage Range Input Voltage Range Output Voltage Range Storage Temperature Maximum power dissipation still
SYMBOL
MIN.
MAX.
UNITS
Exposure device under conditions beyond limits specified Maximum Ratings extended periods cause permanent damage device affect product reliability. These conditions represent stress rating only, functional operations device these other conditions above operational limits noted this specification implied.
Electrical Characteristics PARAMETERS
Operating supply current High Impedance output current Input clamp voltage Input Capacitance Output Capacitance High level output voltage level output voltage Output differential-pair crossing voltage
SYMBOL
DD2.5 DDPD
CONDITIONS
(Fclk=100Mhz) VDD=2.7V, =VDD -18mA Max, -1mA 2.3V, -12mA Max, 2.3V, 12mA
MIN.
TYP.
MAX.
-1.2
UNITS
VDD-0.1 (VDD/2)0.2 (VDD/ 2)+0.2
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
03/29/02 Page
PLL102-108
Programmable Zero Delay Clock Driver
Recommended Operating Conditions PARAMETERS
Output supply voltage Analog Supply voltage High level input voltage level input voltage Operating free-air temperature
SYMBOL
MIN.
TYP.
MAX.
UNITS
Timing requirements SYMBOL
PARAMETERS
Input clock frequency Input clock duty cycle Stabilization time after power
MIN.
MAX.
UNITS
Switching Characteristics PARAMETERS
high level propagation delay time High level propagation delay time Jitter (peak peak) Jitter (cycle cycle) Phase error Output output skew Pulse skew Duty Cycle Rise time, Fall time
SYMBOL
cyc-cyc (phase error) oskew pskew
CONDITIONS
CLK_INT output CLK_INT output 66MHz 100/133/200/266MHz 66MHz 100/133/200/266MHz differential input output terminals terminated with 120/16pF 66MHz 100MHz 101MHz 266MHz Load 120/16pF
MIN.
TYP.
MAX.
UNITS
-150 49.5 50.5
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
03/29/02 Page
PLL102-108
Programmable Zero Delay Clock Driver
PACKAGE INFORMATION
0.400 0.410 10.160 10.414
0.292 0.299 7.417 7.595
0.008 0.0135 0.203 0.343
0.025 0.635
0.015 (0.381) 0.010 0.016 (0.254 0.406) 0.620 0.630 (15.75 16.00)
0.088 0.096 (2.235 2.438)
0.097 0.104 (2.464 2.642) 30-60 0.050 (1.27) 0.008 0.016 (0.203 0.406)
48PIN SSOP
ORDERING INFORMATION
part ordering, please contact Sales Department:
47745 Fremont Blvd., Fremont, 94538, Tel: (510) 492-0990 Fax: (510) 492-0991
order number this device combination following: Device number, Package type Operating temperature range
PART NUMBER
PLL102-108
PART NUMBER TEMPERATURATURE C=COMMERCIAL M=MILITARY I=INDUSTRAL PACKAGE TYPE X=SSOP
PhaseLink Corporation, reserves right make changes products specifications, both time without notice. information furnished Phaselink believed accurate reliable. However, PhaseLink makes guarantee warranty concerning accuracy said information shall responsible loss damage whatever nature resulting from reliance upon this product. LIFE SUPPORT POLICY: PhaseLink's products authorized critical components life support devices systems without express written approval President PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
03/29/02 Page
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