Frequency Generator with 200MHz Differential Clocks Supports pair
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PLL207-151
Frequency Generator with 200MHz Differential Clocks
Supports pair differential clocks INTEL Brookdale chipsets. Programmable Spread Spectrum Modulation from ±0.1% ±1.5% with minimum step size ±0.012%. Selectable either center down. Selectable Spread Spectrum modulation profile. AccuSkew Programmable Precision skew tuning channel with maximum precision over variation temperature, process voltage. Finest step starts with 80ps. AccuDrive Programmable Output Buffer drive strength with minimum step. PCI, PCI_F, USB, DOT, REF, 3V66 3V66/VCH (3.3V) 66.66MHz 48MHz. Power management control stop CPU, PCI. Support 2-wire serial interface. Single byte micro-step linear Frequency programming with smooth switching. Available SSOP.
CONFIGURATION
VDD1 XOUT VSS1 PCI_F0 PCI_F1 PCI_F2 VDD2 VSS2 PCI0 PCI1 PCI2 PCI3 VDD2 VSS2 PCI4 PCI5 PCI6 VDD3 VSS3 3V66_2 3V66_3 3V66_4 3V66_5 PD#/^ VDD1 VSS1 Vtt_PWRGD# CPU_STOP#^ CPUT0 CPUC0 VDD5 CPUT1 CPUC1 VSS5 VDD5 CPUT2 CPUC2 MULTSEL0^ IREF VSS_IREF 48MHz_USB 48MHz_DOT VDD4 VSS4 3V66_0/VCH PCI_STOP#^ 3V66_1 VDD3 VSS3 SCLK SDATA
PLL207-151
BLOCK DIAGRAM
XOUT XTAL
Note: Pull (100k), Active low, Bi-directional latched power-up
CPUT0 PLL1 CPUC0
POWER GROUP
VDD1, VSS1: REF, XIN, XOUT, ANALOG VDD2, VSS2: VDD3, VSS3: 3V66 VDD4, VSS4: 48MHz VDD5, VSS5: CPUT CPUC
CPUT1 SDATA SCLK (0:2)* Logic CPUT2 CPUC1
Control Logic
MULTSEL0 CPU_STOP# PCI(0:6) PCI_STOP# 3V66 (1:5) IREF 3V66_0/VCH 48MHz_USB 48MHz_DOT PCI_F(0:2) CPUC2
SPECIFICATIONS
Output Jitter 200ps 3V66 Output Jitter 250ps Output Skew
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
11/27/02 Page
PLL207-151
Frequency Generator with 200MHz Differential Clocks
DESCRIPTIONS
Name
XOUT PCI_F(0:2) PCI(0:6) 3V66(1:5) Vtt_PWRGD# SDATA SCLK PCI_STOP# 3V66_0/VCH 48MHz_DOT 48MHz_USB MULTSEL0 CPUC(0:2) CPUT(0:2) CPU_STOP
Number
1,8,14,19,26, 32,37,46,50 5,6,7 10,11,12,13, 16,17,18 21,22,23,24, 44,48,51 45,49,52
Type
3.3V Power Supply.
Description
14.318Mhz crystal input connected crystal. 14.318Mhz crystal output. clock optionally affected PCI_STOP (see Byte PCI_F will left free running Byte [3:5] will stopped Byte [3:5] They have ohms on-chip series resistor. clock outputs. They have ohms on-chip series resistor. 66MHz reference clock from internal VCO. ohms on-chip series resistor. Power Down Control input. When low, Power Down will disable clock outputs including internal crystal clock. This 100k internal pull-up. This 3.3V LVTTL input level sensitive strobe used determine when (0:2) MULTSEL0 inputs valid ready sampled (active low). Serial data inputs serial interface port. Halts clocks when (except PCI_F which free running). This 100k internal pull-up. 3.3V output selectable through 66MHz from internal 48MHz (non-Speed Spectrum Controlled). ohms on-chip series resistor. 48MHz output DOT. ohms on-chip series resistor. 48MHz output USB. ohms on-chip series resistor. Frequency select pins. This establishes reference current pairs, requires fixed precision resistor tied ground order establish appropriate current. This input selecting current multiplier outputs. This 100k internal pull-up. Complementary clock differential pair outputs. True clock differential pair outputs. Halts clocks when input low. This 100k internal pull-up.
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
11/27/02 Page
PLL207-151
Frequency Generator with 200MHz Differential Clocks
DESCRIPTIONS (CONTINUED)
Name
FS(0:1) VSS_I
Number
54,55 4,9,15,20,27, 31,36,47
Type
Frequency select pins.
Description
14.318MHz reference clock. ohms on-chip series resistor. Current reference programming input buffers. This returned device VSS. 0.0V Power Supply.
FEQUENCY (MHz) SELECTION TABLE
66.66 133.3 66.66 133.3 Tristate TCLK/2 Reserved Reserved
3V66
66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 Tristate TCLK/4 Reserved Reserved
PCI_F,
33.3 33.3 33.3 33.3 33.3 33.3 33.3 33.3 Tristate TCLK/8 Reserved Reserved
Spread Spectrum modulation rate
-0.5% down spread -0.5% down spread -0.5% down spread -0.5% down spread -0.75% down spread -0.75% down spread -0.75% down spread -0.75% down spread
POWER MANAGEMENT CONIGURATION
CPU_STOP#
PCI_STOP#
CPUT
IREF*2 IREF*2 IREF*2
CPUC
FLOAT FLOAT FLOAT
3V66
PCI_F
USB/DOT
PLL/OSC
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
11/27/02 Page
PLL207-151
Frequency Generator with 200MHz Differential Clocks
HOST SWING SELECT FUNCTIONS
MULT_SEL0
Board target trace
Reference (Rr); IREF VDD/(3*Rr)
(1%); IREF 5.00mA (1%); IREF 2.32mA
Output Current
IREF IREF
1.0V 0.7V
MAXIMUM ALLOWED CURRENT
Conditions Powerdown Mode (PD# Full Active
Max. supply consumption 3.465V static inputs 25mA Iref 2.32 45mA Iref 5.0mA
TIMING DIAGRAMS PHASE RELATIONSHIP
Figure: 3V66 Phase Relationship Un-Buffered Mode
3V66(0:1)
3V66(2:4)
3V66_5 Tpci PCI_F(0:2) PCI(0:6)
Group Skews Common Transition Edges: Group
3V66 3V66
Un-Buffered Mode)
Symbols
3V66
Description
3V66(0:5) pin-to-pin skew PCI_F(0:2) (0:6) pin-to-pin skew 3V66(0:5) leads 33MHz
Units
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
11/27/02 Page
PLL207-151
Frequency Generator with 200MHz Differential Clocks
CONFIGURATION SETTING
Address Assignment Slave Receiver/Transmitter Data Transfer Rate
Provides both slave write read back functionality Standard mode 100kbits/s This serial interface designed allow multiple protocols write read from controller. includes Block Read/Write, Block Index Read/Write, Byte Read/Write Word Read/Write. general, bytes must accessed sequential order from lowest highest byte. Each byte transferred must followed acknowledge bit. byte transferred without acknowledged will terminate transfer. write read block both begins with master sending slave address write condition (0xD2) read condition (0xD3).
Data Protocol
WRITE MODE
Block Write Address Command Byte count Data Byte Data Byte Data Data Byte
Block Index Write
Address
Command =(00~22)
Byte count
Data Byte
Data Byte
Data
Data Byte M+N-1
Byte Write
Address
Command =(00~22)+128
Data Byte
Word Write
Address
Command =(00~22)+128
Data Byte
Data Byte
READ MODE
Block Read Address Command Address Byte count Data Byte Data Byte Data Data Byte
Block Index Read
Address
Command =(00~22)
Address
Byte count
Data Byte
Data Byte
Data
Data Byte M+N-1
Byte Read
Address
Command =(00~22)+128
Address
Data Byte
Word Read
Address
Command =(00~22)+128
Address
Data Byte
Data Byte
Legend:
Start
Acknowledge Stop host
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
11/27/02 Page
PLL207-151
Frequency Generator with 200MHz Differential Clocks
BYTE Functional Frequency Select Clock Register (1=Enable, 0=Disable)
Pin#
Default
Description
OFF, Spread Spectrum Enable mode: 0=CPU drive when 1=non drive Select 66Mhz/48Mhz. 0=66Mhz, 1=48Mhz Reflects value CPU_STOP#. Reflects value PCI_STOP#. Power-up latched value (Read only) Power-up latched value (Read only) Power-up latched value (Read only)
BYTE Control Register (1=Enable, 0=Disable)
Pin#
45,44 49,48 52,51
Default
Description
Reflects current MULTSEL0 value (Read only) mode: 0=CPU drive when STP, 1=non drive, CPU=STPD Allow control CPUCLKT2/C2 with assertion CPU_STOP# 0=not free running, 1=free running Allow control CPUCLKT1/C1 with assertion CPU_STOP# 0=not free running, 1=free running Allow control CPUCLKT0/C0 with assertion CPU_STOP# 0=not free running, 1=free running Enables/disables CPUT2, CPUC2. When disabled, defaults CPUT2 CPUC2 Enables/disables CPUT1, CPUC1. When disabled, defaults CPUT1 CPUC1 Enables/disables CPUT0, CPUC0. When disabled, defaults CPUT0 CPUC0
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
11/27/02 Page
PLL207-151
Frequency Generator with 200MHz Differential Clocks
BYTE Control Register (1=Enable, 0=Disable)
Pin#
Default
Description
Reserved PCI6 (1=Active 0=Inactive) PCI5 (1=Active 0=Inactive) PCI4 (1=Active 0=Inactive) PCI3 (1=Active 0=Inactive) PCI2 (1=Active 0=Inactive) PCI1 (1=Active 0=Inactive) PCI0 (1=Active 0=Inactive)
BYTE Control Register (1=Enable, 0=Disable)
Pin#
Default
Description
48MHz_DOT (1=Active 0=Inactive) 48MHz_USB (1=Active 0=Inactive) Allows control PCI_F2 output after assertion PCI_STOP#. Free running, free running. Allows control PCI_F1 output after assertion PCI_STOP#. Free running, free running. Allows control PCI_F0 output after assertion PCI_STOP#. Free running, free running. PCI_F2 (1=Active 0=Inactive) PCI_F1 (1=Active 0=Inactive) PCI_F0 (1=Active 0=Inactive)
BYTE Control Register (1=Enable, 0=Disable)
Pin#
Profile Accu-SST
Default
Description
linear, non-linear Accu-SST programming Enable: Byte setting 3V66_1 (1=Active 0=Inactive) 3V66_0/VCH (1=Active 0=Inactive) 3V66_5 (1=Active 0=Inactive) 3V66_4 (1=Active 0=Inactive) 3V66_3 (1=Active 0=Inactive) 3V66_2 (1=Active 0=Inactive)
11/27/02 Page
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
PLL207-151
Frequency Generator with 200MHz Differential Clocks
BYTE Linear Programming Register (1=Enable, 0=Disable)
Pin#
Default
Description
Linear programming sign "+", Linear programming magnitude (MSB) Linear programming magnitude Linear programming magnitude Linear programming magnitude Linear programming magnitude Linear programming magnitude Linear programming magnitude (LSB)
BYTE Vendor Revision Register
Pin#
Default
Description
Revision (read only) Revision (read only) Revision (read only) Revision (read only) Vendor (read only) Vendor (read only) Vendor (read only) Vendor (read only)
BYTE Accu-Spread Spectrum Modulation Amplitude Programming Register:
NAME
SST6 SST5 SST4 SST3 SST2 SST1 SST0
Default
Description
Spread Spectrum mode selection. 1=Center Spread, Down Spread
Center Spread: SST<6:0> Modulation rate Down Spread: SST<6:0> Modulation rate
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
11/27/02 Page
PLL207-151
Frequency Generator with 200MHz Differential Clocks
BYTE SKEW Control Register (1=Enable, 0=Disable)
SKEW CPU0
Name
SKEW ENABLE
Default
Description
Enable Accu-Skew programming. 1=enable, 0=disable Skew calibration: 1=enable, 0=disable [5:3] +320ps +240ps +160ps +80ps These three bits will adjust timing CPU0 signals (CPUT0/CPUC0) either positive negative delay +320ps -240ps with ±80ps step accuracy.
Default
-80ps -160ps -240ps [2:0] +320ps +240ps +160ps +80ps Default -80ps -160ps -240ps
SKEW CPU1
These three bits will adjust timing CPU1 signals (CPUT1/CPUC1) either positive negative delay +320ps -240ps with ±80ps step accuracy.
BYTE SKEW Control Register (1=Enable, 0=Disable)
SKEW CPU2
Name
Default
Reserved Reserved [5:3] +320ps +240ps +160ps +80ps Default -80ps -160ps -240ps [2:0] +640ps +480ps +320ps +160ps Default -160ps -320ps -480ps
Description
These three bits will adjust timing CPU2 signals (CPUT2/CPUC2) either positive negative delay +320ps -240ps with ±80ps step accuracy.
SKEW 3V66
These three bits will adjust timing 3V66 signals (3V66[0:5]) either positive negative delay +640ps -480ps with ±160ps step accuracy.
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
11/27/02 Page
PLL207-151
Frequency Generator with 200MHz Differential Clocks
BYTE Control Register (1=Enable, 0=Disable)
PCI_F Strength SKEW
Name
Default
Reserved Reserved [5:3] +640ps +480ps +320ps +160ps Default -160ps -320ps -480ps [2:0] +50% +38% +25% +13% Default -13% -25% -38%
Description
These three bits will adjust timing signals (PCI_F[0:2], PCI[0:6]) either positive negative delay +640ps -480ps with ±160ps step accuracy.
These three bits will program drive strength PCI_F[0:2] output clocks either increase decrease from -38% +50%.
BYTE Buffer Strength Control Register (1=Enable, 0=Disable)
Strength
Name
Default
Reserved Reserved [2:0] +50% +38% +25% +13% Default -13% -25% -38% [2:0] +40% +30% +20% +10% Default -10% -20% -30%
Description
These three bits will program drive strength PCI[0:6] output clocks either increase decrease from -38% +50%.
3V66 Strength
These three bits will program drive strength 3V66[0:5] output clocks either increase decrease from -30% +40%.
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
11/27/02 Page
PLL207-151
Frequency Generator with 200MHz Differential Clocks
BYTE Buffer Strength Control Register (1=Enable, 0=Disable)
Strength Strength
Name
Default
Reserved Reserved [2:0] +40% +30% +20% +10% Default -10% -20% -30% [2:0] +50% +38% +25% +13% Default -13% -25% -38%
Description
These three bits will program drive strength 48MHz_USB, 48MHz_DOT output clocks either increase decrease from -30% +40%.
These three bits will program drive strength output clocks either increase decrease from -38% +50%.
ASSERTION (Transition from Logic Logic "0")
When Power-Down (PD#) sampled consecutive rising edges CPUT clock, then clock outputs must held their next high transition (except CPUC which must driven high with value IREF). After clocks have been stopped, internal stages Crystal oscillator will driven power stopped condition.
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
11/27/02 Page
PLL207-151
Frequency Generator with 200MHz Differential Clocks
Figure: assertion (Transition from Logic Logic '0')
PCIF
PWRDWN#
CPUC
CPUT
3V66
14.318MHz
48MHz
DE-ASSERTION (Transition from Topic Topic "1")
Power-Down (PD#) taken from High transition return normal running operation. Crystal Oscillator stages released from start-up normal operation. clocks (differential outputs driven 3V66_(0:5) clocks then operating. After clocks released. Following (DOT clocks) 14.318MHz) clocks released. Figure: de-assertion (Transition from Logic Logic '1')
min. 100us max.
PCIF
PWRDWN#
CPUC
CPUT
3V66
48MHz
14.318MHz
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
11/27/02 Page
PLL207-151
Frequency Generator with 200MHz Differential Clocks
Figure: Assertion CPU_Stop# Waveforms
CPU_Stop#
CPUC
CPUT
Figure: Assertion PCI_Stop# Waveforms
PCI_Stop#
PCIF(0:2) 33MHz PCI(0:6) 33MHz
Note: PCIF left free-running selected I2C.
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
11/27/02 Page
PLL207-151
Frequency Generator with 200MHz Differential Clocks
PROGRAMMING FREQUENCY USING SMART-BYTE: simplify traditional loop counter setting, PLL207-151 device incorporates SMART-BYTE technology with single byte programming I2C. Detail PLL207-151's dual mode frequency programming method described below: ROM-table Frequency Programming: pre-defined frequencies found Frequency table accessed through external jumpers. Micro-step Linear Frequency Programming: Frequency programmed fine linear positive negative stepping around selected frequency Frequency table. highest step either +127 -127. Other frequencies will changed proportionally with rate that frequency changes. formula follow:
CPU.ROM-Table
Where: magnitude factor defined Byte 5.bit (0:6) (sign bit) defined Byte5.bit constant equal 0.9/(CPUDivider) ranging from 0.11~0.45.
FREQUENCY PROGRAMMING EXAMPLE: Procedures program target frequency Mhz:
Locate closest frequency from Frequency-ROM table: 0.22 Solve (Linear Magnitude factor) integer: ROMTABLE (110 108) 0.22 Program register:
Setting I2C.BYTE57
Sign
(0.22) 1.83
109.98 frequency increased Table 1.83 36.66
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
11/27/02 Page
PLL207-151
Frequency Generator with 200MHz Differential Clocks
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings PARAMETERS
Supply Voltage Input Voltage, Output Voltage, Storage Temperature Ambient Operating Temperature Junction Temperature Voltage
SYMBOL
MIN.
MAX.
UNITS
Exposure device under conditions beyond limits specified Maximum Ratings extended periods cause permanent damage device affect product reliability. These conditions represent stress rating only, functional operations device these other conditions above operational limits noted this specification implied.
Electrical Specifications PARAMETERS
Input High Voltage Input Voltage Input Leakage Current Output High Voltage Output Voltage Input Capacitance Output Capacitance
SYMBOL
CONDITIONS
MIN.
-0.3
TYP.
MAX.
+0.3
UNITS
Electrical Specifications PARAMETERS
Rise Time
SYMBOL
OUTPUTS
3V66, 66MHz,
CONDITION
@1.0V Measured 0.4V 2.4V, =20pf, 3.3V±5% @1.0V Measured 0.4V 2.4V, =20pf, 3.3V±5%
MIN.
TYP.
MAX.
UNITS
Fall Time
3V66, 66MHz,
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
11/27/02 Page
PLL207-151
Frequency Generator with 200MHz Differential Clocks
Electrical Specifications (Continued) PARAMETERS SYMBOL OUTPUTS
Cycle Cycle jitter cyc-cyc 3V66, 66MHz 48MHz, DOT, Skew skew 3V66 3V66 PCI_F Duty Cycle CPU, PCI, REF, 48MHz, 3V66 48MHz_USB, DOT, 3V66, 66MHz, Falling edge Rate 48MHz_USB, DOT, 3V66, 66MHz, 48MHz_USB Long Term jitter L-jitter 48MHz_DOT Output enable delay Output disable delay Stabilization time Tpzl,Tpzh Tplz,Tpzh outputs outputs outputs
CONDITION
@1.5V @1.5V @1.5V @1.5V Un-buffered mode @1.5V Measured 0.4V 2.4V Measured 0.4V 2.4V Measured 0.4V 2.4V Measured 0.4V 2.4V 125us period jitter (8kHz modulation Amplitude) 10us period jitter (100kHz modulation Amplitude)
MIN.
TYP.
MAX.
UNITS
Rising edge Rate
V/ns
10.0 10.0
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
11/27/02 Page
PLL207-151
Frequency Generator with 200MHz Differential Clocks
PACKAGE INFORMATION
Package Pins#
SSOP (QSOP) 300mil
inches 2.79 0.406 0.343 0.254 18.54 7.60 10.67 0.095 0.008 0.008 0.005 0.720 0.291 0.395 0.110 0.016 0.0135 0.010 0.730 0.299 0.420
Unit
2.41 0.203 0.203 0.127 18.29 7.39 10.03
0.635BSC 0.508 1.016
0.025BSC 0.020 0.040
56PIN SSOP
ORDERING INFORMATION
PhaseLink Corporation, reserves right make changes products specifications, both time without notice. information furnished PhaseLink believed accurate reliable. However, PhaseLink makes guarantee warranty concerning accuracy said information shall responsible loss damage whatever nature resulting from reliance upon this product.
LIFE SUPPORT POLICY: PhaseLink's products authorized critical components life support devices systems
part ordering, please contact Sales Department:
47745 Fremont Blvd., Fremont, 94538, Tel: (510) 492-0990 Fax: (510) 492-0991
order number this device combination following: Device number, Package type Operating temperature range
PART NUMBER
PLL207-151
PART NUMBER TEMPERATURATURE C=COMMERCIAL M=MILITARY I=INDUSTRAL PACKAGE TYPE X=SSOP
without express written approval President PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
11/27/02 Page
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