Motherboard Clock Generator Generates clock frequencies chip sets

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Motherboard Clock Generator Generates clock frequencies chip sets

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PLL205-03
Motherboard Clock Generator
Generates clock frequencies chip sets requiring multiple clocks high speed SDRAM buffers. Support pair differential clocks, 3.3V push-pull clock, highspeed SDRAM buffers 3-DIMM applications. 24_48MHz clock 48MHz clock. Two14.318MHz reference clocks. Power management control stop CPU, Power down Mode from programming. Support 2-wire serial interface with builtin Vendor Device Revision Single byte micro-step linear Frequency Programming with Glitch free smooth switching. Enhanced SDRAM output Drive selectable I2C. Spread Spectrum ±0.25% center spread, -0.5% downspread. duty cycle with jitter. Available SSOP.
CONFIGURATION
VDD0 REF0//CPU_STOP#^ XOUT VDD1 PCI5/MODE*^ PCI0/FS3*^ PCI1/SEL24_48*^ PCI2 PCI3 PCI4 VDD2 SDRAMIN SDRAM11 SDRAM10 VDD3 SDRAM9 SDRAM8 SDATA SCLK
REF1/FS2*^ CPUT1 CPUC0 CPUT0 VDD3 PD#^ SDRAM12 SDRAM0 SDRAM1 VDD3 SDRAM2 SDRAM3 SDRAM4 SDRAM5 VDD3 SDRAM6 SDRAM7 VDD4 48MHz/FS0*^ 24_48MHz/FS1*^
Note: Pull Active Bi-directional latched power-up
MODE CONFIGURATION BLOCK DIAGRAM
VDD1 XOUT XTAL REF(0:1)
PLL205-03
MODE (Pin (OUTPUT) (INPUT)
REF0 CPU_STOP
CPUT1 SDATA SCLK (0:3)* Control Logic PLL1 CPUC0 Logic CPUT0
POWER GROUP
VDD0: CORE VDD1: REF(0:1), XIN, XOUT VDD2: PCI(0:5) VDD3: SDRAM(0:12) VDD4: 48MHz, 24_48MHz
VDD2 PCI(0:4)
PCI5 VDD4 48Mhz PLL2
SPECIFICATIONS
Cycle Cycle jitter: 250ps. output skew: 500ps. output skew: ±175ps SDRAM SDRAM output skew: 250ps. skew (CPU leads):
24_48Mhz VDD3 SDRAM(0:11)
SDRAMIN SDRAM12
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
06/23/00 Page
PLL205-03
Motherboard Clock Generator
DESCRIPTIONS
Name
VDD0 VDD1 VDD2 VDD3 VDD4 XOUT REF0//CPU_STOP
Number
19,30,36,42 3,9,16,22, 33,39,45,47
Type
Power supply CORE.
Description
Power supply REF0, REF1, crystal oscillator. Power supply (0:5). Power supply SDRAM (0:12). Power supply 24_48MHz 48MHz. Ground. 14.318MHz crystal input that internal loads (36pF) feedback resistor from XOUT. 14.318MHz crystal output. internal load (36pF). Multiplexed controlled MODE signal. When CPU_STOP low, will halt CPUT (0:1), CPUC0 SDRAM (0:11) outputs. output mode, this will generate buffered reference clock output. power-up, MODE function will activated. When MODE Low, input CPU_STOP. When high, output REF0. After input data latched, this will generate clock. power-up, this input will determine clock frequency. After input sampling, this will generate output clocks. internal pull (high default). power-up, this will select 24MHz (when high) 48MHz (when low) pin25 output. After input sampling, this output. internal pull resistor. clock outputs. Buffer input pin: signal provided this input buffered SDRAM outputs. SDRAM clock outputs, Fan-out Buffer outputs from SDRAMIN pin. Serial data inputs serial interface port. power-up, these pins input pins will determine clock frequency. FS0, have internal pull (high default). When CPU_STOP low, this still free running. When power down low, this SDRAM will stopped. When low, will stop clock outputs. internal pull-up resistor. "True" clock differential pair open-drain output. "Complementary" clocks differential pair open-drain outputs. "True" clock push-pull output. Buffered reference clock output after input data latched during power-up.
PCI5/MODE
PCI0/FS3
PCI1/SEL24_48 PCI(2:4) SDRAMIN SDRAM(0:11) SDATA SCLK 24_48MHz/FS1, 24MHz/FS0 SDRAM12 CPUT0 CPUC0 CPUT1 REF1/FS2
11,12,13 17,18,20,21,28, 29,31,32,34,35, 37,38 25,26
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
06/23/00 Page
PLL205-03
Motherboard Clock Generator
FREQUENCY (MHz) SELECTION TABLE
Byte0 Bit2
124.0 75.0 83.3 66.8 103.0 112.0 133.3 100.0 120.0 115.0 110.0 105.0 140.0 150.0 124.0 133.3 90.0 92.5 95.0 97.5 101.5 127.0 136.5 100.0 120.0 117.5 122.0 107.5 145.0 155.0 130.0 133.3
41.3 37.5 41.7 33.4 34.3 37.3 44.4 33.3 40.0 38.3 36.7 35.0 35.0 37.5 31.0 33.3 30.0 30.8 31.7 32.5 33.8 42.3 34.1 33.3 40.0 39.2 40.7 35.8 36.3 38.7 32.5 33.3
Spread Spectrum Modulation
±0.25% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% -0.5% -0.5% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% -0.5%
default
POWER MANAGEMENT
CPU_STOP CPUC0 Stopped Running CPUT (0:1) Stopped Running SDRAM (0:11) Stopped Running SDRAM12 Running Running CRYSTAL Running Running Running Running
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47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
PLL205-03
Motherboard Clock Generator
POWER MANAGEMENT (Continued)
CPUC0 Stopped Running CPUT (0:1) Stopped Running SDRAM (0:11) Stopped Running SDRAM12 Stopped Running CRYSTAL Stopped Running Stopped Running
CONFIGURATION SETTING
Address Assignment Slave Receiver/Transmitter Data Transfer Rate
Provides both slave write readback functionality Standard mode 100kbits/s serial bits will read sent clock driver following order Byte Bits Byte Bits Byte Bits This serial protocol designed allow both blocks write read from controller. bytes must accessed sequential order from lowest highest byte. Each byte transferred must followed acknowledge bit. byte transferred without acknowledged will terminate transfer. write read block both begins with master sending slave address write condition (0xD2) read condition (0xD3). Following acknowledge this address byte, Write Mode: Command Byte Byte Count Byte must sent master ignored slave, Read Mode: Byte Count Byte will read master then other Data Byte. Byte Count Byte default power-up (0x09).
Serial Bits Reading
Data Protocol
CONTROL REGISTERS
BYTE Functional Frequency Select Clock Register (1=Enable, 0=Disable)
Pin#
Default
Description
Frequency selection Table Frequency selection Table Frequency selection Table Frequency selection Table Frequency selection control 1=Via I2C, 0=Via External jumper Frequency selection Table 0=Normal 1=Spread Spectrum enable 0=Normal 1=Tristate Mode outputs
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47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
PLL205-03
Motherboard Clock Generator
BYTE Clock Register (1=Enable, 0=Disable)
Pin#
17,18,20,21, 28,29,31,32, 34,35,37,38 43,44 43,44
Default
Description
Reserved High Strength SDRAM Select 1=Normal, Enhanced Enhanced CPUT1 Drive Select 1=Normal, 0=Enhanced Enhanced CPUT0, CPUC0 Drive Select (1=Normal, 0=Enhanced 25%) SDRAM12 Active/Inactive Reserved CPUT0, CPUC0 Active/Inactive CPUT1 Active/Inactive
BYTE Clock Register (1=Enable, 0=Disable)
Pin#
Default
Description
Reserved PCI5 Active/Inactive Reserved PCI4 Active/Inactive PCI3 Active/Inactive PCI2 Active/Inactive PCI1 Active/Inactive PCI0 Active/Inactive
BYTE SDRAM Clock Register (1=Enable, 0=Disable) Pin# Default Description
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
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PLL205-03
Motherboard Clock Generator
Reserved Reserved 48MHz Active/Inactive 24_48MHz Active/Inactive SDRAM11 Active/Inactive SDRAM10 Active/Inactive SDRAM9 Active/Inactive SDRAM8 Active/Inactive
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
06/23/00 Page
PLL205-03
Motherboard Clock Generator
BYTE SDRAM Clock Register (1=Enable, 0=Disable)
Pin#
Default
Description
SDRAM7 Active/Inactive SDRAM6 Active/Inactive SDRAM5 Active/Inactive SDRAM4 Active/Inactive SDRAM3 Active/Inactive SDRAM2 Active/Inactive SDRAM1 Active/Inactive SDRAM0 Active/Inactive
BYTE Peripheral Clock Register (1=Enable, 0=Disable)
Pin#
Default
Description
Inverted Power-up latched value (Read only) Inverted Power-up latched value (Read only) Inverted Power-up latched value (Read only) Inverted Power-up latched value (Read only) Reserved Inverted Power-up latched SEL24_48MHz value (Read only) REF1 Active/Inactive REF0 Active/Inactive
BYTE Revision Vendor Register (1=Enable, 0=Disable)
Pin#
Default
Description
Revision Revision Revision Revision Vendor Vendor Vendor Vendor
Note: Default value power-up
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
06/23/00 Page
PLL205-03
Motherboard Clock Generator
BYTE Linear Programming Register (1=Enable, 0=Disable)
Pin#
Default
Description
Linear programming sign "+", Linear programming magnitude (MSB) Linear programming magnitude Linear programming magnitude Linear programming magnitude Linear programming magnitude Linear programming magnitude Linear programming magnitude (LSB)
BYTE Device Register (1=Enable, 0=Disable)
Pin#
Default
Reserved Device Device Device Device Device Device Device
Description
Note: Default value power-up
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
06/23/00 Page
PLL205-03
Motherboard Clock Generator
PROGRAMMING FREQUENCY simplify traditional loop counter setting, PLL205-03 device incorporates SMART-BYTE technology with single byte programming better optimize clock jitter spread spectrum performance. Detail PLL205-03's dual mode frequency programming method described below: ROM-table Frequency Programming: pre-defined frequencies found Frequency table accessed either through external jumpers setting internal register BYTE0. Micro-step Linear Frequency Programming: Frequency programmed fine linear positive negative stepping around selected frequency Frequency table. highest step either +127 -127. Other frequencies will changed proportionally with rate that frequency change. formula follow:
CPU.ROM-Table (=0.22)
Where: magnitude factor defined Byte 7.bit(0:6) (sign bit) defined Byte7.bit constant 0.22
FREQUENCY PROGRAMMING EXAMPLE: Procedures program target frequency 139.0 Mhz:
Locate closest frequency from Frequency-ROM table: 136.5 0.22 Solve (Linear Magnitude factor) integer: ROMTABLE (139 136.5) 0.22 Program register:
Setting I2C.BYTE0 Setting I2C.BYTE7
Sign
136.5 (0.22) 138.92 frequency increased 34.1 (1+1.8%) 34.7
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
06/23/00 Page
PLL205-03
Motherboard Clock Generator
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings PARAMETERS
Supply Voltage Input Voltage, Output Voltage, Storage Temperature Ambient Operating Temperature Junction Temperature Voltage
SYMBOL
MIN.
MAX.
UNITS
Exposure device under conditions beyond limits specified Maximum Ratings extended periods cause permanent damage device affect product reliability. These conditions represent stress rating only, functional operations device these other conditions above operational limits noted this specification implied.
AC/DC Electrical Specifications PARAMETERS
Input High Voltage Input Voltage Input High Current Input Current
SYMBOL
CONDITIONS
MIN.
-0.3
TYP.
MAX.
+0.3
UNITS
Logic inputs without internal pull-up SCLK, Logic inputs with internal pull-up resistors, 2,7,8,10,25,26,48 66MHz 100MHz 133MHz 3.3V Logic Inputs XOUT pins 14.318
Input Current Power Down Pull-up resistor Operating Supply Current Input frequency Input Capacitance
-200
kohm
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
06/23/00 Page
PLL205-03
Motherboard Clock Generator
Output Buffer Electrical Specifications
Unless otherwise stated, power supplies 3.3V±5%, ambient temperature range 70°C
PARAMETERS
SYMBOL
OUTPUTS
CPUT1 (Open Drain)
CONDITIONS
Measured 0.3V 1.2V, =20pf, 3.3V±5% Measured 0.3V 1.2V, =20pf, 3.3V±5% Measured 0.4V 2.4V, =20pf, 3.3V±5% Measured 0.4V 2.4V, =30pf, 3.3V±5% Measured 0.4V 2.4V, =20pf, 3.3V±5% Measured 0.3V =20pf, 3.3V±5% Measured 1.2V =20pf, 3.3V±5% Measured 2.4V =20pf, 3.3V±5% Measured 2.4V =30pf, 3.3V±5% Measured 2.4V =20pf, 3.3V±5% 1.5V 1.2V, 0.3V, 0.4V, 0.4V, 0.4V,
MIN.
TYP.
MAX.
UNITS
Output Rise time
REF(0:1) PCI(0:5) 24_48MHz, 48MHz CPUT1 (Open Drain)
Output Fall time
REF(0:1) PCI(0:5) 24_48MHz, 48MHz REF(0:1),CPU, PCI(0:5) 24_48MHz, 48MHz CPUT1 CPUT0
Duty Cycle
Clock Skew
SKEW
CPUT1 PCI(0:5) REF(0:1) REF1 24_48MHz, 48MHz
-500
Output Impedance
=3.3V±5%
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
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PLL205-03
Motherboard Clock Generator
Output Buffer Electrical Specifications, continued
Unless otherwise stated, power supplies 3.3V±5%, ambient temperature range 70°C
PARAMETERS
SYMBOL
OUTPUTS
CPUT1 REF(0:1)
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Output High Current
PCI(0:5) 24_48MHz 48MHz SDRAM CPUT1 REF(0:1)
2.0V
0.4V
Output Current
PCI(0:5) 24_48MHz 48MHz SDRAM 0.8V
Jitter, Sigma Jitter, Absolute
sigma
REF,48MHz,24MHz REF,48MHz,24MHz
1.5V 1.5V Measured 1.5V -250
pullup +0.6 pullup +0.6 1100
Jitter (cycle cycle) Differential Voltage Differential Voltage Differential Crossover Voltage
cyc-cyc
(Open Drain)
Note: pullup 1.5V (external); specifies minimum input differential voltages required switching, where "true" input level "complement" input level.
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
06/23/00 Page
PLL205-03
Motherboard Clock Generator
PACKAGE INFORMATION
0.400 0.410 10.160 10.414
0.292 0.299 7.417 7.595
0.008 0.0135 0.203 0.343
0.025 0.635
0.015 (0.381) 0.010 0.016 (0.254 0.406) 0.620 0.630 (15.75 16.00)
0.088 0.096 (2.235 2.438)
0.097 0.104 (2.464 2.642) 30-60 0.050 (1.27) 0.008 0.016 (0.203 0.406)
48PIN SSOP
ORDERING INFORMATION
part ordering, please contact Sales Department:
47745 Fremont Blvd., Fremont, 94538, Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
order number this device combination following: Device number, Package type Operating temperature range
PLL205-03
PART NUMBER TEMPERATURATURE C=COMMERCIAL M=MILITARY I=INDUSTRAL PACKAGE TYPE X=SSOP
PhaseLink Corporation, reserves right make changes products specifications, both time without notice. information furnished PhaseLink believed accurate reliable. However, PhaseLink makes guarantee warranty concerning accuracy said information shall responsible loss damage whatever nature resulting from reliance upon this product. LIFE SUPPORT POLICY: PhaseLink's products authorized critical components life support devices systems without express written approval President PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
06/23/00 Page

Motherboard Clock Generator Generates clock frequencies chip sets

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