Programmable Clock Generator with 133MHz Generates clock frequenc
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PLL203-61
Programmable Clock Generator with 133MHz
Generates clock frequencies INTEL Chip sets. Supports clocks, high-speed SDRAM clocks 3-DIMM applications clocks. Three 3V66MHz clocks 2.5v APIC clock. 24MHz clock 48MHz clock. double strength 14.318MHz reference clock. Support 2-wire serial with built-in Vendor Device Revision Single byte micro-step linear Frequency programming with glitch free smooth switching. Built-in programmable watchdog timer seconds with 1-second interval. will generate reset output when timer expired. Spread Spectrum 0.25% center spread. duty cycle with jitter. Available SSOP.
CONFIGURATION
VDD1 XOUT 3V66_0 3V66_1 3V66_2 VDD2 VDD3 PCI0x2/FS0 PCI1x2/FS1 PCI2/SIO PCI3 PCI4 PCI5 VDD3 PCI6 PCI7 PD#/WDRESET# SCLK SDATA VDD5 SDRAM11 SDRAM10 REFx2/FS4 VDDL1 APIC VDDL2 CPU0 CPU1 SDRAM0 SDRAM1 SDRAM2 VDD5 SDRAM3 SDRAM4 SDRAM5 SDRAM6 SDRAM7 SDRAM_F VDD5 24_48MHzx2/FS2 48Mhzx2/FS3 VDD4 VDD5 SDRAM8 SDRAM9
PLL203-61
BLOCK DIAGRAM
Note: Pull Active low, Bi-directional latched power-up
VDD1 XOUT XTAL REFx2
POWER GROUP
VDD1: REF, XIN, XOUT, CORE VDD2: 3V66(0:2) VDD3: PCI(0:7) VDD4: 48MHz 24_48MHz VDD5: SDRAM(0:11)& SDRAM_F VDDL1: APIC VDDL2: CPU(0:1)
VDDL2 (0:4)* (0:1) VDDL1 PLL1 Control Logic SDATA SCLK Logic APIC VDD2 3V66 (0:2) VDD3 (0:7) VDD5 SDRAM (0:11) WATCH SDRAM_F WDRESET#
SPECIFICATIONS
Cycle Cycle jitter: 250ps: CPU, SDRAM 500ps: APIC, 48Mhz, 3V66, Skew: 250ps: CPU, 3V66 500ps: SDRAM, APIC, PCI, 48Mhz Clock Offset (@CPU=100Mhz): 4.5~5.5ns: CPU-SDRAM, CPU-3V66 1.5~3.5ns: 3V66-PCI -0.5~0.5ns: SDRAM-3V66, PCI-APIC
03/13/00 Page
VDD4 48Mhz PLL2
24_48Mhz
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
PLL203-61
Programmable Clock Generator with 133MHz
DESCRIPTIONS
Name
REFX2/FS4 XOUT 3V66(0:2) SDRAM(0:11), SDRAM_F PCI0X2/FS0, PCI1X2/FS1 PCI(3:7) PCI2/SIO
Number
6,7,8 48,47,46,44, 43,42,40,39, 31,30,27,26,38 11,12 15,16, 17,19,20
Type
Description
Reference 14.318Mhz Clock with Drive strength. This latches value power-up. (See Frequency Selection table page 14.318 crystal input connected crystal. 14.318 crystal output. 66MHz clock output. (See Frequency Selection table page3). 3.3V SDRAM Clocks with frequencies defined Frequency Selection table. SDRAM_F free running clock output. clock output with drive strength. These pins latch FS(0:1) value power-up. (See Frequency Selection table page These pins have internal pull resistors. clock output. (See Frequency Selection table page power-up, function will activated. When Low, output frequency pin35 48MHz. When High, Pin35 24MHz. After input data latched, this clock output. internal pull resistor. 48MHz Clock output with drive strength. This latches value power-up. (See Frequency selection table page3). This internal pull resistor. 48MHz Clock output with drive strength. This latches value power-up. (See Frequency selection table page3). This internal pull resistor. Serial data inputs serial interface port. Power Down Control input. When low, will disable clock outputs including internal crystal clock. enable watchdog timer masks action. 2.5V Clocks with frequencies defined Frequency Selection table page3. 2.5V APIC Clock output running Synchronous with PCI/2 clock output. Power supply REF, crystal oscillator, Core. Power supply 3V66(0:2). Power supply (0:7). Power supply 48MHz 24MHz. Power supply SDRAM (0:11), SDRAM_F. Power supply APIC 2.5V. Power supply (0:1) 2.5V. Ground.
03/13/00 Page
48MHzX2/FS3
24_48MHzx2/FS2 SDATA SCLK WDRESET# CPU(0:1) APIC VDD1 VDD2 VDD3 VDD4 VDD5 VDDL1 VDDL2
52,51 10,18 25,32,37,45 4,5,14,21,28, 29,36,41,49,50
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
PLL203-61
Programmable Clock Generator with 133MHz
FREQUENCY (MHz) SELECTION TABLE
55.0 60.0 66.8 68.3 70.0 72.0 75.0 77.0 83.3 90.0 100.3 103.0 112.5 115.0 120.0 125.0 128.0 130.0 133.7 137.0 140.0 145.0 150.0 153.3 125.0 130.0 133.7 137.0 140.0 145.0 150.0 153.3
SDRAM
82.5 90.0 100.2 102.5 105.0 108.0 112.5 115.5 83.3 90.0 100.3 103.0 112.5 115.0 120.0 125.0 128.0 130.0 133.7 137.0 140.0 145.0 150.0 153.3 93.8 97.5 100.3 102.8 105.0 108.8 112.5 115.0
3V66
55.0 60.0 66.8 68.3 70.0 72.0 75.0 77.0 55.5 60.0 66.9 68.7 75.0 76.7 80.0 83.3 64.0 65.0 66.9 68.5 70.0 72.5 75.0 76.7 62.5 65.0 66.9 68.5 70.0 72.5 75.0 76.7
27.5 30.0 33.4 34.0 35.0 36.0 37.5 38.5 27.8 30.0 33.4 34.3 37.5 38.3 40.0 41.7 32.0 32.5 33.4 34.3 35.0 36.3 37.5 38.3 31.3 32.5 33.4 34.3 35.0 36.3 37.5 38.3
APIC
13.8 15.0 16.7 17.1 17.5 18.0 18.8 19.3 13.9 15.0 16.7 17.2 18.8 19.2 20.0 20.8 16.0 16.3 16.7 17.1 17.5 18.1 18.8 19.2 15.6 16.3 16.7 17.1 17.5 18.1 18.8 19.2
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
03/13/00 Page
PLL203-61
Programmable Clock Generator with 133MHz
FREQUENCY (MHz) SELECTION TABLE GROUP TIMING
(CPU:SDRAM:3V66)
Group Timing
55.0 60.0 66.8 68.3 70.0 72.0 75.0 77.0 83.3 90.0 100.3 103.0 112.5 115.0 120.0 125.0 128.0 130.0 133.7 137.0 140.0 145.0 150.0 153.3 125.0 130.0 133.7 137.0 140.0 145.0 150.0 153.3
SDRAM
82.5 90.0 100.2 102.5 105.0 108.0 112.5 115.5 83.3 90.0 100.3 103.0 112.5 115.0 120.0 125.0 128.0 130.0 133.7 137.0 140.0 145.0 150.0 153.3 93.8 97.5 100.3 102.8 105.0 108.8 112.5 115.0
3V66
55.0 60.0 66.8 68.3 70.0 72.0 75.0 77.0 55.5 60.0 66.9 68.7 75.0 76.7 80.0 83.3 64.0 65.0 66.9 68.5 70.0 72.5 75.0 76.7 62.5 65.0 66.9 68.5 70.0 72.5 75.0 76.7
27.5 30.0 33.4 34.0 35.0 36.0 37.5 38.5 27.8 30.0 33.4 34.3 37.5 38.3 40.0 41.7 32.0 32.5 33.4 34.3 35.0 36.3 37.5 38.3 31.3 32.5 33.4 34.3 35.0 36.3 37.5 38.3
APIC
13.8 15.0 16.7 17.1 17.5 18.0 18.8 19.3 13.9 15.0 16.7 17.2 18.8 19.2 20.0 20.8 16.0 16.3 16.7 17.1 17.5 18.1 18.8 19.2 15.6 16.3 16.7 17.1 17.5 18.1 18.8 19.2
(66:100:66)
(100:100:66)
(133:133:66)
(133:100:66)
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
03/13/00 Page
PLL203-61
Programmable Clock Generator with 133MHz
GROUP OFFSET TIMING RELATIONSHIP
Group
10ns
20ns
30ns
40ns
Cycle Repeats 66MHz SDRAM 100MHz 3V66 66MHz Group Cycle Repeats 100MHz 5.0ns SDRAM 100MHz 5.0ns 3V66 66MHz Group Cycle Repeats 133MHz 3.75ns SDRAM 133MHz 0.0ns 3V66 66MHz Group Cycle Repeats 133MHz 0.0ns SDRAM 100MHz 0.0ns 3V66 66MHz 0.0ns 10ns 20ns 3.75ns 30ns 40ns 0.0ns 10ns 20ns 30ns 40ns 0.0ns 7.5ns 0.0ns 2.5ns
10ns
20ns
30ns
40ns
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
03/13/00 Page
PLL203-61
Programmable Clock Generator with 133MHz
CONFIGURATION SETTING
Address Assignment Slave Receiver/Transmitter Data Transfer Rate
Provides both slave write readback functionality Standard mode 100kbits/s serial bits will read sent clock driver following order Byte Bits Byte Bits Byte Bits This serial protocol designed allow both blocks write read from controller. bytes must accessed sequential order from lowest highest byte. Each byte transferred must followed acknowledge bit. byte transferred without acknowledged will terminate transfer. write read block both begins with master sending slave address write condition (0xD2) read condition (0xD3). Following acknowledge this address byte, Write Mode: Command Byte Byte Count Byte must sent master ignored slave, Read Mode: Byte Count Byte will read master then other Data Byte. Byte Count Byte default power-up (0x09).
Serial Bits Reading
Data Protocol
CONTROL REGISTERS
BYTE Functional Frequency Select Clock Register (1=Enable, 0=Disable)
Pin#
Default
Description
Frequency selection Table Frequency selection Table Frequency selection Table Frequency selection Table Frequency selection control 1=Via I2C, 0=Via External jumper Frequency selection Table Normal ±0.25% Center Spread Normal Tristate outputs
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
03/13/00 Page
PLL203-61
Programmable Clock Generator with 133MHz
BYTE Control Register (1=Enable, 0=Disable)
Pin#
Default
Description
Inverted Power-up latched value (Read only) Inverted Power-up latched value (Read only) Inverted Power-up latched value (Read only) 24MHz (Active/Inactive) Inverted Power-up latched value (Read only) 48MHzX2 (Active/Inactive) Reserved Reserved
BYTE SDRAM Clock Register (1=Enable, 0=Disable)
Pin#
Default
Description
SDRAM7 (Active/Inactive) SDRAM6 (Active/Inactive) SDRAM5 (Active/Inactive) SDRAM4 (Active/Inactive) SDRAM3 (Active/Inactive) SDRAM2 (Active/Inactive) SDRAM1 (Active/Inactive) SDRAM0 (Active/Inactive)
BYTE Clock Register (1=Enable, 0=Disable)
Pin#
Default
Description
PCI7 (Active/Inactive) PCI6 (Active/Inactive) PCI5 (Active/Inactive) PCI4 (Active/Inactive) PCI3 (Active/Inactive) PCI2 (Active/Inactive) PCI1 (Active/Inactive) PCI0 (Active/Inactive)
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
03/13/00 Page
PLL203-61
Programmable Clock Generator with 133MHz
BYTE Control Register (1=Enable, 0=Disable)
Pin#
Default
Description
3V66_0 (Active/Inactive) 3V66_1 (Active/Inactive) 3V66_2 (Active/Inactive) Inverted Power-up latched value (Read only) APIC (Active/Inactive) Inverted Power-up latched value (Read only) CPU1 (Active/Inactive) CPU0 (Active/Inactive)
BYTE SDRAM Clock Register (1=Enable, 0=Disable)
Pin#
Default
Description
Reserved Reserved Reserved Reserved SDRAM11 (Active/Inactive) SDRAM10 (Active/Inactive) SDRAM9 (Active/Inactive) SDRAM8 (Active/Inactive)
BYTE Fall-Back Frequency Revision Vendor Register (1=Enable, 0=Disable)
Pin#
Default
Description
Revision Revision Revision Fall-back Frequency selection Fall-back Frequency selection Fall-back Frequency selection Fall-back Frequency selection Fall-back Frequency selection Revision Vendor Vendor Vendor Vendor
Note: Default value power-up
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
03/13/00 Page
PLL203-61
Programmable Clock Generator with 133MHz
BYTE Linear Programming Register (1=Enable, 0=Disable)
Pin#
Default
Description
Linear programming sign "+", Linear programming magnitude (MSB) Linear programming magnitude Linear programming magnitude Linear programming magnitude Linear programming magnitude Linear programming magnitude Linear programming magnitude (LSB)
Note: This register will initialized following WATCHDOG RESET.
BYTE WATCHDOG TIMER Device Register (1=Enable, 0=Disable)
Pin#
Default
Device
Description
Watchdog Timer Enable Bit. 1=Enable, 0=Disable Watchdog Time Interval (MSB) Watchdog Time Interval Watchdog Time Interval Watchdog Time Interval Watchdog Time Interval Watchdog Time Interval (LSB) Device Device Device Device Device Device
Note: Default value power-up
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
03/13/00 Page
PLL203-61
Programmable Clock Generator with 133MHz
PROGRAMMING FREQUENCY simplify traditional loop counter setting, PLL203-61 device incorporates SMART-BYTE technology with single byte programming better optimize clock jitter spread spectrum performance. Detail PLL203-61's dual mode frequency programming method described below: ROM-table Frequency Programming: pre-defined frequencies found Frequency table accessed either through external jumpers setting internal register BYTE0. Micro-step Linear Frequency Programming: Frequency programmed fine linear positive negative stepping around selected frequency Frequency table. highest step either +127 -127. Other frequencies will changed proportionally with rate that frequency change. formula follow:
CPU.ROM-Table (=0.22 0.15)
Where: magnitude factor defined Byte 7.bit(0:6) (sign bit) defined Byte7.bit constant related CPU's three Timing groups definition 0.22 (for Group B,C) 0.15 (for Group A,D)
FREQUENCY PROGRAMMING EXAMPLE: Procedures program target frequency 123.0 Group timing:
Locate closest frequency from Frequency-ROM table: 120.0 0.22 Group Solve (Linear Magnitude factor) integer: ROMTABLE (123 120) 0.22 Program register:
Setting I2C.BYTE0 Setting I2C.BYTE7
SDRAM 3V66
Sign
120.0 (0.22) 120.0 (1+2.6%) 80.0 (1+2.6%) 40.0 (1+2.6%)
123.08 frequency increased 123.08 82.04 41.02
03/13/00 Page
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
PLL203-61
Programmable Clock Generator with 133MHz
BUILT-IN WATCHDOG TIMER (WDT) Watchdog timer used perform safe recovery frequency switching causes system enter into "Hang-up" state within reasonable period time Watchdog time interval). watchdog time interval programmed between seconds with increment second setting value I2C.Byte8.Bit(5:0). Once Enabled, disabled within period that shorter than programmed watchdog interval; otherwise will generate 500ms watchdog reset pulse provoke system reset. After system restarts, PLL203-61 will start from predefined Fall-back Frequency (the value Byte6,bits(0:4)). system reason fails again Fall-back Frequency, internal hardware will then generate watchdog reset restart system from value external hardware jumper setting ensure safe recovery. Example usage: System power-up CPU= 66.8MHz (Group where external jumpers used. Switch target CPU=100.3MHz frequency (Group with following register setting:
FSEL
Setting I2C.BYTE0
Setting I2C.BYTE7
Sign
WD-Timer Setting I2C.BYTE8
FBSEL
Setting I2C.BYTE6
fall-back frequency same location that FSEL since frequency switching between different timing groups will cause system hang After timer expired seconds, system will restart properly target 100.3MHz capable; otherwise will perform another reset action restart system from 66.8 Switch target CPU=78Mhz within same timing Group fall-back frequency recommended most safe comfortable level ensure successful reboot such 72.0 system unable switch 78Mhz.
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
03/13/00 Page
PLL203-61
Programmable Clock Generator with 133MHz
OPERATIONAL FLOW CHART START Register Loading: Fall-Back, WD-TIMER, WD-ENABLE Register Loading: FSEL
Disable WDEnable Target Setting
SUCCESS
Wait System Response
Copy Fall-Back Frequency Setting Frequency Setting Disable WDEnable Fall-Back Frequency Setting
FAIL After specified WD-Timer Expired
SUCCESS
System Restart Fall-back Frequency
FAIL After specified WD-Timer Expired
System Restart Jumper-Setting Frequency
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
03/13/00 Page
PLL203-61
Programmable Clock Generator with 133MHz
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings PARAMETERS
Supply Voltage Input Voltage, Output Voltage, Storage Temperature Ambient Operating Temperature Junction Temperature Voltage
SYMBOL
MIN.
MAX.
UNITS
Exposure device under conditions beyond limits specified Maximum Ratings extended periods cause permanent damage device affect product reliability. These conditions represent stress rating only, functional operations device these other conditions above operational limits noted this specification implied.
AC/DC Electrical Specifications PARAMETERS
Reference input clock rise time Reference input clock fall time Dynamic Current Static Current Input High Voltage Input Voltage Input Frequency
SYMBOL
CONDITIONS
From 0.8V From 0.8V 66Mhz load
MIN.
TYP.
MAX.
UNITS
+0.3
Inputs except inputs except
-0.3 14.318
Logic Inputs Output Capacitance 11,12,13,23,24,34,35,56
Kohm Kohm
Input Capacitance
Pull resistor Pull down resistor
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
03/13/00 Page
PLL203-61
Programmable Clock Generator with 133MHz
Output Buffer Electrical Specifications
Unless otherwise stated, power supplies 3.3V±5%, ambient temperature range 70°C
PARAMETERS
SYMBOL
OUTPUTS
CPU,APIC
CONDITIONS
Measured 0.4V 2.0V, =10-20pf, 2.5V±0.5% Measured 0.4V 2.4V, =10-20pf Measured 0.4V 2.4V, =10-30pf Measured 2.0V 0.4V, =10-20pf, 2.5V±0.5% Measured 2.4V 0.4V, =10-20pf Measured 2.4V 0.4V, =10-30pf Measured 1.25V =20pf, =2.5V Measured 1.5V, =20~30pf, =3.3V 2.5V, Measured 1.25V
MIN.
TYP.
MAX.
UNITS
Output Rise time
REF,48MHZ, 24_48MHZ SDRAM,3V66 CPU,APIC
Output Fall time
REF,48MHZ, 24_48MHZ SDRAM,3V66 CPU,APIC
Duty Cycle
REF,48MHZ, SDRAM, PCI,3V66 APIC
Clock Skew (pin-pin)
PSKEW
3V66 SDRAM PCI, 48MHZ 66MhZ CPU-SDRAM 100Mhz 133Mhz 66MhZ -0.5 -0.5 -0.5 frequency Measured 1.5V
Clock Skew
SKEW
CPU-3V66
100Mhz 133Mhz
SDRAM-3V66 3V66-PCI PCI-APIC
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
03/13/00 Page
PLL203-61
Programmable Clock Generator with 133MHz
Output Buffer Electrical Specifications, continued
Unless otherwise stated, power supplies 3.3V±5%, ambient temperature range 70°C
PARAMETERS
SYMBOL
OUTPUTS
APIC
CONDITIONS
=2.5V±0.5%
MIN.
13.5
TYP.
MAX.
UNITS
Output Impedance
REF,48MHZ SDRAM PCI,3V66 APIC 1.0V 2.375V 1.0V 2.375V 1.0V 3.135V 2.0V 3.135V 1.0V 3.135V 1.2V 0.3V 1.2V 0.3V 1.95V 0.4V 1.0V 0.4V 1.95V 0.4V Measured 1.25V =3.3V±0.5%
ohms
Output High Current
REF,48MHZ SDRAM PCI,3V66 APIC
Output Current
REF,48MHZ SDRAM PCI,3V66 APIC
Jitter (cycle cycle)
cyc-cyc
SDRAM 48MHZ,PCI,3V66 Measured 1.5V
1000
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
03/13/00 Page
PLL203-61
Programmable Clock Generator with 133MHz
PACKAGE INFORMATION
0.395 0.420 10.033 10.668
0.291 0.299 7.392 7.959
0.008 0.0135 0.203 0.343
0.025 0.835
0.015 (0.381) 0.010 0.016 (0.25 0.41) 0.720 0.730 (18.29 16.00)
0.087 0.094 (2.224 2.399)
0.095 0.110 (2.416 2.955) 30-6 0.050 (1.346) 0.008 0.016 (0.20 0.41)
56PIN SSOP
ORDERING INFORMATION
part ordering, please contact Sales Department:
47745 Fremont Blvd., Fremont, 94538, Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
order number this device combination following: Device number, Package type Operating temperature range
PLL203-61
PART NUMBER TEMPERATURATURE C=COMMERCIAL M=MILITARY I=INDUSTRAL PACKAGE TYPE X=SSOP
PhaseLink Corporation, reserves right make changes products specifications, both time without notice. information furnished PhaseLink believed accurate reliable. However, PhaseLink makes guarantee warranty concerning accuracy said information shall responsible loss damage whatever nature resulting from reliance upon this product. LIFE SUPPORT POLICY: PhaseLink's products authorized critical components life support devices systems without express written approval President PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
03/13/00 Page
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