Motherboard Clock Generator with 133MHz Generates clock frequenci
|
|
|
Top Searches for this datasheet
PLL203-11
Motherboard Clock Generator with 133MHz
Generates clock frequencies INTEL Chip sets. Supports clocks, high-speed SDRAM clocks 2-DIMM applications clocks. Three 3.3V 3V66MHz clocks. 24/48MHz clock 48MHz clocks. double-strength 2.5V IOAPIC clock. double-strength 14.318MHz reference clock. Support 2-wire serial interface with builtin Vendor Device Revision Single byte micro-step linear Frequency programming with glitch free smooth switching. Built-in programmable watchdog timer seconds with 1-second interval. will generate reset output when timer expired. Spread Spectrum 0.25% center spread, -0.5% downspread. duty cycle with jitter. Available SSOP.
CONFIGURATION
REFx2/SEL24_48*^ VDD1 XOUT 3V66_0 3V66_1 3V66_2 VDD2 VDD3 PCI0x2/FS0 PCI1x2/FS1
VDDL1 IOAPICx2 VDDL2 CPU0 CPU1 SDRAM0 SDRAM1 SDRAM2 VDD5 SDRAM3 SDRAM4 SDRAM5 SDRAM6 SDRAM7 SDRAM_F VDD5 24_48Mhz/FS2 48Mhz_1/FS3*^
PLL203-11
PCI2 PCI3 PCI4 VDD3 PCI5 PCI6 PD#/WDRESET# SCLK SDATA
48Mhz_0x2/FS4 VDD4
Note: pull down, Pull Active low,
BLOCK DIAGRAM
VDD1 XTAL REFx2
Bi-directional latched power-up
POWER GROUP
XOUT
VDDL2 (0:1) (0:4)* VDDL1 IOAPIC PLL1 Control Logic SDATA SCLK Logic VDD2 3V66 (0:2)
VDD1: REF, XIN, XOUT, CORE VDD2: 3V66(0:2) VDD3: PCI(0:6) VDD4: 48MHz_0, 48MHz_1 24_48MHz VDD5: SDRAM(0:7)& SDRAM_F VDDL1: IOAPIC VDDL2: CPU(0:1)
SPECIFICATIONS
Cycle Cycle jitter: 250ps: CPU, SDRAM 500ps: APIC, 48Mhz, 3V66, Skew: 250ps: CPU, 3V66 500ps: SDRAM, APIC, PCI, 48Mhz Clock Offset (@CPU=100Mhz): 4.5~5.5ns: CPU-SDRAM, CPU-3V66 1.5~3.5ns: 3V66-PCI -0.5~0.5ns: SDRAM-3V66, PCI-APIC
VDD3 (0:6) VDD5 SDRAM (0:7) SDRAM_F WDRESET#
WATCH
VDD4 48Mhz_0 PLL2 48Mhz_1
24_48Mhz
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
05/01/00 Page
PLL203-11
Motherboard Clock Generator with 133MHz
DESCRIPTIONS
Name
REFx2/SEL24_48 XOUT 3V66(0:2) SDRAM(0:7), SDRAM_F PCI0x2/FS0, PCI1x2/FS1 PCI(2:6) 48MHz_0x2/FS4
Number
7,8,9 41,40,39,37, 36,35,33,32,31 12,13 15,16,17,19,20
Type
Description
power this will select 24MHz (when high) 48MHz (when low) output. After input sampling, this double strength output. This internal pull-up resistor. 14.318Mhz crystal input connected crystal. 14.318Mhz crystal output. 66MHz clock output. (See Frequency Selection table page3). 3.3V SDRAM Clocks with frequencies defined Frequency Selection table. SDRAM_F free running clock output. clock output. These pins latch FS(0:1) value power-on. (See Frequency Selection table page internal pull resistor, while internal pull down resistor. clock output. (See Frequency Selection table page Double strength 48MHz clock output. This latches value poweron. (See Frequency selection table page3). This internal pull resistor. 48MHz clock output. This latches value power-on. (See Frequency selection table page3). This internal pull resistor. power this input will determine clock frequency. internal pull down resistor. Serial data inputs serial interface port. Power Down Control input. When low, will disable clock outputs including internal crystal clock. enable watchdog timer masks action. 2.5V Clocks with frequencies defined Frequency Selection table page3. 2.5V double strength IOAPIC clock output. Power supply REF, crystal oscillator, Core. Power supply 3V66(0:2). Power supply (0:6). Power supply 48MHz 24_48MHz. Power supply SDRAM (0:7), SDRAM_F. Power supply IOAPIC 2.5V. Power supply (0:1) 2.5V. Ground.
05/01/00 Page
48MHz_1/FS3 24_48MHz/FS2 SDATA SCLK PD#/WDRESET# CPU(0:1) IOAPICx2 VDD1 VDD2 VDD3 VDD4 VDD5 VDDL1 VDDL2
45,44 11,18 30,38 5,6,14,21,29, 34,42,43
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
PLL203-11
Motherboard Clock Generator with 133MHz
FREQUENCY (MHz) SELECTION TABLE
Byte0 Bit2
default
66.6 66.8 68.6 71.3 100.0 100.3 103.0 107.0 133.3 133.7 137.3 120.0 133.3 133.7 137.3 120.0 136.0 140.0 142.6 145.3 136.0 140.0 142.6 145.3 146.6 153.3 160.0 166.6 146.6 160.0 166.6 200.0
SDRAM
100.0 100.3 103.0 107.0 100.0 100.3 103.0 107.0 133.3 133.7 137.3 120.0 100.0 100.3 103.0 90.0 136.0 140.0 142.6 145.3 102.0 105.0 107.0 109.0 146.6 153.3 160.0 166.6 110.0 120.0 125.0 200.0
3V66
66.6 66.8 68.6 71.3 66.6 66.8 68.6 71.3 66.6 66.8 68.6 60.0 66.6 66.8 68.6 60.0 68.0 70.0 71.3 72.6 68.0 70.0 71.3 72.6 73.3 76.6 80.0 83.3 73.3 80.0 83.3 100.0
33.3 33.4 34.3 35.6 33.3 33.4 34.3 35.6 33.3 33.4 34.3 30.0 33.3 33.4 34.3 30.0 34.0 35.0 35.6 36.3 34.0 35.0 35.6 36.3 36.6 38.3 40.0 41.6 36.6 40.0 41.6 50.0
IOAPIC
16.6 16.7 17.1 17.8 16.6 16.7 17.1 17.8 16.6 16.7 17.1 15.0 16.6 16.7 17.1 15.0 17.0 17.5 17.8 18.1 17.0 17.5 17.8 18.1 18.3 19.1 20.0 20.8 18.3 20.0 20.8 25.0
Spread Spectrum Modulation
-0.5% ±0.25% ±0.25% ±0.25% -0.5% ±0.25% ±0.25% ±0.25% -0.5% ±0.25% ±0.25% ±0.25% -0.5% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25%
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
05/01/00 Page
PLL203-11
Motherboard Clock Generator with 133MHz
FREQUENCY (MHz) SELECTION TABLE GROUP TIMING
(CPU:SDRAM:3V66)
Group Timing
66.6 66.8 68.6 71.3 100.0 100.3 103.0 107.0 120.0 133.3 133.7 136.0 137.3 140.0 142.6 145.3 146.6 153.3 160.0 166.6 200.0 120.0 133.3 133.7 137.3 136.0 140.0 142.6 145.3 146.6 160.0 166.6
SDRAM
100.0 100.3 103.0 107.0 100.0 100.3 103.0 107.0 120.0 133.3 133.7 136.0 137.3 140.0 142.6 145.3 146.6 153.3 160.0 166.6 200.0 90.0 100.0 100.3 103.0 102.0 105.0 107.0 109.0 110.0 120.0 125.0
3V66
66.6 66.8 68.6 71.3 66.6 66.8 68.6 71.3 60.0 66.6 66.8 68.0 68.6 70.0 71.3 72.6 73.3 76.6 80.0 83.3 100.0 60.0 66.6 66.8 68.6 68.0 70.0 71.3 72.6 73.3 80.0 83.3
33.3 33.4 34.3 35.6 33.3 33.4 34.3 35.6 30.0 33.3 33.4 34.0 34.3 35.0 35.6 36.3 36.6 38.3 40.0 41.6 50.0 30.0 33.3 33.4 34.3 34.0 35.0 35.6 36.3 36.6 40.0 41.6
IOAPIC
16.6 16.7 17.1 17.8 16.6 16.7 17.1 17.8 15.0 16.6 16.7 17.0 17.1 17.5 17.8 18.7 18.3 19.1 20.0 20.8 25.0 15.0 16.6 16.7 17.1 17.0 17.5 17.8 18.1 18.3 20.0 20.8
(66:100:66)
(100:100:66)
(133:133:66)
(133:100:66)
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
05/01/00 Page
PLL203-11
Motherboard Clock Generator with 133MHz
GROUP OFFSET TIMING RELATIONSHIP
Group
10ns
20ns
30ns
40ns
Cycle Repeats 66MHz SDRAM 100MHz 3V66 66MHz Group Cycle Repeats 100MHz 5.0ns SDRAM 100MHz 5.0ns 3V66 66MHz Group Cycle Repeats 133MHz 3.75ns SDRAM 133MHz 0.0ns 3V66 66MHz Group Cycle Repeats 133MHz 0.0ns SDRAM 100MHz 0.0ns 3V66 66MHz 0.0ns 10ns 20ns 3.75ns 30ns 40ns 0.0ns 10ns 20ns 30ns 40ns 0.0ns 7.5ns 0.0ns 2.5ns
10ns
20ns
30ns
40ns
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
05/01/00 Page
PLL203-11
Motherboard Clock Generator with 133MHz
CONFIGURATION SETTING
Address Assignment Slave Receiver/Transmitter Data Transfer Rate
Provides both slave write readback functionality Standard mode 100kbits/s serial bits will read sent clock driver following order Byte Bits Byte Bits Byte Bits This serial protocol designed allow both blocks write read from controller. bytes must accessed sequential order from lowest highest byte. Each byte transferred must followed acknowledge bit. byte transferred without acknowledged will terminate transfer. write read block both begins with master sending slave address write condition (0xD2) read condition (0xD3). Following acknowledge this address byte, Write Mode: Command Byte Byte Count Byte must sent master ignored slave, Read Mode: Byte Count Byte will read master then other Data Byte. Byte Count Byte default power-up (0x09).
Serial Bits Reading
Data Protocol
CONTROL REGISTERS
BYTE Functional Frequency Select Clock Register (1=Enable, 0=Disable)
Pin#
Default
Description
Frequency selection Table Frequency selection Table Frequency selection Table Frequency selection Table Frequency selection control 1=Via I2C, 0=Via External jumper Frequency selection Table Normal Spread Spectrum Enable Normal Tristate outputs
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
05/01/00 Page
PLL203-11
Motherboard Clock Generator with 133MHz
BYTE SDRAM Clock Register (1=Enable, 0=Disable)
Pin#
Default
Description
Inverted Power-on latched value (Read only) Inverted Power-on latched value (Read only) SDRAM_F (Active/Inactive) SDRAM7 (Active/Inactive) SDRAM6 (Active/Inactive) SDRAM5 (Active/Inactive) SDRAM4 (Active/Inactive) SDRAM3 (Active/Inactive)
BYTE Clock Register (1=Enable, 0=Disable)
Pin#
Default
Description
Inverted Power-on latched value (Read only) PCI6 (Active/Inactive) PCI5 (Active/Inactive) PCI4 (Active/Inactive) PCI3 (Active/Inactive) PCI2 (Active/Inactive) PCI1 (Active/Inactive) PCI0 (Active/Inactive)
BYTE 3V66 Clock Register (1=Enable, 0=Disable)
Pin#
Default
Description
Inverted Power-on latched value (Read only) Reserved Reserved Inverted Power-on latched value (Read only) Reserved 3V66_0 3V66_1 3V66_2
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
05/01/00 Page
PLL203-11
Motherboard Clock Generator with 133MHz
BYTE Control Register (1=Enable, 0=Disable)
Pin#
Default
Description
Reserved Reserved Reserved Reserved Reserved 48MHz_0 48MHz_1 24_48MHz
BYTE Control Register (1=Enable, 0=Disable)
Pin#
Default
Description
Inverted Power-on latched SEL24_48 value (Read only) IOAPIC CPU1 CPU0 SDRAM2 SDRAM1 SDRAM0
BYTE Fall-Back Frequency/ Revision/ Vendor Register (1=Enable, 0=Disable)
Pin#
Default
Revision Revision Revision
Description
Fall-back Frequency selection Fall-back Frequency selection Fall-back Frequency selection Fall-back Frequency selection Fall-back Frequency selection
Revision Vendor Vendor Vendor Vendor
Note: Default value power-up
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
05/01/00 Page
PLL203-11
Motherboard Clock Generator with 133MHz
BYTE Linear Programming Register (1=Enable, 0=Disable)
Pin#
Default
Description
Linear programming sign "+", Linear programming magnitude Linear programming magnitude Linear programming magnitude Linear programming magnitude Linear programming magnitude Linear programming magnitude Linear programming magnitude
Note: This register will initialized following WATCHDOG RESET.
BYTE WATCHDOG TIMER Device Register (1=Enable, 0=Disable)
Pin#
Default
Device
Description
Watchdog Timer Enable Bit. 1=Enable, 0=Disable Watchdog Time Interval (MSB) Watchdog Time Interval Watchdog Time Interval Watchdog Time Interval Watchdog Time Interval Watchdog Time Interval (LSB) Device Device Device Device Device Device
Note: Default value power-up
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
05/01/00 Page
PLL203-11
Motherboard Clock Generator with 133MHz
PROGRAMMING FREQUENCY simplify traditional loop counter setting, PLL203-01 device incorporates SMART-BYTE technology with single byte programming better optimize clock jitter spread spectrum performance. Detail PLL203-01's dual mode frequency programming method described below: ROM-table Frequency Programming: pre-defined frequencies found Frequency table accessed either through external jumpers setting internal register BYTE0. Fine-step Linear Frequency Programming: Frequency programmed fine linear positive negative stepping around current selected frequency Frequency table. highest step either +127 -127. Other frequencies will changed proportionally with rate that frequency change. formula follow:
CPU-ROM-table (=0.22 0.15)
Where: magnitude factor defined Byte 7.bit(0:6) (sign bit) defined Byte7.bit constant related CPU's three Timing groups definition 0.22 (for Group B,C) 0.15 (for Group A,D)
FREQUENCY PROGRAMMING EXAMPLE: Procedures program target frequency 123.0 Group timing:
Locate closest frequency from Frequency from Frequency-ROM table: 120.0 0.22 Group Solve (Linear Magnitude factor) integer: CPU-ROMTABLE (123 120) 0.22 Program register:
Setting I2C.BYTE0 Setting I2C.BYTE7
SDRAM 3V66
Sign
120.0 120.0 80.0 40.0
(0.22) 2.6%) 2.6%) 2.6%)
123.08 frequency increased 2.6% 123.12 82.08 41.04
05/01/00 Page
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
PLL203-11
Motherboard Clock Generator with 133MHz
BUILT-IN WATCHDOG TIMER (WDT) Watchdog timer used perform safe recovery frequency switching causes system enter into "Hang-up" state within reasonable period time Watchdog time interval). watchdog time interval programmed between seconds with increment second setting value I2C.Byte8.Bit(5:0). Once Enabled, disabled within period that shorter than programmed watchdog interval; otherwise will generate 500ms watchdog reset pulse provoke system reset. After system restarts, PLL203-61 will start from predefined Fall-back Frequency (the value Byte6,bits(0:4)). system reason fails again Fall-back Frequency, internal hardware will then generate watchdog reset restart system from value external hardware jumper setting ensure safe recovery. Example usage: System power-up CPU= 66.8MHz (Group where external jumpers used. Switch target CPU=100.3MHz frequency (Group with following register setting:
FSEL
Setting I2C.BYTE0
Setting I2C.BYTE7
Sign
WD-Timer Setting I2C.BYTE8
FBSEL
Setting I2C.BYTE6
fall-back frequency same location that FSEL since frequency switching between different timing groups will cause system hang After timer expired seconds, system will restart properly target 100.3MHz capable; otherwise will perform another reset action restart system from 66.8 Switch target CPU=78Mhz within same timing Group fall-back frequency recommended most safe comfortable level ensure successful reboot such 72.0 system unable switch 78Mhz.
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
05/01/00 Page
PLL203-11
Motherboard Clock Generator with 133MHz
OPERATIONAL FLOW CHART START Register Loading: Fall-Back, WD-TIMER, WD-ENABLE Register Loading: FSEL
Disable WDEnable Target Setting
SUCCESS
Wait System Response
Copy Fall-Back Frequency Setting Frequency Setting Disable WDEnable Fall-Back Frequency Setting
FAIL After specified WD-Timer Expired
SUCCESS
System Restart Fall-back Frequency
FAIL After specified WD-Timer Expired
System Restart Jumper-Setting Frequency
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
05/01/00 Page
PLL203-11
Motherboard Clock Generator with 133MHz
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings PARAMETERS
Supply Voltage Input Voltage, Output Voltage, Storage Temperature Ambient Operating Temperature Junction Temperature Voltage
SYMBOL
MIN.
MAX.
UNITS
Exposure device under conditions beyond limits specified Maximum Ratings extended periods cause permanent damage device affect product reliability. These conditions represent stress rating only, functional operations device these other conditions above operational limits noted this specification implied.
AC/DC Electrical Specifications PARAMETERS
Operating Supply Current Input High Current Input Current Input Current Input High Voltage Input Voltage Input Frequency
SYMBOL
DD3.3OP
CONDITIONS
66MHz With pull-up resistors With pull-up resistors Inputs except inputs except
MIN.
TYP.
MAX.
UNITS
-200 -0.3 14.318
+0.3
Logic Inputs Output Capacitance 1,12,26,27 13,28
Kohm Kohm
Input Capacitance
Power Down Supply Current Pull resistor Pull down resistor
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
05/01/00 Page
PLL203-11
Motherboard Clock Generator with 133MHz
Output Buffer Electrical Specifications
Unless otherwise stated, power supplies 3.3V±5%, ambient temperature range 70°C
PARAMETERS
SYMBOL
OUTPUTS
CPU,IOAPIC
CONDITIONS
Measured 0.4V 2.0V, =10-20pf, 2.5V±0.5% Measured 0.4V 2.4V, =10-20pf Measured 0.4V 2.4V, =10-30pf Measured 2.0V 0.4V, =10-20pf, 2.5V±0.5% Measured 2.4V 0.4V, =10-20pf Measured 2.4V 0.4V, =10-30pf Measured 1.25V =20pf, =2.5V Measured 1.5V, =20~30pf, =3.3V 2.5V, Measured 1.25V
MIN.
TYP.
MAX.
UNITS
Output Rise time
REF,48MHZ, 24_48MHZ SDRAM PCI,3V66 CPU,IOAPIC
Output Fall time
REF,48MHZ, 24_48MHZ SDRAM PCI,3V66 CPU,IOAPIC
Duty Cycle
REF,48MHZ, SDRAM, PCI,3V66 IOAPIC
Clock Skew (pin-pin)
PSKEW
3V66 SDRAM,48MHz 66MhZ CPU-SDRAM 100Mhz 133Mhz 66MhZ -0.5 -0.5 -0.5 frequency Measured 1.5V
Clock Skew
SKEW
CPU-3V66
100Mhz 133Mhz
SDRAM-3V66 3V66-PCI PCI-IOAPIC
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
05/01/00 Page
PLL203-11
Motherboard Clock Generator with 133MHz
Output Buffer Electrical Specifications, continued
Unless otherwise stated, power supplies 3.3V±5%, ambient temperature range 70°C
PARAMETERS
SYMBOL
OUTPUTS
IOAPIC
CONDITIONS
=2.5V±0.5%
MIN.
13.5
TYP.
MAX.
UNITS
Output Impedance
REF,48MHZ SDRAM PCI,3V66 IOAPIC 1.0V 2.375V 1.0V 2.375V 1.0V 3.135V 2.0V 3.135V 1.0V 3.135V 1.2V 0.3V 1.2V 0.3V 1.95V 0.4V 1.0V 0.4V 1.95V 0.4V Measured 1.25V =3.3V±0.5%
Output High Current
REF,48MHZ SDRAM PCI,3V66 IOAPIC
Output Current
REF,48MHZ SDRAM PCI,3V66 IOAPIC
Jitter (cycle cycle)
cyc-cyc
SDRAM PCI,3V66 REF,48MHz Measured 1.5V
1000
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
05/01/00 Page
PLL203-11
Motherboard Clock Generator with 133MHz
PACKAGE INFORMATION
0.400 0.410 10.160 10.414
0.292 0.299 7.417 7.959
0.008 0.0135 0.203 0.343
0.025 0.835
0.015 (0.381) 0.010 0.016 (0.25 0.41) 0.620 0.630 (15.75 16.00)
0.088 0.096 (2.250 2.450)
0.097 0.104 (2.467 2.642) 30-6 0.050 (1.346) 0.008 0.016 (0.20 0.41)
48PIN SSOP
ORDERING INFORMATION
part ordering, please contact Sales Department:
45437 Warm Springs Blvd., Fremont, 94539, Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
order number this device combination following: Device number, Package type Operating temperature range
PLL203-11
PART NUMBER TEMPERATURATURE C=COMMERCIAL M=MILITARY I=INDUSTRAL PACKAGE TYPE X=SSOP
PhaseLink Corporation, reserves right make changes products specifications, both time without notice. information furnished PhaseLink believed accurate reliable. However, PhaseLink makes guarantee warranty concerning accuracy said information shall responsible loss damage whatever nature resulting from reliance upon this product. LIFE SUPPORT POLICY: PhaseLink's products authorized critical components life support devices systems without express written approval President PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
05/01/00 Page
Other recent searches
X1226 - X1226 X1226 Datasheet
S1C17704 - S1C17704 S1C17704 Datasheet
PN3643 - PN3643 PN3643 Datasheet
LP2986 - LP2986 LP2986 Datasheet
CM71-10108-2E - CM71-10108-2E CM71-10108-2E Datasheet
ATE-1 - ATE-1 ATE-1 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
