Programmable Clock Generator Apollo Pro-266 with Generates clock

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Programmable Clock Generator Apollo Pro-266 with Generates clock

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PLL202-54
Programmable Clock Generator Apollo Pro-266 with
Generates clock frequencies Pentium/ system processor. Support clocks, PCI. Enhanced Output Drive selectable I2C. 48MHz clock 24_48MHz clock I2C). Three 2.5V APIC 14.318MHz ref. clocks. Program 5-bit (Voltage Identification) through I2C. Power management control stop CPU, PCI, AGP, APIC clocks. Supports 2-wire serial interface with readback. Single byte micro-step linear Frequency Programming with glitch free smooth switching. Built-in programmable watchdog timer. Spread Spectrum ±0.25% center, ±0.5% center, ±0.75% center, -0.5% downspread duty cycle with jitter. Available SSOP.
CONFIGURATION
VDD1 XOUT VDD2 48MHz/FS3 24_48Mhz/FS2 PCI_F PCI0 PCI1 PCI2 PCI3 VDD3 PCI4 PCI5 PCI6 PCI7 FS1^ FS0^ AGP0 VDD3 VIDENB VID0 VID1 VID2 REF0 REF1/FS4 VDDL1 APIC0 APIC1 APIC2 VDDL2 CPU0 CPU1 VDDL2 CPU2 CPU_STOP# PCI_STOP/WDRESET# VDD4 SDATA SCLK AGP2 AGP1 VDD5 VID4 VID3
PLL202-54
Note: Pull Active Bi-directional latched power-up
BLOCK DIAGRAM
VDD1 XOUT XTAL VDDL2 (0:2) SDATA SCLK REF(0:1)
POWER GROUP
VDD1: REF(0:1), XIN, XOUT, CORE VDD2: 48MHz 24_48MHz VDD3: PCI(0:7), PCI_F VDD4: AGP(0:2) VDD5: I2C, VDDL1: APIC(0:2) VDDL2: CPU(0:2)
Logic
VDDL1 APIC (0:2)
(0:4)*
Control Logic PLL1 VDD3 (0:7) PCI_F VDD4 (0:2)
SPECIFICATIONS
Cycle Cycle jitter: 250ps. Cycle Cycle jitter: 500ps. skew: 500ps. skew 175ps. skew (CPU lead): typical 2ns. skew: 250ps.
VDD2 48Mhz PLL2
SDATA SCLK Registers
24_48Mhz VID(0:4)
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PLL202-54
Programmable Clock Generator Apollo Pro-266 with
DESCRIPTIONS
Name
VDD1 VDD2 VDD3 VDD4 VDD5 VDDL1 VDDL2 XOUT PCI_STOP/ WDRESET# CPU_STOP PCI_F, PCI(0:7) CPU(0:2) AGP(0:2) SDATA SCLK VIDENB VID(0:4) REF1/FS4* 48MHz/FS3* 24_48MHz/FS2* FS1,FS0 APIC(0:2) REF0
Number
15,24 45,49 2,8,12,19,32,33, 38,44,48,51 9,10,11,13,14, 16,17,18,20 47,46,43 23,34,35 26,27,28,29,30 55,6,7 21,22 53,52,50
Type
Description
Power supply REF(0:1), crystal oscillator core. Power supply 48MHz 24_48MHz. Power supply PCI(0:7), PCI_F. Power supply AGP(0:2). Power supply SDATA, SCLK, VID[0:4] internal Latches. Power supply APIC(0:2) (2.5V). Power supply CPU(0:2) (2.5V). Ground. 14.318MHz crystal input connected crystal. 14.318MHz crystal output. Asynchronous active input used power down device into power state. internal clocks disabled crystal stopped. When input LOW, PCI_STOP will stop PCI(0:7) except PCI_F. enable watchdog timer masks PCI_STOP action. When input LOW, CPU_STOP will stop CPU(0:2). clocks with frequencies defined Frequency Table. These pins except PCI_F will when PCI_STOP LOW. clocks with frequencies defined Frequency Table. These pins when CPU_STOP LOW. clocks outputs defined PCI. Serial data input serial interface port. When input Low, will disable output VID(0:4) which allows data directly sent PWM. When High, enables override data writing Byte5 register. This 120K internal pull voltage ouput power these pins input pins will determine clock frequency. After input sampling, these pins will generate output clocks. They have internal pull power these pins will determine clock frequency. 2.5V APIC clock output running synchronous with PCI/2 clock output. controlled byte byte 3.3V 14.318MHz clock output.
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
10/18/00 Page
PLL202-54
Programmable Clock Generator Apollo Pro-266 with
POWER MANAGEMENT
CPU_STOP PCI_SOTP CPU(0:1) Running Running Running Running PCI_F Running Running Running XTAL,VCO Running Running Running
FREQUENCY (MHz) SELECTION TABLE
200.0 190.0 180.0 170.0 166.0 160.0 150.0 145.0 140.0 136.0 130.0 124.0 66.8 100.2 118.0 133.4 66.8 100.2 115.0 133.4 66.8 100.2 110.0 133.4 105.0 90.0 85.0 78.0 66.6 100.0 75.0 133.3
80.0 76.0 72.0 68.0 66.4 64.0 75.0 72.5 70.0 68.0 65.0 62.0 66.8 66.8 78.6 66.7 66.8 66.8 76.6 66.7 66.8 66.8 73.3 66.7 70.0 60.0 56.6 78.0 66.6 66.6 75.0 66.6
40.0 38.0 36.0 34.0 33.2 32.0 37.5 36.2 35.0 34.0 32.5 31.0 33.4 33.4 39.3 33.3 33.4 33.4 38.3 33.3 33.4 33.4 36.6 33.3 35.0 30.0 28.3 39.0 33.3 33.3 37.5 33.3
APIC
20.0 19.0 18.0 17.0 16.6 13.0 18.7 18.1 17.5 17.0 16.2 15.5 16.7 16.7 19.6 16.6 16.7 16.7 19.1 16.6 16.7 16.7 18.3 16.6 17.5 15.0 14.1 19.5 16.6 16.6 18.7 16.6
Spread Spectrum
0.25% 0.25% 0.25% 0.25% 0.25% 0.25% 0.25% 0.25% 0.25% 0.25% 0.25% 0.25% 0.75% 0.75% 0.25% 0.75% 0.25% 0.25% 0.25% 0.25% 0.5% 0.5% 0.25% 0.5% 0.25% 0.25% 0.25% 0.25% 0.5% 0.5% 0.25% 0.5%
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
10/18/00 Page
PLL202-54
Programmable Clock Generator Apollo Pro-266 with
FREQUENCY (MHz) SELECTION TABLE GROUP TIMING
Divider Ratio (CPU:AGP)
(1.5
66.6 66.8 66.8 66.8 75.0 78.0 85.0 90.0 100.0 100.2 100.2 100.2 105.0 110.0 115.0 118.0 124.0 130.0 133.3 133.4 133.4 133.4 136.0 140.0 145.0 150.0 160.0 166.0 170.0 180.0 190.0 200.0
66.6 66.8 66.8 66.8 75.0 78.0 56.6 60.0 66.6 66.8 66.8 66.8 70.0 73.3 76.6 78.6 62.0 65.0 66.6 66.7 66.7 66.7 68.0 70.0 72.5 75.0 64.0 66.4 68.0 72.0 76.0 80.0
33.3 33.4 33.4 33.4 37.5 39.0 28.3 30.0 33.3 33.4 33.4 33.4 35.0 36.6 38.3 39.3 31.0 32.5 33.3 33.3 33.3 33.3 34.0 35.0 36.2 37.5 32.0 33.2 34.0 36.0 38.0 40.0
APIC
16.6 16.7 16.7 16.7 18.7 19.5 14.1 15.0 16.6 16.7 16.7 16.7 17.5 18.3 19.1 19.6 15.5 16.2 16.6 16.6 16.6 16.6 17.0 17.5 18.1 18.7 13.0 16.6 17.0 18.0 19.0 20.0
Spread Spectrum
0.5% 0.75% 0.25% 0.5% 0.25% 0.25% 0.25% 0.25% 0.5% 0.75% 0.25% 0.5% 0.25% 0.25% 0.25% 0.25% 0.25% 0.25% 0.5% 0.75% 0.25% 0.5% 0.25% 0.25% 0.25% 0.25% 0.25% 0.25% 0.25% 0.25% 0.25% 0.25%
(2.5
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
10/18/00 Page
PLL202-54
Programmable Clock Generator Apollo Pro-266 with
CONFIGURATION SETTING
Address Assignment Slave Receiver/Transmitter Data Transfer Rate
Provides both slave write readback functionality Standard mode 100kbits/s serial bits will read sent clock driver following order Byte Bits Byte Bits Byte Bits This serial protocol designed allow both blocks write read from controller. bytes must accessed sequential order from lowest highest byte. Each byte transferred must followed acknowledge bit. byte transferred without acknowledged will terminate transfer. write read block both begins with master sending slave address write condition (0xD2) read condition (0xD3). Following acknowledge this address byte, Write Mode: Command Byte Byte Count Byte must sent master ignored slave, Read Mode: Byte Count Byte will read master then other Data Byte.
Serial Bits Reading
Data Protocol
CONTROL REGISTERS
BYTE Functional Frequency Select Clock Register (1=Enable, 0=Disable)
Pin#
Default
Description
Frequency selection Table Frequency selection Table Frequency selection Table Frequency selection Table Frequency selection control 1=Via I2C, 0=Via External jumper Frequency selection Table OFF, Spread Spectrum Enable Normal, Tristate Mode outputs
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
10/18/00 Page
PLL202-54
Programmable Clock Generator Apollo Pro-266 with
BYTE Clock Register (1=Enable, 0=Disable)
Pin#
Default
Description
Inverted power latched FS2:FS1 VID2:VID1 (Read only, selectable Byte9.bit2) Fall-back Frequency FS2:FS1 (Write only) Normal, Drive Enhanced Inverted power latched VID0 (Read only, selectable Byte9.bit2) Fall-back Frequency (Write only) CPU2 Active/Inactive CPU1 Active/Inactive CPU0 Active/Inactive APIC2 (Active/Inactive)
BYTE Clock Register (1=Enable, 0=Disable)
Pin#
Default
Description
PCI7 Active/Inactive PCI6 Active/Inactive PCI5 Active/Inactive PCI4 Active/Inactive PCI3 Active/Inactive PCI2 Active/Inactive PCI1 Active/Inactive PCI0 Active/Inactive
BYTE Clock Register (1=Enable, 0=Disable)
Pin#
Default
Description
Inverted power latched VID3 (Read only, selectable Byte9.bit2) Fall-back Frequency (Write only) 24_48Mhz selection, 0=24MHz, 1=48MHz 48MHz Active/Inactive 24_48MHz Active/Inactive PCI_F Active/Inactive AGP2 Active/Inactive AGP1 Active/Inactive AGP0 Active/Inactive
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
10/18/00 Page
PLL202-54
Programmable Clock Generator Apollo Pro-266 with
BYTE Linear Programming Register (1=Enable, 0=Disable)
Pin#
Default
Description
Linear programming sign "+", Linear programming magnitude (MSB) Linear programming magnitude Linear programming magnitude Linear programming magnitude Linear programming magnitude Linear programming magnitude Linear programming magnitude (LSB)
BYTE Register (1=Enable, 0=Disable)
Pin#
Default
Description
Inverted power latched VID4 (Read only, selectable Byte9.bit2) Fall-back Frequency (Write only) VID4 APIC1 APIC0 VID3 VID2 VID1 VID0
BYTE Reserved Register (For external buffer)
Pin#
Default
Description
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
10/18/00 Page
PLL202-54
Programmable Clock Generator Apollo Pro-266 with
BYTE Reserved Register (For external buffer)
Pin#
Default
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Description
BYTE Watchdog Timer Revision Vendor Register (1=Enable, 0=Disable)
Pin#
Default
Description
Watchdog Timer Enable Bit. 1=Enable, 0=Disable Enable, Enable, Disable Watchdog Time Interval (MSB) Watchdog Time Interval Watchdog Time Interval Watchdog Time Interval Watchdog Time Interval Watchdog Time Interval (LSB) Revision Revision Vendor Vendor Vendor Vendor
Note: Default value power-up. Don't write into this register, writing into this register cause malfunction.
BYTE Reserved (1=Enable, 0=Disable)
Pin#
Default
Reserved Reserved Reserved Reserved Reserved
Description
Select power-up latched input value Frequency Select, Status (Read Only) Status (Read Only)
Note: Default value power-up. Don't write into this register, writing into this register cause malfunction.
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
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PLL202-54
Programmable Clock Generator Apollo Pro-266 with
APPLICATION DIAGRAM OUTPUTS
Internal
External circuitry
(0:4)
(0=GND, 1=open)
I2C: Byte
VID4 VID3 VID2 VID1 VID0
(0:4)
120k
VIDENB
FUNCTIONAL DESCRIPTION
Introduction PLL202-54 provides five VID(0:4) output pins that permit chip override data sent after start-up. order reset default conditions, chip also offers VIDENB (VID enable) pin. user configurable values VID(0:4) bits buffered PLL202-54 using I2C. Moreover, enable also controlled through (see application diagram). Upon power-up, default bits sent depicted application diagram, VID(0:4) output pins enabled disabled AND-gate controlled VIDENB input ENB-bit internal VID-byte. VIDENB input internal pull-up 120k, resulting default high value, unless overridden external circuitry. contrary, upon power-up, ENB-bit defaulted `0'. result, AND-gate goes `low' output buffers disabled, setting them high impedance. This permits default bits sent PWM. Meanwhile, time after power-up, user write modify internal VID-byte. Enabling override data PLL202-54 Once internal VID-bits have been written with I2C, user enable output buffers writing ENB-bit. This will AND-gate `high' enable output buffers. Depending internal VID-bit values, this will either result very impedance between output (VIDn very
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
10/18/00 Page
PLL202-54
Programmable Clock Generator Apollo Pro-266 with
impedance between output (VIDn case, comparison with this very small impedance, external resistor will seen high impedance, thus permitting PLL202-54 outputs override VID-bits CPU. Clearly, this only take place VIDENB input also high, that AND-gate `high'. Disabling override resetting original order reset default conditions, user offered possibilities anytime. Through I2C, user write internal ENB-bit. This will simply disable output buffers. high impedance output buffers will allow bits pass through resistor reset default values. Additionally, user also offered possibility directly change VIDENB input low, instead going through I2C. This will also AND-gate `low' disable output buffers, bringing about same results.
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
10/18/00 Page
PLL202-54
Programmable Clock Generator Apollo Pro-266 with
PROGRAMMING FREQUENCY simplify traditional loop counter setting, PLL202-54 device incorporates SMART-BYTE technology with single byte programming better optimize clock jitter spread spectrum performance. Detail PLL202-54's dual mode frequency programming method described below: ROM-table Frequency Programming: pre-defined frequencies found Frequency table accessed either through external jumpers setting internal register BYTE0. Fine-step Linear Frequency Programming: Frequency programmed fine linear positive negative stepping around current selected frequency Frequency table. highest step either +127 -127. Other frequencies will changed proportionally with rate that frequency change. formula follow:
CPU-ROM-table (=0.22, 0.15 0.11)
Where: magnitude factor defined Byte4.bit (0:6) (sign bit) defined Byte4.bit constant related CPU's three Timing groups definition 0.11 (for Group 0.15 (for Group 0.22 (for Group
FREQUENCY PROGRAMMING EXAMPLE: Procedures program target frequency 122.0 Group timing:
Locate closest frequency from Frequency from Frequency-ROM table: 118.0 0.15 Group Solve (Linear Magnitude factor) integer: CPU-ROMTABLE (122 118) 0.15 Program register:
Setting I2C.BYTE0 Setting I2C.BYTE4
Sign
118.0 (0.15) 122.05 frequency increased 0.04% 78.6 0.04%) 78.63
39.3 0.04%) 39.32
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
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PLL202-54
Programmable Clock Generator Apollo Pro-266 with
BUILT-IN WATCHDOG TIMER (WDT) Watchdog timer used perform safe recovery frequency switching causes system enter into "Hang-up" state within reasonable period time Watchdog time interval). watchdog time interval programmed between seconds with increment second setting value I2C.Byte8.Bit(5:0). Once Enabled, disabled within period that shorter than programmed watchdog interval; otherwise will generate 500ms watchdog reset pulse provoke system reset. After system restarts, PLL202-54 will start from predefined Fall-back Frequency (the value Byte1.Bit(4,6,7), Byte3.Bit7, Byte5.Bit7). system reason fails again Fall-back Frequency, internal hardware will then generate watchdog reset restart system from value external hardware jumper setting ensure safe recovery. Example usage: System power-up CPU= 66.8MHz (Group where external jumpers used. Switch target CPU=100.2MHz frequency (Group with following register setting:
FSEL
Setting I2C.BYTE0
Setting I2C.BYTE7
Sign
WD-Timer Setting I2C.BYTE8
FBSEL
Setting I2C.BYTE1,
fall-back frequency same location that FSEL since frequency switching between different timing groups will cause system hang After timer expired seconds, system will restart properly target 100.2MHz capable; otherwise will perform another reset action restart system from 66.8 Switch target CPU=79MHz within same timing Group fall-back frequency recommended most safe comfortable level ensure successful reboot such 75.0 system unable switch 79Mhz.
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
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PLL202-54
Programmable Clock Generator Apollo Pro-266 with
OPERATIONAL FLOW CHART START Register Loading: Fall-Back, WD-TIMER, WD-ENABLE Register Loading: FSEL
Disable WDEnable Target Setting
SUCCESS
Wait System Response
Copy Fall-Back Frequency Setting Frequency Setting Disable WDEnable Fall-Back Frequency Setting
FAIL After specified WD-Timer Expired
SUCCESS
System Restart Fall-back Frequency
FAIL After specified WD-Timer Expired
System Restart Jumper-Setting Frequency
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
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PLL202-54
Programmable Clock Generator Apollo Pro-266 with
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings PARAMETERS
Supply Voltage Input Voltage, Output Voltage, Storage Temperature Ambient Operating Temperature Junction Temperature Voltage
SYMBOL
MIN.
MAX.
UNITS
Exposure device under conditions beyond limits specified Maximum Ratings extended periods cause permanent damage device affect product reliability. These conditions represent stress rating only, functional operations device these other conditions above operational limits noted this specification implied.
DC/AC Electrical Specifications PARAMETERS
Input High Voltage Input Voltage Input High Current Input Current Input Current
SYMBOL
CONDITIONS
Inputs except inputs except with pull-up resistor with pull-up resistor pF@66MHz, 3.3V±5% pF@133MHz, 3.3V±5% pF@66MHz, 2.5V±5% pF@133MHz, 2.5V±5% crossing target Freq. 6,7,21,22,47 3.3V Logic Inputs XOUT pins
MIN.
-0.3
TYP.
MAX.
+0.3
UNITS
-200 14.318
Supply Current
Transition Time Pull-up resistor Input frequency Input Capacitance
trans
kohm
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PLL202-54
Programmable Clock Generator Apollo Pro-266 with
DC/AC Electrical Specifications (continued)
Unless otherwise stated, power supplies 3.3V±5%, ambient temperature range 70°C
PARAMETERS
SYMBOL
OUTPUTS
CONDITIONS
Measured 0.4V 2.0V, =10-20pf, 2.5V±5% Measured 0.4V 2.4V, =10-20pf Measured 0.4V 2.4V, =10-30pf Measured 0.4V, =10-20pf, 2.5V±5% Measured 2.4V 0.4V, =10-20pf Measured 2.4V 0.4V, =10-30pf Measured 1.5V =20pf Measured 1.5V, =20~30pf Rising edge 1.25V, =20pf Rising edge 1.5V, =30pf Rising edge 1.5V, =30pf Measured 1.25V Measured 1.5V Assumes full supply voltage reached within from power-up. Short cycle exist prior frequency stabilization. =3.3V(2.5V)±5% =3.3V±5% =3.3V±5%
MIN.
TYP.
MAX.
UNITS
Output Rise time
REF, 48MHz, 24MHz PCI_F, PCI, AGP, APIC
Output Fall time
REF, 48MHz, 24MHz PCI_F, PCI, AGP, APIC CPU,APIC,REF, 48MHz,24MHz PCI,
Duty Cycle
Clock Skew
SKEW
Jitter(Cycle Cycle)
cyc-cyc
PCI, CPU,PCI_F,PCI, APIC,AGP,REF, 48MHz,24MHz
Frequency Stabilization Time
output impedance
PCI,AGP REF,48MHz,24MHz
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
10/18/00 Page
PLL202-54
Programmable Clock Generator Apollo Pro-266 with
PACKAGE INFORMATION
0.395 0.420 10.033 10.668
0.291 0.299 7.391 7.595
0.008 0.0135 0.203 0.343
0.025 0.635
0.015 (0.381) 0.010 0.016 (0.254 0.406) 0.720 0.730 (18.288 18.542)
0.087 0.094 (2.210 2.388)
0.095 0.110 (2.413 2.794) 30-6 0.050 (1.270) 0.008 0.016 (0.203 0.406)
56PIN SSOP
ORDERING INFORMATION
part ordering, please contact Sales Department:
47745 Fremont Blvd., Fremont, 94538, Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
order number this device combination following: Device number, Package type Operating temperature range
PLL202-54
PART NUMBER TEMPERATURATURE C=COMMERCIAL M=MILITARY I=INDUSTRAL PACKAGE TYPE X=SSOP
PhaseLink Corporation, reserves right make changes products specifications, both time without notice. information furnished Phaselink believed accurate reliable. However, PhaseLink makes guarantee warranty concerning accuracy said information shall responsible loss damage whatever nature resulting from reliance upon this product. LIFE SUPPORT POLICY: PhaseLink's products authorized critical components life support devices systems without express written approval President PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
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Programmable Clock Generator Apollo Pro-266 with Generates clock

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