Motherboard Clock Generator SIS540/630 with 133MHz Generates cloc
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PLL202-13
Motherboard Clock Generator SIS540/630 with 133MHz
Generates clock frequencies SIS540, SIS630 Pentium chip sets, requiring multiple clocks high speed SDRAM buffers. Support clocks, 7PCI high-speed SDRAM buffers 3-DIMM applications. selectable 48MHz clock output (default MHz). clock output. Two14.318MHz reference clocks. Support 2-wire serial interface with builtin Vendor Device Revision Single byte micro-step linear Frequency Programming with Glitch free smooth switching. Built-in programmable watch timer seconds with 1-second interval. will generate reset output when timer expired. Spread Spectrum ±0.25% center -0.5% down. duty cycle with jitter. Available SSOP.
CONFIGURATION
VDD0 REF0/FS3*v GNDREF XOUT VDD1 PCI0/FS1* PCI1/FS2* PCI2 PCI3 PCI4 PCI5 PCI6 VDD2 SDRAM0 SDRAM1 VDD3 SDRAM2 SDRAM3 SDATA SCLK
WDRESET# VDDL1 CPU0 CPU1 CPU2 VDD3 SDRAM13 SDRAM12 SDRAM11 SDRAM10 VDD3 SDRAM9 SDRAM8 SDRAM7 SDRAM6 VDD3 SDRAM5 SDRAM4 VDD4 48MHz/FS0* 24_48MHz/CPU2.5_3.3*v
Note: Pull down, Active Bi-directional latched power-up
BLOCK DIAGRAM
VDD1 XTAL REF(0:1)
POWER GROUP
VDD0: CORE VDD1: REF0, XIN, XOUT VDD2: PCI(0:6) VDD3: SDRAM(0:13) VDD4: 48MHz, 24_48MHz VDDL1: CPU(0:2)
PLL202-13
XOUT
VDDL2 (0:3)* CPU(0:2) VDD3 SDRAM(0:13) VDD2 PCI(0:6) VDD4 48Mhz PLL2
PLL1
Control Logic
SPECIFICATIONS
Cycle Cycle jitter: 250ps. output skew: 500ps. SDRAM output skew: 500ps. output skew: 250ps. SDRAM SDRAM output skew: 250ps. skew (CPU leads):
SDATA SCLK Logic Watch
24_48Mhz WDRESET
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
02/15/00 Page
PLL202-13
Motherboard Clock Generator SIS540/630 with 133MHz
DESCRIPTIONS
Name
VDD0 VDD1 VDD2 VDD3 VDD4 VDDL1 XOUT REF0/FS3* PCI0/FS1* PCI1/FS2* 48MHz/FS0* (0:6) (0:2) SDRAM (0:13) SDATA SCLK 48MHz 24_48MHz/ CPU2.5_3.3*
Number
19,30,36,42 3,10,16,22, 33,39,44 2,7,8,26 7,8,9,11,12, 13,14 46,45,43 17,18,20,21,28, 29,31,32,34,35, 37,38,40,41
Type
Power supply Core.
Description
Power supply REF0, REF1, crystal oscillator. Power supply (0:6). Power supply SDRAM (0:13). Power supply 24_48MHz 48MHz. Power supply (0:2) 2.5V. Ground. 14.318MHz crystal input connected crystal. 14.318MHz crystal output. power these pins input pins will determine clock frequency. After input sampling, these pins will generate output clocks. They have internal pull down (low default). clocks with frequencies defined Frequency Table. clocks with frequencies defined Frequency Table. SDRAM clocks with frequencies defined Frequency Table.
Serial data input serial interface port. 48MHz output after input data latched during power-up. Clock output SUPER after input data latched during power-up. programmed setting byte1.bit7 select either 24Mhz (default) 48Mhz. CPU2.5_3.3 input will program internal skew circuits based voltage. high, selects 2.5V. Low, selects 3.3V (default). This open drain output. will watchdog timer expiration. Buffered reference clock after input data latched during power-up.
WDRESET# REF0
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
02/15/00 Page
PLL202-13
Motherboard Clock Generator SIS540/630 with 133MHz
FREQUENCY (MHz) SELECTION TABLE
Byte0 bit7
66.6 100.0 150.0 133.3 66.8 100.0 100.0 133.3 66.8 97.0 68.0 95.0 95.0 112.0 166.0 96.2 66.8 100.2 97.0 100.2 75.0 83.3 105.0 133.6 110.2 115.0 120.0 138.0 140.0 145.0 147.6 160.0
SDRAM
100.0 100.0 100.0 100.0 133.6 133.3 150.0 133.3 66.8 97.0 113.3 95.0 126.7 112.0 111.0 96.2 100.2 100.2 97.0 133.6 100.0 125.0 140.0 133.6 147.0 153.4 120.0 138.0 140.0 145.0 147.6 160.0
33.3 33.3 37.6 33.3 33.4 33.3 37.6 33.3 33.4 32.3 28.3 31.6 31.6 37.3 27.6 32.1 33.4 33.4 32.3 33.4 37.5 31.2 35.0 33.4 36.7 38.3 30.0 34.5 35.0 36.2 36.9 26.6
Spread Spectrum Modulation
-0.5% -0.5% ±0.25% -0.5% ±0.25% -0.5% ±0.25% -0.5% ±0.25% -0.5% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% -0.5% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25%
default
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
02/15/00 Page
PLL202-13
Motherboard Clock Generator SIS540/630 with 133MHz
FREQUENCY (MHz) SELECTION TABLE TIMING GROUP
Group Timing
(CPU:SDRAM)
Byte0 bit7
66.8 95.0 96.2 97.0 97.0 100.0 100.2 112.0 120.0 133.3 133.6 138.0 140.0 145.0 147.6 160.0 150.0 166.0 66.6 66.8 83.3 100.0 133.3 66.8 75.0 95.0 100.0 100.2 105.0 110.2 115.0 68.0
SDRAM
66.8 95.0 96.2 97.0 97.0 100.0 100.2 112.0 120.0 133.3 133.6 138.0 140.0 145.0 147.6 160.0 100.0 111.0 100.0 100.2 125.0 150.0 100.0 133.6 100.0 126.7 133.3 133.6 140.0 147.0 153.4 113.3
33.4 31.6 32.1 32.3 32.3 33.3 33.4 37.3 30.0 33.3 33.4 34.5 35.0 36.2 36.9 26.6 37.6 27.6 33.3 33.4 31.2 37.6 33.3 33.4 37.5 31.6 33.3 33.4 35.0 36.7 38.3 28.3
Spread Spectrum Modulation
±0.25% ±0.25% -0.5% -0.5% ±0.25% -0.5% ±0.25% ±0.25% ±0.25% -0.5% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25% -0.5% ±0.25% ±0.25% ±0.25% -0.5% ±0.25% ±0.25% ±0.25% -0.5% ±0.25% ±0.25% ±0.25% ±0.25% ±0.25%
(2:2)
(2:3) (3:2) (3:4) (4:2)
(4:3)
(5:3)
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
02/15/00 Page
PLL202-13
Motherboard Clock Generator SIS540/630 with 133MHz
CONFIGURATION SETTING
Address Assignment Slave Receiver/Transmitter Data Transfer Rate
Provides both slave write readback functionality Standard mode 100kbits/s serial bits will read sent clock driver following order Byte Bits Byte Bits Byte Bits This serial protocol designed allow both blocks write read from controller. bytes must accessed sequential order from lowest highest byte. Each byte transferred must followed acknowledge bit. byte transferred without acknowledged will terminate transfer. write read block both begins with master sending slave address write condition (0xD2) read condition (0xD3). Following acknowledge this address byte, Write Mode: Command Byte Byte Count Byte must sent master ignored slave, Read Mode: Byte Count Byte will read master then other Data Byte.
Serial Bits Reading
Data Protocol
CONTROL REGISTERS
BYTE Functional Frequency Select Clock Register (1=Enable, 0=Disable)
Pin#
Default
Description
Frequency selection Table Frequency selection Table Frequency selection Table Frequency selection Table Frequency selection control 1=Via I2C, 0=Via External jumper Frequency selection Table 0=Normal 1=Spread Spectrum enable 0=Normal 1=Tristate Mode outputs
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
02/15/00 Page
PLL202-13
Motherboard Clock Generator SIS540/630 with 133MHz
BYTE Clock Register (1=Enable, 0=Disable)
Pin#
Default
Description
Select 24_48MHZ output. 0=48Mhz, 1=24Mhz Reserved Reserved Reserved CPU2 Active/Inactive CPU1 Active/Inactive CPU0 Active/Inactive Reserved
BYTE Clock Register (1=Enable, 0=Disable)
Pin#
Default
Description
Inverted power latched CPU2.5_3.3 value (Read-back only) PCI6 Active/Inactive PCI5 Active/Inactive PCI4 Active/Inactive PCI3 Active/Inactive PCI2 Active/Inactive PCI1 Active/Inactive PCI0 Active/Inactive
BYTE SDRAM Clock Register (1=Enable, 0=Disable)
Pin#
Default
Description
SDRAM7 Active/Inactive SDRAM6 Active/Inactive SDRAM5 Active/Inactive SDRAM4 Active/Inactive SDRAM3 Active/Inactive SDRAM2 Active/Inactive SDRAM1 Active/Inactive SDRAM0 Active/Inactive
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
02/15/00 Page
PLL202-13
Motherboard Clock Generator SIS540/630 with 133MHz
BYTE Reserved Clock Register (1=Enable, 0=Disable)
Pin#
Default
Description
24_48MHz (Active/Inactive) 48MHz (Active/Inactive) SDRAM13 (Active/Inactive) SDRAM12 (Active/Inactive) SDRAM11 (Active/Inactive) SDRAM10 (Active/Inactive) SDRAM9 (Active/Inactive) SDRAM8 (Active/Inactive)
BYTE Peripheral Clock Register (1=Enable, 0=Disable)
Pin#
Default
Description
Reserved Reserved Inverted power latched value (Read-back only) Inverted power latched value (Read-back only) Inverted power latched value (Read-back only) Inverted power latched value (Read-back only) REF1 Active/Inactive REF0 Active/Inactive
BYTE Fall-Back Frequency Revision Vendor Register (1=Enable, 0=Disable)
Pin#
Default
Description
Fall-back Frequency selection Fall-back Frequency selection Fall-back Frequency selection Fall-back Frequency selection Fall-back Frequency selection Vendor Vendor Vendor Revision Revision Revision Revision Vendor
Note: Default value power-up
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
02/15/00 Page
PLL202-13
Motherboard Clock Generator SIS540/630 with 133MHz
BYTE Linear Programming Register (1=Enable, 0=Disable)
Pin#
Default
Description
Linear programming sign "+", Linear programming magnitude (MSB) Linear programming magnitude Linear programming magnitude Linear programming magnitude Linear programming magnitude Linear programming magnitude Linear programming magnitude (LSB)
Note: This register will initialized following WATCHDOG RESET.
BYTE WATCHDOG TIMER Device Register (1=Enable, 0=Disable)
Pin#
Default
Device
Description
Watchdog Timer Enable Bit. 1=Enable, 0=Disable Watchdog Time Interval (MSB) Watchdog Time Interval Watchdog Time Interval Watchdog Time Interval Watchdog Time Interval Watchdog Time Interval (LSB) Device Device Device Device Device Device
Note: Default value power-up
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
02/15/00 Page
PLL202-13
Motherboard Clock Generator SIS540/630 with 133MHz
PROGRAMMING FREQUENCY simplify traditional loop counter setting, PLL202-13 device incorporates SMART-BYTE technology with single byte programming better optimize clock jitter spread spectrum performance. Detail PLL202-13's dual mode frequency programming method described below: ROM-table Frequency Programming: pre-defined frequencies found Frequency table accessed either through external jumpers setting internal register BYTE0. Micro-step Linear Frequency Programming: Frequency programmed fine linear positive negative stepping around selected frequency Frequency table. highest step either +127 -127. Other frequencies will changed proportionally with rate that frequency change. formula follow:
CPU.ROM-Table (=0.22, 0.15, 0.11 0.09)
Where: magnitude factor defined Byte 7.bit(0:6) (sign bit) defined Byte7.bit constant related CPU's seven Timing groups definition 0.22 (for Group 0.15 (for Group C,D) 0.11 (for Group 0.09 (for Group
FREQUENCY PROGRAMMING EXAMPLE: Procedures program target frequency 139.0 Group timing:
Locate closest frequency from Frequency-ROM table: 133.6 0.22 Group Solve (Linear Magnitude factor) integer: ROMTABLE (139 133.6) 0.22 Program register:
Setting I2C.BYTE0 Setting I2C.BYTE7
Sign
133.6 (0.22) 139.1 frequency increased SDRAM 133.6 (1+4.1%) 139.1 33.4 (1+4.1%) 34.7
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 02/15/00 Page
PLL202-13
Motherboard Clock Generator SIS540/630 with 133MHz
BUILT-IN WATCHDOG TIMER (WDT) Watchdog timer used perform safe recovery frequency switching causes system enter into "Hang-up" state within reasonable period time Watchdog time interval). watchdog time interval programmed between seconds with increment second setting value I2C.Byte8.Bit(5:0). Once Enabled, disabled within period that shorter than programmed watchdog interval; otherwise will generate 500ms watchdog reset pulse provoke system reset. After system restarts, PLL202-13 will start from predefined Fall-back Frequency (the value Byte6,bits(7:3)). system reason fails again Fall-back Frequency, internal hardware will then generate watchdog reset restart system from value external hardware jumper setting ensure safe recovery. Example usage: System power-up CPU= 66.8MHz (Group where external jumpers used. Switch target CPU=100.0MHz frequency (Group with following register setting:
FSEL
Setting I2C.BYTE0
Setting I2C.BYTE7
Sign
WD-Timer Setting I2C.BYTE8
FBSEL
Setting I2C.BYTE6
fall-back frequency same location that FSEL since frequency switching between different timing groups will cause system hang After timer expired seconds, system will restart properly target 100.0MHz capable; otherwise will perform another reset action restart system from 66.8 Switch target CPU=98Mhz within same timing Group fall-back frequency recommended most safe comfortable level ensure successful reboot such system unable switch 98Mhz.
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
02/15/00 Page
PLL202-13
Motherboard Clock Generator SIS540/630 with 133MHz
OPERATIONAL FLOW CHART START Register Loading: Fall-Back, WD-TIMER, WD-ENABLE Register Loading: FSEL
Disable WDEnable Target Setting
SUCCESS
Wait System Response
Copy Fall-Back Frequency Setting Frequency Setting Disable WDEnable Fall-Back Frequency Setting
FAIL After specified WD-Timer Expired
SUCCESS
System Restart Fall-back Frequency
FAIL After specified WD-Timer Expired
System Restart Jumper-Setting Frequency
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
02/15/00 Page
PLL202-13
Motherboard Clock Generator SIS540/630 with 133MHz
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings PARAMETERS
Supply Voltage Input Voltage, Output Voltage, Storage Temperature Ambient Operating Temperature Junction Temperature Voltage
SYMBOL
MIN.
MAX.
UNITS
Exposure device under conditions beyond limits specified Maximum Ratings extended periods cause permanent damage device affect product reliability. These conditions represent stress rating only, functional operations device these other conditions above operational limits noted this specification implied.
AC/DC Electrical Specifications PARAMETERS
Input High Voltage Input Voltage Input High Current Input Current Pull-down resistor Input frequency Input Capacitance
SYMBOL
CONDITIONS
Inputs except inputs except Logic inputs with internal pull-down resistors 2,7,8,25,26 3.3V Logic Inputs XOUT pins
MIN.
-0.3
TYP.
MAX.
+0.3
UNITS
Kohm
14.318
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
02/15/00 Page
PLL202-13
Motherboard Clock Generator SIS540/630 with 133MHz
Output Buffer Electrical Specifications
Unless otherwise stated, power supplies 3.3V±5%, ambient temperature range 70°C
PARAMETERS
SYMBOL
OUTPUTS
CONDITIONS
Measured 0.4V 2.4V, =10-20pf, 3.3V±5% Measured 0.4V 2.4V, =10-20pf Measured 0.4V 2.4V, =10-30pf Measured 0.4V 2.4V, =10-30pf, 3.3V±5% Measured 2.4V 0.4V, =10-20pf, 3.3V±5% Measured 2.4V 0.4V, =10-20pf Measured 2.4V 0.4V, =10-30pf Measured 2.4V 0.4V, =10-30pf, 3.3V±5% Measured 1.5V =20pf, =2.5V
MIN.
TYP.
MAX.
UNITS
REF0, REF1 Output Rise time SDRAM, 24_48MHz REF0, REF1 Output Fall time SDRAM, 24_48MHz Duty Cycle CPU, 24_48MHz, 48MHz, REF, PCI, SDRAM SDRAM SDRAM Clock Skew SKEW SDRAM SDRAM SDRAM Output Impedance REF0, PCI, 48Mhz, 24_48Mhz SDRAM REF1
V/ns
V/ns
Measured 1.5V, equal loads
=3.3V(2.5V)±5%
=3.3V±5%
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
02/15/00 Page
PLL202-13
Motherboard Clock Generator SIS540/630 with 133MHz
Output Buffer Electrical Specifications, continued
Unless otherwise stated, power supplies 3.3V±5%, ambient temperature range 70°C
PARAMETERS
SYMBOL
OUTPUTS
CPU(0:2) SDRAM(0:13)
CONDITIONS
1.25V =2.5V±5%)
MIN.
TYP.
MAX.
UNITS
Output High Current
PCI(0:6) REF0 REF1 24_48MHz CPU(0:2) SDRAM(0:13) 1.25V =2.5V±5%) 1.5V
Output Current
PCI(0:6) REF0 REF1 24_48MHz Measured 1.25V Measured 1.5V Measured 1.25V Measured 1.5V Measured 1.25V Measured 1.5V Measured 1.5V 1.5V
Jitter, Sigma
sigma
REF,48MHz,24MHz
Jitter, Absolute
REF,48MHz,24MHz
Jitter (cycle cycle)
cyc-cyc
SDRAM
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
02/15/00 Page
PLL202-13
Motherboard Clock Generator SIS540/630 with 133MHz
PACKAGE INFORMATION
0.400 0.410 10.160 10.414
0.292 0.299 7.417 7.959
0.008 0.0135 0.203 0.343
0.025 0.835
0.015 (0.381) 0.010 0.016 (0.25 0.41) 0.620 0.630 (15.75 16.00)
0.088 0.096 (2.250 2.450)
0.097 0.104 (2.467 2.642) 30-6 0.050 (1.346) 0.008 0.016 (0.20 0.41)
48PIN SSOP
ORDERING INFORMATION
part ordering, please contact Sales Department:
47745 Fremont Blvd., Fremont, 94538, Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
order number this device combination following: Device number, Package type Operating temperature range
PLL202-13
PART NUMBER TEMPERATURATURE C=COMMERCIAL M=MILITARY I=INDUSTRAL PACKAGE TYPE X=SSOP
PhaseLink Corporation, reserves right make changes products specifications, both time without notice. information furnished PhaseLink believed accurate reliable. However, PhaseLink makes guarantee warranty concerning accuracy said information shall responsible loss damage whatever nature resulting from reliance upon this product. LIFE SUPPORT POLICY: PhaseLink's products authorized critical components life support devices systems without express written approval President PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
02/15/00 Page
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