Programmable Clock Generator 1681 Chip Sets Supports 1681 Pentium
|
|
|
Top Searches for this datasheet
PLL202-108
Programmable Clock Generator 1681 Chip Sets
Supports 1681 Pentium Chipsets. Programmable Spread Spectrum Modulation from ±0.1% ±1.5% with step size small ±0.012%. Selectable Spread Spectrum either center down. Selectable Spread Spectrum modulation profile. AccuSkew Programmable Precision skew tuning channel with maximum precision over variation temperature, process voltage with step size small 80ps. AccuDrive Programmable Output Buffer drive strength with +50% -40%. Programmable frequency with variable Programmable Output Divider CPU, HTT, PCI. differential CPUCLK CLK, AGP, PCI, clock outputs. programmable 24MHz 48MHz SIO. Support 2-wire serial interface. Built-in programmable watchdog timer Available SSOP.
CONFIGURATION
VDDREF XOUT VSSREF REF0/FS2*V REF1/FS0*V PCI8//PCISTOP#^ PCI7/FS1*V PCI6/MULTSEL*V VSSPCI VDDPCI PCI5/HTTSEL*^ PCI4 PCI3 PCI2 VDDPCI VSSPCI PCI1 PCI0 PCIF/SEL24_48#*^ VSS48M 48MHZ/FS3*V 24_48MHz/MODE*^ VDD48M SCLK SDATA WDRESET# CPUCTP#^/Vtt_pwrgd CPUT0 CPUC0 VDDCPU VSSCPU CPUT1 CPUC1 IREF AVSS AVDD PD#^ HTTT0 HTTC0 VDDHTT VSSHTT HTTT1 HTTC1 VDDAGP AGP0 AGP1 VSSAGP
PLL202-108
Note:
Pull (120k),
Pull down (120k), Active low,
Bi-directional latched power-up
BLOCK DIAGRAM
REF(0:1) VDDCPU CPUT (0:1) CPUC (0:1) VDDHTT HTTT (0:1) HTTC (0:1) (0:1) (0:8) PCIF 48Mhz PLL2 SDATA SCLK Logic Watch 24_48Mhz WDRESET#
POWER GROUP
VDDREF (3.3V), VSSREF: REF, XIN, XOUT VDDPCI (3.3V), VSSPCI: VDDAGP (3.3V), VSSAGP: VDD48M (3.3V), VSS48M: 48MHz, 24_48MHz VDDCPU (3.3V), VSSCPU: CPUT/C[0:1] VDDHTT (3.3V), VSSHTT: HTTT/C[0:1] AVDD (3.3V), AVSS: Analog
XOUT CPUSTP# PCISTP# MULTSEL HTTSEL FS(0:3)
XTAL
PLL1
Control Logic
SPECIFICATIONS
Output Skew 150ps. Output Skew 150ps Output Skew 500ps (early) Skew: (typ 2ns). (early) Skew: (typ 2ns). Skew 150ps. Skew 150ps. outputs cycle cycle jitter 150ps. outputs cycle cycle jitter 250ps. outputs cycle cycle jitter 250ps. 48MHz outputs cycle cycle jitter 350ps.
8/20/02 Page
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
PLL202-108
Programmable Clock Generator 1681 Chip Sets
DESCRIPTIONS
Name
XOUT REF[0:1]/FS[0,2] CPUSTP#/Vtt_Pwrgd
Number
Type
Description
14.318Mhz crystal input connected crystal 14.318Mhz crystal output 14.318Mhz Reference clock output. This latch FS[0,2] value powerup. (See Frequency Selection table). internal pull down resistor. power-up, this input Vtt_PWRGD After first high low, this acts CPU_STOP disable clock outputs including when Low. When Vtt_PWRGD input high, (0:3), MULTSEL, HTTSEL MODE inputs latched outputs enabled. 120K internal pull resistor. clock output (see Frequency table). Differential pair output Hyper Transport output clocks Watch reset signal will generated after watchdog timer expires Enable (Byte9.bit7) active clock output (see Frequency table). This latches HTTSEL value power-up. After power-up, this acts clock output. HTTSEL used select current multiplier outputs. HTTSEL=0, IOH=8XIREF. HTTSEL=1, IOH=9XIREF. internal pull-up resistor. This latches MULTSEL value power-up. After power-up, this acts clock output. MULTSEL used select current multiplier outputs. MULTSEL=0, IOH=6XIREF. MULTSEL=1, IOH=7XIREF. internal pull-down resistor. Bi-directional pin. power-up, input value latched. After powerup, this acts PCI7 output. internal pull-down resistor. When MODE=1 (pin23), this acts PCI_STOP input stop clock outputs except PCIF when low. When MODE low, this will acts clock output. 120K internal pull resistor. This latches SEL24_48 value power After power-up, this acts PCIF clock output. SEL24_48=1, select 24Mhz. SEL24_48=0 select 48Mhz. 120K internal pull resistor. Differential pair output Host. Differential pair output Chip Sets. This latches MODE value power-up. After power-up, this acts 24_48MHz clock output with default 24MHz selection I2C. MODE function select mobile desktop mode 120K internal pull resistor.
AGP[0:1] HTT[C/T]_[0:1] WDRESET PCI[0:4] PCI5/HTTSEL
26,27 29,30, 33,34 13,14,15, 18,19
PCI6/MULTSEL
PCI7/FS1 PCI8//PCI_STOP#
PCIF/SEL24_48#
CPU[C/T]_0 CPU[C/T]_1 24_48MHz/MODE
39,40 43,44
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
8/20/02 Page
PLL202-108
Programmable Clock Generator 1681 Chip Sets
DESCRIPTIONS (Continue)
Name
48MHz/FS3 Iref
Number
Type
Description
power-up, input value latched. After power-up, this acts output. internal pull-down resistor. This establishes reference current differential pairs, requires fixed precision resistor tied ground order establish appropriate current. Serial data inputs serial interface port. Serial data inputs serial interface port. 3.3V Power Supply PCIF, PCI[0:8] clock 3.3V Power Supply clock. 3.3V Power Supply clock. 3.3V Power Supply 48MHz 24_48MHz clock 3.3V power internal PLL. 3.3v power supply CPU[T,C]_[0:1] clocks. 3.3v power supply REF[0:2] clocks Ground.
SDATA SCLK VDDPCI VDDAGP VDDHTT VDD48M AVDD VDDCPU VDDREF
11,16 4,10,17,21,2 5,31,37,41,
HOST SWING SELECT FUNCTIONS
MULTISEL0 Board Target Trace/Term Reference (Rr) VDD/(3*Rr) 221; Iref 5.0mA 475; Iref 2.32 Output Current 6*IREF 7*IREF 1.0V 0.7V
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
8/20/02 Page
PLL202-108
Programmable Clock Generator 1681 Chip Sets
FREQUENCY (MHz) SELECTION TABLE
100.00 133.33 200.00 166.67 66.67 90.00 105.00 165.00 101.00 134.67 202.00 168.33 103.00 137.33 206.00 171.67 105.00 140.00 210.00 175.00 107.00 142.67 214.00 178.35 110.00 146.67 220.00 183.35 113.00 150.67 226.00 188.35
66.67 66.67 66.67 66.67 66.67 60.00 70.00 55.00 67.33 67.33 67.33 67.33 68.67 68.67 68.67 68.67 70.00 70.00 70.00 70.00 71.33 71.33 71.33 71.34 73.33 73.33 73.33 73.34 75.33 75.33 75.33 75.34
33.33 33.33 33.33 33.33 33.33 30.00 35.00 27.50 33.67 33.67 33.67 33.67 34.33 34.33 34.33 34.33 35.00 35.00 35.00 35.00 35.67 35.67 35.67 35.67 36.67 36.67 36.67 36.67 37.67 37.67 37.67 37.67
33.33 33.33 33.33 33.33 33.33 30.00 35.00 27.50 33.67 33.67 33.67 33.67 34.33 34.33 34.33 34.33 35.00 35.00 35.00 35.00 35.67 35.67 35.67 35.67 36.67 36.67 36.67 36.67 37.67 37.67 37.67 37.67
Amplitude
-0.5% down -0.5% down -0.5% down -0.5% down ±0.3% center ±0.3% center ±0.3% center ±0.3% center ±0.3% center ±0.3% center ±0.3% center ±0.3% center ±0.3% center ±0.3% center ±0.3% center ±0.3% center ±0.3% center ±0.3% center ±0.3% center ±0.3% center ±0.3% center ±0.3% center ±0.3% center ±0.3% center ±0.3% center ±0.3% center ±0.3% center ±0.3% center ±0.3% center ±0.3% center ±0.3% center ±0.3% center
(CPU)
14,286 14,286 14,286 11,905 14,286 12,857 15,000 11,786 14,429 14,429 14,429 12,024 14,714 14,714 14,714 12,262 15,000 15,000 15,000 12,500 15,286 15,286 15,286 12,739 15,714 15,714 15,714 13,096 16,143 16,143 16,143 13,454
0.45 0.60 0.90 0.90 0.30 0.45 0.45 0.90 0.45 0.60 0.90 0.90 0.45 0.60 0.90 0.90 0.45 0.60 0.90 0.90 0.45 0.60 0.90 0.90 0.45 0.60 0.90 0.90 0.45 0.60 0.90 0.90
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
8/20/02 Page
PLL202-108
Programmable Clock Generator 1681 Chip Sets
CONFIGURATION SETTING
Address Assignment Slave Receiver/Transmitter Data Transfer Rate
Provides both slave write readback functionality Standard mode 100kbits/s This serial interface designed allow multiple protocols write read from controller. includes Block Read/Write, Block Index Read/Write, Byte Read/Write Word Read/Write. general, bytes must accessed sequential order from lowest highest byte. Each byte transferred must followed acknowledge bit. byte transferred without acknowledged will terminate transfer. write read block both begins with master sending slave address write condition (0xD2) read condition (0xD3).
Data Protocol
WRITE MODE
Block Write Address Command Byte count Data Byte Data Byte Data Data Byte
Block Index Write
Address
Command =(00~22)
Byte count
Data Byte
Data Byte
Data
Data Byte M+N-1
Byte Write
Address
Command =(00~22)+128
Data Byte
Word Write
Address
Command =(00~22)+128
Data Byte
Data Byte
READ MODE
Block Read Address Command Address Byte count Data Byte Data Byte Data Data Byte
Block Index Read
Address
Command =(00~22)
Address
Byte count
Data Byte
Data Byte
Data
Data Byte M+N-1
Byte Read
Address
Command =(00~22)+128
Address
Data Byte
Word Read
Address
Command =(00~22)+128
Address
Data Byte
Data Byte
Legend:
Start
Acknowledge Stop host
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
8/20/02 Page
PLL202-108
Programmable Clock Generator 1681 Chip Sets
CONTROL REGISTERS
BYTE Functional Frequency Select Clock Register (1=Enable, 0=Disable)
Pin#
Default
Power-up Latched FS3:FS0 value
Description
Frequency selection 1=Via I2C, 0=Via External jumper 0=normal, Spread Spectrum Enable (Reserved)
BYTE Control Register (1=Enable, 0=Disable)
Pin#
Default
Description
AGP1 (1=Active 0=Inactive) AGP0 (1=Active 0=Inactive) 24_48MHz (1=Active, 0=Inactive) 48MHz (1=Active, 0=Inactive) Inverted Power-up latched value (Read only) Inverted Power-up latched value (Read only) Inverted Power-up latched value (Read only) Inverted Power-up latched value (Read only)
BYTE Control Register (1=Enable, 0=Disable)
Pin#
43,44 39,40 33,34 29,30 43,44 39,40
Default
Description
CPU_STOP# setting CPU[C/T]_0 (0=Free Running, 1=Stopped) CPU_STOP# setting CPU[C/T]_1 (0=Free Running, 1=Stopped) CPU_STOP# setting AGP0 (0=Free Running, 1=Stopped) CPU_STOP# setting AGP1 (0=Free Running, 1=Stopped) CPU_STOP# setting HTT[C/T]_0 (0=Free Running, 1=Stopped) CPU_STOP# setting HTT[C/T]_1 (0=Free Running, 1=Stopped) CPU[C/T]_0 (1=Active 0=Inactive) CPU[C/T]_1 (1=Active 0=Inactive)
8/20/02 Page
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
PLL202-108
Programmable Clock Generator 1681 Chip Sets
BYTE Clock Register (1=Enable, 0=Disable)
Pin#
Default
Description
PCI_STOP# setting PCIF (0=Free Running, 1=Stopped) PCI_STOP# setting PCI0 (0=Free Running, 1=Stopped) PCI_STOP# setting PCI1 (0=Free Running, 1=Stopped) PCI_STOP# setting PCI2 (0=Free Running, 1=Stopped) PCI_STOP# setting PCI3 (0=Free Running, 1=Stopped) PCI_STOP# setting PCI4 (0=Free Running, 1=Stopped) PCI_STOP# setting PCI5 (0=Free Running, 1=Stopped) PCI_STOP# setting PCI6 (0=Free Running, 1=Stopped)
BYTE Vendor Revision Register
Pin#
Default
Description
PCIF (1=Active 0=Inactive) PCI0 (1=Active 0=Inactive) PCI1 (1=Active 0=Inactive) PCI2 (1=Active 0=Inactive) PCI3 (1=Active 0=Inactive) PCI4 (1=Active 0=Inactive) PCI5 (1=Active 0=Inactive) PCI6 (1=Active 0=Inactive)
BYTE Output Control Register
Pin#
33,34 29,30
Default
Description
PCI7 (1=Active 0=Inactive) PCI8 (1=Active 0=Inactive) HTT[C/T]0 (1=Active, 0=Inactive) HTT[C/T]1 (1=Active, 0=Inactive) (Reserved) (Reserved) REF1 (1=Active, 0=Inactive) REF0 (1=Active, 0=Inactive)
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
8/20/02 Page
PLL202-108
Programmable Clock Generator 1681 Chip Sets
BYTE Control Register (1=Enable, 0=Disable)
Pin#
Default
Description
Vendor (read only) Vendor (read only) Vendor (read only) Vendor (read only) Revision (read only) Revision (read only) Revision (read only) Revision (read only)
BYTE Linear Programming Register (1=Enable, 0=Disable)
Pin#
Default
Description
Linear programming sign "+", Linear programming magnitude (MSB) Linear programming magnitude Linear programming magnitude Linear programming magnitude Linear programming magnitude Linear programming magnitude Linear programming magnitude (LSB)
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
8/20/02 Page
PLL202-108
Programmable Clock Generator 1681 Chip Sets
BYTE WATCHDOG Fall Back Register (1=Enable, 0=Disable)
Pin#
Default
Description
Watchdog Timer Unit Bit[7:6]: 500ms, Initialization setting Linear Programming Byte after Watch reset. Byte initialized after WD-Reset generated. Byte unchanged after WD-Reset generated. Fall-back Frequency selection Fall-back Frequency selection Fall-back Frequency selection Fall-back Frequency selection Fall-back Frequency selection
BYTE WATCHDOG TIMER Register (1=Enable, 0=Disable)
Name
WDT<5> WDT<4> WDT<3> WDT<2> WDT<1> WDT<0>
Default
Description
Watchdog Timer Enable Bit. 1=Enable, 0=Disable 0=Watch falls back hardware jumper setting frequency 1=Watch falls back fall back frequency setting Byte Watchdog Time Interval (MSB) Watchdog Time Interval Watchdog Time Interval Watchdog Time Interval Watchdog Time Interval Watchdog Time Interval (LSB)
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
8/20/02 Page
PLL202-108
Programmable Clock Generator 1681 Chip Sets
BYTE Programming Mode Counter Register (1=Enable, 0=Disable)
Name
AccuSkew Enable
Default
Description
AccuSkew Setting process independent accuracy. 1=enable, 0=disable. Initialization setting Skew Control Buffer drive strength registers after Watch reset. Byte 12~17 initialized after WD-Reset generated. Byte 12~17 unchanged after WD-Reset generated. Watch Timer Status info (read only) linear, non-linear Accu-SST programming Enable: Byte11, setting Enable Skew programming (byte12~14). 1=enable, 0=disable Enable VCO-N Counter programming (byte21~22) programming through setting byte 21~22 programming through Frequency setting
Status Profile Accu-SST Enable Skew Enable VCO-N Enable
BYTE Spread Spectrum Modulation Amplitude Programming Register:
NAME
SST6 SST5 SST4 SST3 SST2 SST1 SST0
Default
Description
Spread Spectrum mode selection. 1=Center Spread, Down Spread
Center Spread: SST<6:0> Modulation rate Down Spread: SST<6:0> Modulation rate
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
8/20/02 Page
PLL202-108
Programmable Clock Generator 1681 Chip Sets
TABLE Output Signals SKEW Programming Summary: Bit<2:0>
Skew Setting (±80ps/step)
+320ps +240ps +160ps +80ps Default -80ps -160ps -240ps Setting applies following outputs: CPU0 CPU1
Skew Setting (±160ps/step)
+640ps +480ps +320ps +160ps Default -160ps -320ps -480ps Setting applies following outputs:
Byte SKEW Control Register
Skew CPU1 Skew CPU0
Name
Default
Reserved. Reserved.
Description
These three bits will adjust timing CPU_Host signals (CPUT_0/CPUC_0) either positive negative delay +320ps -240ps with ±80ps step accuracy. These three bits will adjust timing CPU_chip_sets signals (CPUT_1/CPUC_1) either positive negative delay +320ps -240ps with ±80ps step accuracy.
Byte SKEW Control Register
Skew HTT1 Skew HTT0
Name
CPU-PCI Skew
Default
Description
Skew setting between clocks Bit[7:6]: (default) 2.5ns These three bits will adjust timing HTTT_0/HTTC_0 signal either positive negative delay +640ps -480ps with ±160ps step accuracy. These three bits will adjust timing HTTT_1/HTTC_1 clock signals either positive negative delay +640ps -480ps with ±160ps step accuracy.
8/20/02 Page
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
PLL202-108
Programmable Clock Generator 1681 Chip Sets
Byte SKEW Control Register
Skew Skew
Name
Default
Reserved. Reserved.
Description
These three bits will adjust timing AGP0 AGP1 clock signals either positive negative delay +640ps -480ps with ±160ps step accuracy. These three bits will adjust timing clock signals either positive negative delay +640ps -480ps with ±160ps step accuracy.
TABLE Output Drive Strength Programming Summary: Bit<2:0>
+40% +30% +20% +10% Default -10% -20% -30% Setting applies following outputs AGP[0:1] 48M, 24_48MHz
Setting
+50% +38% +25% +13% Default -13% -25% -38%
Setting
Setting applies following outputs PCIF,PCI[5:8] PCI[0:4] REF[0:1]
Byte Buffer Drive Strength Control Register
Strength
Name
Default
Reserved. Reserved. Reserved. Reserved. Reserved.
Description
These three bits will program drive strength clocks output clock (see Table
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
8/20/02 Page
PLL202-108
Programmable Clock Generator 1681 Chip Sets
Byte Buffer Drive Strength Control Register
Strength PCIF, PCI[5:8] Strength
Name
Default
Reserved. Reserved.
Description
These three bits will program drive strength 48MHz 24_48MHz output clocks (see Table
These three bits will program drive strength PCIF PCI[5:8] output clocks (see Table
Byte Buffer Drive Strength Control Register
Strength PCI[0:4] Strength
Name
Default
Reserved. Reserved.
Description
These three bits will program drive strength PCI[0:4] output clocks (see Table
These three bits will program drive strength REF[0:1] output clocks (see Table
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
8/20/02 Page
PLL202-108
Programmable Clock Generator 1681 Chip Sets
TABLE Divider Programming Summary: Bit<3:0>
1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 CPU0 CPU1
High Speed Divider
Default Selection
Speed Divider
Default Selection /7.5 AGP[0:1]
Speed Divider
Default Selection PCIF,PCI
Byte Divider Control Register
CPU-CS Divider CPU-Host Divider
Name
Default
Description
These four bits will program divider CPUT_0 CPUC_0 clocks (see Table
These four bits will program divider CPUC_1 CPUT_1 clocks (see Table
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
8/20/02 Page
PLL202-108
Programmable Clock Generator 1681 Chip Sets
Byte Divider Control Register
Divider Divider
Name
Default
Description
These four bits will program divider clocks (see Table
These four bits will program divider clocks (see Table
Byte Divider Control Register
Divider
Name
Default
(Reserved)
Description
These four bits will program divider clocks (see Table
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
8/20/02 Page
PLL202-108
Programmable Clock Generator 1681 Chip Sets
BYTE Counter Register:
Name
N<15> N<14> N<13> N<12> N<11> N<10> N<9> N<8>
Default
Description
VCO(MHz)= N<15:0> 14.318/
BYTE Counter Register
Name
N<7> N<6> N<5> N<4> N<3> N<2> N<1> N<0>
Default
Description
VCO(MHz)= N<15:0> 14.318/
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
8/20/02 Page
PLL202-108
Programmable Clock Generator 1681 Chip Sets
PROGRAMMING FREQUENCY simplify traditional loop counter setting, PLL202-108 device incorporates SMART-BYTE AccuVCO technology with single variable programming I2C. Detail PLL202-108's tri-mode frequency programming method described below: ROM-table Frequency Programming: pre-defined frequencies found Frequency table accessed through external jumpers bits setting. Micro-step Linear Frequency Programming: Frequency programmed fine linear positive negative stepping around selected frequency Frequency table. highest step either +127 -127. Other frequencies will changed proportionally with rate that frequency changes.
CPU.ROM-Table
Where: magnitude factor defined Byte 7.bit (0:6) (sign bit) defined Byte7.bit defined Frequency table 1.79/(VCO_Divider).
Frequency Programming: Internal frequency defined function times fixed constant 0.028.
Where:
0.028
limited range between 200(Mhz) 1200(Mhz). (counter) defined byte 21,22
Programmable divider Table pre-defined divider Frequency table will then determine output Frequency. Other frequencies will changed proportionally with rate that frequency changes. formula follow:
VCO_divider
Where: VCO_divider either predefined frequency table through Byte 18-20
BUILT-IN WATCHDOG TIMER (WDT) Watchdog timer used perform safe recovery frequency switching causes system enter into "Hang-up" state within reasonable period time Watchdog time interval). While disabled, watchdog time interval programmed between 250ms seconds setting timer unit timer interval. Once Enabled, disabled within period that shorter than programmed watchdog interval; otherwise will generate 500ms watchdog reset pulse provoke system reset. After system restarts, PLL202-108 will start from predefined Fall-back Frequency system reason fails again Fall-back Frequency, internal hardware will then generate watchdog reset restart system from value external hardware jumper setting ensure safe recovery.
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 8/20/02 Page
PLL202-108
Programmable Clock Generator 1681 Chip Sets
OPERATIONAL FLOW CHART
START Register Loading: Fall-Back, WD-TIMER, WD-ENABLE
Disable WDEnable Target Setting
SUCCESS
Wait System Response
Copy Fall-Back Frequency Setting Frequency Setting Disable WDEnable Fall-Back Frequency Setting
FAIL After specified WD-Timer Expired
SUCCESS
System Restart Fall-back Frequency
FAIL After specified WD-Timer Expired
System Restart Jumper-Setting Frequency
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
8/20/02 Page
PLL202-108
Programmable Clock Generator 1681 Chip Sets
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings PARAMETERS
Supply Voltage Input Voltage, Output Voltage, Storage Temperature Ambient Operating Temperature Junction Temperature Voltage
SYMBOL
MIN.
MAX.
UNITS
Exposure device under conditions beyond limits specified Maximum Ratings extended periods cause permanent damage device affect product reliability. These conditions represent stress rating only, functional operations device these other conditions above operational limits noted this specification implied.
DC/AC Electrical Specifications PARAMETERS
Input High Voltage Input Voltage Input High Current Input Current Input Current
SYMBOL
CONDITIONS
Inputs except inputs except with pull-up resistor with pull-up resistor pF@66MHz, 3.3V±5% pF@133MHz, 3.3V±5% pF@66MHz, 2.5V±5% pF@133MHz, 2.5V±5% crossing target Freq. 3.3V Logic Inputs XOUT pins
MIN.
-0.3
TYP.
MAX.
+0.3
UNITS
-200 14.318
Supply Current
Transition Time Input frequency Input Capacitance
trans
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
8/20/02 Page
PLL202-108
Programmable Clock Generator 1681 Chip Sets
DC/AC Electrical Specifications (continued)
Unless otherwise stated, power supplies 3.3V±5%, ambient temperature range 70°C
PARAMETERS
SYMBOL
OUTPUTS
CONDITIONS
Measured 0.4V 2.0V, =10-20pf, 2.5V±5% Measured 0.4V 2.4V, =10-20pf Measured 0.4V 2.4V, =10-30pf Measured 0.4V, =10-20pf, 2.5V±5% Measured 2.4V 0.4V, =10-20pf Measured 2.4V 0.4V, =10-30pf Measured 1.5V =20pf Measured 1.5V, =20~30pf Rising edge 1.25V, =20pf Rising edge 1.5V, =30pf Rising edge 1.5V, =30pf Measured 1.25V Measured 1.5V Measured 1.5V Assumes full supply voltage reached within from power-up. Short cycle exist prior frequency stabilization. =3.3V(2.5V)±5% =3.3V±5% =3.3V±5%
MIN.
TYP.
MAX.
UNITS
Output Rise time
REF, 48MHz, 24MHz PCIF, PCI, AGP, APIC
Output Fall time
REF, 48MHz, 24MHz PCIF, PCI, AGP, APIC CPU,APIC,REF, 48MHz,24MHz PCI,
Duty Cycle
Clock Skew
SKEW
Jitter(Cycle Cycle)
cyc-cyc
PCI,
Frequency Stabilization Time
CPU,PCIF,PCI, APIC,AGP,REF, 48MHz,24MHz
output impedance
PCI,AGP REF,48MHz,24MHz
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
8/20/02 Page
PLL202-108
Programmable Clock Generator 1681 Chip Sets
PACKAGE INFORMATION
0.400 0.410 10.160 10.414
0.292 0.299 7.417 7.595
0.008 0.0135 0.203 0.343
0.025 0.635
0.015 (0.381) 0.010 0.016 (0.254 0.406)
0.620 0.630 (15.75 16.00)
0.088 0.096 (2.235 2.438)
0.097 0.104 (2.464 2.642) 30-60 0.050 (1.27) 0.008 0.016 (0.203 0.406)
48PIN SSOP
ORDERING INFORMATION
part ordering, please contact Sales Department:
47745 Fremont Blvd., Fremont, 94538, Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
order number this device combination following: Device number, Package type Operating temperature range
PLL202-108
PART NUMBER TEMPERATURATURE C=COMMERCIAL M=MILITARY I=INDUSTRAL PACKAGE TYPE X=SSOP
PhaseLink Corporation, reserves right make changes products specifications, both time without notice. information furnished Phaselink believed accurate reliable. However, PhaseLink makes guarantee warranty concerning accuracy said information shall responsible loss damage whatever nature resulting from reliance upon this product. LIFE SUPPORT POLICY: PhaseLink's products authorized critical components life support devices systems without express written approval President PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
8/20/02 Page
Other recent searches
XZFABBA10C2 - XZFABBA10C2 XZFABBA10C2 Datasheet
SN74AUC16244 - SN74AUC16244 SN74AUC16244 Datasheet
PI3C3861 - PI3C3861 PI3C3861 Datasheet
MAX8704 - MAX8704 MAX8704 Datasheet
LA175B - LA175B LA175B Datasheet
EPS120050-P5P - EPS120050-P5P EPS120050-P5P Datasheet
CFAH1602J-YYH-JP - CFAH1602J-YYH-JP CFAH1602J-YYH-JP Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
