Programmable Clock Generator 645/650 Chip Sets Supports 645/650,

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Programmable Clock Generator 645/650 Chip Sets Supports 645/650,

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PLL202-107
Programmable Clock Generator 645/650 Chip Sets
Supports 645/650, 646, Chipsets. Programmable Spread Spectrum Modulation from ±0.1% ±1.5% with step size small ±0.012%. Selectable Spread Spectrum either center down. Selectable Spread Spectrum modulation profile. AccuSkew Programmable Precision skew tuning channel with maximum precision over variation temperature, process voltage with step size small 80ps. AccuDrive Programmable Output Buffer drive strength with +50% -40%. Programmable frequency with variable Programmable Output Divider CPU, SDRAM, ZCLK, PCI. differential CPUCLK, SDRAM, ZCLK, AGP, PCI, clock outputs. programmable 24MHz 48MHz SIO. Support 2-wire serial interface. Built-in programmable watchdog timer Available SSOP.
CONFIGURATION
VDDREF REF0/FS0*v REF1/FS1*v REF2/FS2*v VSSREF XOUT VSSZ ZCLK0 ZCLK1 VDDZ WDRESET/PCISTOP#^ VDDPCI PCIF0/FS3*v PCIF1/FS4*v PCI0 PCI1 VSSPCI VDDPCI PCI2 PCI3 PCI4 PCI5 VSSPCI VDDSD SDCLK VSSSD CPU_STOP# CPUT_1 CPUC_1 VDDCPU VSSCPU CPUT_0 CPUC_0 IREF VSSA VDDA SCLK SDATA /Vtt_PWRGD VSSAGP AGP0 AGP1 VDDAGP VDD48M 48MHz 24_48MHz/MULTSEL* VSS48M
PLL202-107
Note:
Pull (120k),
Pull down (120k), Active low,
Bi-directional latched power-up
BLOCK DIAGRAM
REF(0:2) VDD_CPU CPU_STOP# PCI_STOP# MULTSEL FS(0:4) PLL1 Control Logic CPUT (0:1) CPUC (0:1) SDCLK ZCLK (0:1) (0:1) (0:5) PCI_F(0:1) 48Mhz PLL2 SDATA SCLK Logic Watch 24_48Mhz WDRESET#
POWER GROUP
VDDREF (3.3V), VSSREF: REF, XIN, XOUT VDDPCI (3.3V), VSSPCI: VDDAGP (3.3V), VSSAGP: VDD48M (3.3V), VSS48M: 48MHz, 24_48MHz VDDCPU (3.3V), VSSCPU: CPUT/C_[0:1] VDDSD (3.3V), VSSSD: SDCLK VDDA (3.3V), VSSA: Analog VDDZ (3.3V), VSSZ: ZCLK
XOUT
XTAL
SPECIFICATIONS
Output Skew 150ps. AGP(Z) AGP(Z) Output Skew 175ps Output Skew <500ps SDCLK Skew: (Typ 0ns). (early) Skew: (Typ 2ns). (early) Skew: (Typ 2ns). (early) Skew: (Typ 2ns).
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10/28/02 Page
PLL202-107
Programmable Clock Generator 645/650 Chip Sets
DESCRIPTIONS
Name
XOUT REF[0:2]/FS[0:2] PD#/Vtt_PWRGD
Number
2,3,4
Type
Description
14.318Mhz crystal input connected crystal 14.318Mhz crystal output 14.318Mhz Reference clock output. This latch FS[0:2] value powerup. (See Frequency Selection table). internal pull down resistor. power-up, this input Vtt_PWRGD After first high low, this acts disable clock outputs including internal crystal clock when Low. When Vtt_PWRGD input high, (0:4) MULTSEL0 inputs latched outputs enabled. clock output (see Frequency table). Hyper clock output (see Frequency table). Stop clock outputs when low. 120K internal pull resistor. Watch reset will generated after timer expires when Enable (Byte12.bit7) active. When inactive, this acts PCI_STOP input stop clock outputs except PCIF[0:1] when low. 120K internal pull resistor. clock output (see Frequency table). PCI5 programmable double drive strength. This latches MULTSEL value power-up. After power-up, this acts 24_48Mhz clock output with default 24MHz selection I2C. MULTSEL used select current multiplier outputs. MULTSEL=0, IOH=4XIREF. MULTSEL=1, IOH=6XIREF Differential pair output Host. Differential pair output Chip Sets. Bi-directional pin. power-up, FS[3:4] input value latched. After power-up, this acts PCIF[0:1] output. internal pull-down resistor. SDRAM clock output clock output. This establishes reference current differential pairs, requires fixed precision resistor tied ground order establish appropriate current. Serial data inputs serial interface port. Serial data inputs serial interface port.
AGP[0:1] ZCLK[0:1] CPU_STOP# WDRESET/ PCI_STOP#
30,31 9,10
PCI[0:5] 24_48MHz/MULTSEL
16,17,20 21,22,23
CPU[C/T]_0 CPU[C/T]_1 PCIF[0:1]/FS[3:4]
39,40 43,44 14,15
SDCLK 48MHz Iref
SDATA SCLK
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PLL202-107
Programmable Clock Generator 645/650 Chip Sets
DESCRIPTIONS (Continue)
Name
VDDPCI VDDZ VDDAGP VDDSD VDD48M VDDA VDDCPU VDDREF
Number
5,8,18,19 27,34,41,46
Type
3.3V Power Supply Zclock.
Description
3.3V Power Supply PCIF[0:1], PCI[0:5] clock 3.3V Power Supply clock. 3.3V Power Supply SDCLK clock. 3.3V Power Supply 48MHz 24_48MHz clock 3.3V power internal PLL. 3.3v power supply CPU[T,C]_[0:1] clocks. 3.3v power supply REF[0:2] clocks Ground.
HOST SWING SELECT FUNCTIONS
MULTISEL0 Board Target Trace/Term Reference (Rr) VDD/(3*Rr) 221; Iref 5.0mA 475; Iref 2.32 Output Current 4*IREF 6*IREF 1.0V 0.7V
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PLL202-107
Programmable Clock Generator 645/650 Chip Sets
FREQUENCY (MHz) SELECTION TABLE
66.67 100.00 111.17 100.00 100.00 133.40 133.40 133.33 100.00 100.00 111.17 100.00 100.00 133.33 100.00 166.75 166.67 150.00 140.00 166.75 100.00 100.00 133.40 133.40 111.17 125.00 100.00 120.00 133.33 100.00 180.00 200.00
SDCLK
66.67 133.33 166.75 200.00 100.00 133.40 166.75 200.00 166.67 133.33 166.75 200.00 133.33 133.33 166.67 133.40 200.00 150.00 140.00 166.75 133.33 133.33 133.40 166.75 133.40 166.67 140.00 150.00 133.33 133.33 150.00 200.00
ZCLK
66.67 66.67 66.70 66.67 133.33 133.40 133.40 133.33 66.67 133.33 133.40 133.33 100.00 100.00 133.33 133.40 133.33 120.00 140.00 133.40 66.67 80.00 66.70 83.38 133.40 166.67 140.00 150.00 133.33 133.33 128.57 133.33
66.67 66.67 66.70 66.67 66.67 66.70 66.70 66.67 66.67 66.67 66.70 66.67 66.67 66.67 66.67 66.70 66.67 60.00 70.00 66.70 50.00 50.00 55.58 55.58 66.70 62.50 58.33 60.00 57.14 50.00 60.00 66.67
33.33 33.33 33.35 33.33 33.33 33.35 33.35 33.33 33.33 33.33 33.35 33.33 33.33 33.33 33.33 33.35 33.33 30.00 35.00 33.35 33.33 33.33 33.35 33.35 33.35 33.33 35.00 33.33 33.33 33.33 30.00 33.33
Amplitude
±0.5% center ±0.3% center ±0.3% center ±0.3% center ±0.3% center ±0.3% center ±0.3% center ±0.3% center ±0.3% center ±0.3% center ±0.3% center ±0.3% center ±0.3% center ±0.3% center ±0.3% center ±0.3% center ±0.3% center ±0.3% center ±0.3% center ±0.3% center ±0.3% center ±0.3% center ±0.3% center ±0.3% center ±0.3% center ±0.3% center ±0.3% center ±0.3% center ±0.3% center ±0.3% center ±0.3% center ±0.3% center
1000 1000 1000
(CPU)
14,303 14,303 23,851 14,303 14,303 23,851 23,851 14,303 35,759 14,303 23,851 14,303 14,303 14,303 35,759 23,851 35,759 21,455 25,031 23,851 14,303 14,303 23,851 23,851 23,851 17,879 25,031 21,455 14,303 14,303 32,183 28,607
0.30 0.45 0.30 0.45 0.45 0.36 0.36 0.60 0.18 0.45 0.30 0.45 0.45 0.60 0.18 0.45 0.30 0.45 0.36 0.45 0.45 0.45 0.36 0.36 0.30 0.45 0.26 0.36 0.60 0.45 0.36 0.45
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
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PLL202-107
Programmable Clock Generator 645/650 Chip Sets
CONFIGURATION SETTING
Address Assignment Slave Receiver/Transmitter Data Transfer Rate
Provides both slave write readback functionality Standard mode 100kbits/s This serial interface designed allow multiple protocols write read from controller. includes Block Read/Write, Block Index Read/Write, Byte Read/Write Word Read/Write. general, bytes must accessed sequential order from lowest highest byte. Each byte transferred must followed acknowledge bit. byte transferred without acknowledged will terminate transfer. write read block both begins with master sending slave address write condition (0xD2) read condition (0xD3).
Data Protocol
WRITE MODE
Block Write Address Command Byte count Data Byte Data Byte Data Data Byte
Block Index Write
Address
Command =(00~22)
Byte count
Data Byte
Data Byte
Data
Data Byte M+N-1
Byte Write
Address
Command =(00~22)+128
Data Byte
Word Write
Address
Command =(00~22)+128
Data Byte
Data Byte
READ MODE
Block Read Address Command Address Byte count Data Byte Data Byte Data Data Byte
Block Index Read
Address
Command =(00~22)
Address
Byte count
Data Byte
Data Byte
Data
Data Byte M+N-1
Byte Read
Address
Command =(00~22)+128
Address
Data Byte
Word Read
Address
Command =(00~22)+128
Address
Data Byte
Data Byte
Legend:
Start
Acknowledge Stop host
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PLL202-107
Programmable Clock Generator 645/650 Chip Sets
CONTROL REGISTERS
BYTE External Zero Delay Buffer BYTE Functional Frequency Select Clock Register (1=Enable, 0=Disable)
Pin#
Default
Power-up Latched FS3:FS0 value Power-up Latched value
Description
Frequency selection bit: 1=Via I2C, 0=Via External jumper 0=normal, Spread Spectrum Enable Spread Spectrum modulation amplitude selection. defined Frequency Table. ±0.6% (center) fixed.
BYTE Control Register (1=Enable, 0=Disable)
Pin#
Default
Description
AGP1 (1=Active 0=Inactive) AGP0 (1=Active 0=Inactive) 24_48MHZ selection. 1=24Mhz, 0=48Mhz Inverted Power-up latched value (Read only) Inverted Power-up latched value (Read only) Inverted Power-up latched value (Read only) Inverted Power-up latched value (Read only) Inverted Power-up latched value (Read only)
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PLL202-107
Programmable Clock Generator 645/650 Chip Sets
BYTE Control Register (1=Enable, 0=Disable)
Pin#
39,40 43,44 39,40 43,44
Default
Description
ZCLK1 (1=Active, 0=Inactive) ZCLK0 (1=Active, 0=Inactive) PCI_STOP# setting PCIF0 (0=Free Running, 1=Stopped) PCI_STOP# setting PCIF1 (0=Free Running, 1=Stopped) CPU_STOP# setting CPU[C/T]_0 (0=Free Running, 1=Stopped) CPU_STOP# setting CPU[C/T]_1 (0=Free Running, 1=Stopped) CPU[C/T]_0 (1=Active 0=Inactive) CPU[C/T]_1 (1=Active 0=Inactive)
BYTE Clock Register (1=Enable, 0=Disable)
Pin#
Default
Description
PCIF1 (1=Active 0=Inactive) PCIF0 (1=Active 0=Inactive) PCI5 (1=Active 0=Inactive) PCI4 (1=Active 0=Inactive) PCI3 (1=Active 0=Inactive) PCI2 (1=Active 0=Inactive) PCI1 (1=Active 0=Inactive) PCI0 (1=Active 0=Inactive)
BYTE Vendor Revision Register
Pin#
Default
Description
Vendor (read only) Vendor (read only) Vendor (read only) Vendor (read only) Revision (read only) Revision (read only) Revision (read only) Revision (read only)
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PLL202-107
Programmable Clock Generator 645/650 Chip Sets
BYTE Output Control Register
Pin#
Default
Description
48MHz (1=Active, 0=Inactive) 24_48MHz (1=Active, 0=Inactive) SDCLK (1=Active, 0=Inactive) (Reserved) (Reserved) REF2 (1=Active, 0=Inactive) REF1 (1=Active, 0=Inactive) REF0 (1=Active, 0=Inactive)
BYTE Control Register (1=Enable, 0=Disable)
Pin#
MULTSEL1 MULTSEL0
Default
Description
IREF Multiplier setting, [0,7] 4xIREF 5xIREF 6xIREF 7xIREF MULTSEL (IREF multiple) MODE Selection. selection through hardware input selection through control bit[6,7] Latched MULTSEL readback (read only) (Reserved) (Reserved) (Reserved) PCI5 double drive strength selection. 0=normal, 1=2X
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PLL202-107
Programmable Clock Generator 645/650 Chip Sets
BYTE Linear Programming Register (1=Enable, 0=Disable)
Pin#
Default
Description
Linear programming sign "+", Linear programming magnitude (MSB) Linear programming magnitude Linear programming magnitude Linear programming magnitude Linear programming magnitude Linear programming magnitude Linear programming magnitude (LSB)
BYTE WATCHDOG Fall Back Register (1=Enable, 0=Disable)
Pin#
Default
Description
Watchdog Timer Unit Bit[7:6]: 500ms, Initialization setting Linear Programming Byte after Watch reset. Byte initialized after WD-Reset generated. Byte unchanged after WD-Reset generated. Fall-back Frequency selection Fall-back Frequency selection Fall-back Frequency selection Fall-back Frequency selection Fall-back Frequency selection
BYTE WATCHDOG TIMER Register (1=Enable, 0=Disable)
Name
WDT<5> WDT<4> WDT<3> WDT<2> WDT<1> WDT<0>
Default
Description
Watchdog Timer Enable Bit. 1=Enable, 0=Disable 0=Watch falls back hardware jumper setting frequency 1=Watch falls back fall back frequency setting Byte Watchdog Time Interval (MSB) Watchdog Time Interval Watchdog Time Interval Watchdog Time Interval Watchdog Time Interval Watchdog Time Interval (LSB)
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PLL202-107
Programmable Clock Generator 645/650 Chip Sets
BYTE Programming Mode Counter Register (1=Enable, 0=Disable)
Name
AccuSkew Enable
Default
Description
AccuSkew Setting process independent accuracy. 1=enable, 0=disable. Initialization setting Skew Control Buffer drive strength registers after Watch reset. Byte 16~22 initialized after WD-Reset generated. Byte 16~22 unchanged after WD-Reset generated. Watch Timer Status info (read only) linear, non-linear Accu-SST programming Enable: Byte12, setting Enable Skew programming (byte16~18). 1=enable, 0=disable Enable VCO-N Counter programming (byte26~27) programming through setting byte 26~27 programming through Frequency setting
Status Profile Accu-SST Enable Skew Enable VCO-N Enable
BYTE Spread Spectrum Modulation Amplitude Programming Register:
NAME
SST6 SST5 SST4 SST3 SST2 SST1 SST0
Default
Description
Spread Spectrum mode selection. 1=Center Spread, Down Spread
Center Spread: SST<6:0> Modulation rate Down Spread: SST<6:0> Modulation rate
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PLL202-107
Programmable Clock Generator 645/650 Chip Sets
TABLE Output Signals SKEW Programming Summary: Bit<2:0>
Skew Setting (±80ps/step)
+320ps +240ps +160ps +80ps Default -80ps -160ps -240ps Setting applies following outputs: CPU0 CPU1 SDCLK
Skew Setting (±160ps/step)
+640ps +480ps +320ps +160ps Default -160ps -320ps -480ps Setting applies following outputs: ZCLK
Byte SKEW Control Register
Skew CPU1 Skew CPU0
Name
Default
Reserved. Reserved.
Description
These three bits will adjust timing CPU_Host signals (CPUT_0/CPUC_0) either positive negative delay +320ps -240ps with ±80ps step accuracy. These three bits will adjust timing CPU_chip_sets signals (CPUT_1/CPUC_1) either positive negative delay +320ps -240ps with ±80ps step accuracy.
Byte SKEW Control Register
Skew ZCLK Skew SDCLK
Name
CPU-PCI/AGP/Z Skew
Default
Description
Skew setting between Z/AGP/PCI clocks Bit[7:6]: (default) 2.5ns These three bits will adjust timing SDCLK signal either positive negative delay +320ps -240ps with ±80ps step accuracy. These three bits will adjust timing ZCLK[0:1] clock signals either positive negative delay +640ps -480ps with ±160ps step accuracy.
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47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
PLL202-107
Programmable Clock Generator 645/650 Chip Sets
Byte SKEW Control Register
Skew Skew
Name
Default
Reserved. Reserved.
Description
These three bits will adjust timing AGP0 AGP1 clock signals either positive negative delay +640ps -480ps with ±160ps step accuracy. These three bits will adjust timing clock signals either positive negative delay +640ps -480ps with ±160ps step accuracy.
TABLE Output Drive Strength Programming Summary: Bit<2:0>
+33% +25% +17% Default -16% -25% Setting applies following outputs SDCLK
Setting
+40% +30% +20% +10% Default -10% -20% -30%
Setting
+50% +38% Setting applies following outputs ZCLK[0:1] AGP[0:1] 48M, 24_48MHz +25% +13% Default -13% -25% -38%
Setting
Setting applies following outputs PCIF[0:1],PCI0 PCI[1:5] REF[0:2]
Byte Buffer Drive Strength Control Register
SDCLK Strength
Name
Default
Reserved. Reserved. Reserved. Reserved. Reserved.
Description
These three bits will program drive strength SDCLK output clock (see Table
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PLL202-107
Programmable Clock Generator 645/650 Chip Sets
Byte Buffer Drive Strength Control Register
Strength ZCLK Strength
Name
Default
Reserved. Reserved.
Description
These three bits will program drive strength ZCLK0 ZCLK1 output clocks (see Table
These three bits will program drive strength AGP0 AGP1 output clocks (see Table
Byte Buffer Drive Strength Control Register
PCIF,PCI0 Strength Strength
Name
Default
Reserved. Reserved.
Description
These three bits will program drive strength 48MHz 24_48MHz output clocks (see Table
These three bits will program drive strength PCIF[0:1] PCI0 output clocks (see Table
Byte Buffer Drive Strength Control Register
Strength PCI[1:5] Strength
Name
Default
Reserved. Reserved.
Description
These three bits will program drive strength PCI[1:5] output clocks (see Table
These three bits will program drive strength REF[0:2] output clocks (see Table
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PLL202-107
Programmable Clock Generator 645/650 Chip Sets
TABLE Divider Programming Summary: Bit<3:0>
1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000
High Speed Divider
Default Selection CPU0 CPU1 SDCLK
Speed Divider
Default Selection /7.5 ZCLK AGP[0:1]
Speed Divider
Default Selection PCIF,PCI
Byte Divider Control Register
CPU-CS Divider CPU-Host Divider
Name
Default
Description
These four bits will program divider CPUT_0 CPUC_0 clocks (see Table
These four bits will program divider CPUC_1 CPUT_1 clocks (see Table
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PLL202-107
Programmable Clock Generator 645/650 Chip Sets
Byte Divider Control Register
ZCLK Divider SDCLK Divider
Name
Default
Description
These four bits will program divider SDRAM clock (see Table
These four bits will program divider ZCLK clocks (see Table
Byte Divider Control Register
AGP[0:1] Divider
Name
Default
Description
These four bits will program divider AGP0 AGP1 clocks (see Table
Divider
These four bits will program divider clocks (see Table
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PLL202-107
Programmable Clock Generator 645/650 Chip Sets
BYTE Counter Register:
Name
N<15> N<14> N<13> N<12> N<11> N<10> N<9> N<8>
Default
Description
VCO(MHz)= N<15:0> 14.318/
BYTE Counter Register
Name
N<7> N<6> N<5> N<4> N<3> N<2> N<1> N<0>
Default
Description
VCO(MHz)= N<15:0> 14.318/
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PLL202-107
Programmable Clock Generator 645/650 Chip Sets
PROGRAMMING FREQUENCY simplify traditional loop counter setting, PLL202-107 device incorporates SMART-BYTE AccuVCO technology with single variable programming I2C. Detail PLL202-107's tri-mode frequency programming method described below: ROM-table Frequency Programming: pre-defined frequencies found Frequency table accessed through external jumpers bits setting. Micro-step Linear Frequency Programming: Frequency programmed fine linear positive negative stepping around selected frequency Frequency table. highest step either +127 -127. Other frequencies will changed proportionally with rate that frequency changes.
CPU.ROM-Table
Where: magnitude factor defined Byte 11.bit (0:6) (sign bit) defined Byte11.bit defined Frequency table 1.79/(VCO_Divider).
Frequency Programming: Internal frequency defined function times fixed constant 0.028.
Where:
0.028
limited range between 200(Mhz) 1200(Mhz). (counter) defined byte 26,27
Programmable divider Table pre-defined divider Frequency table will then determine output Frequency. Other frequencies will changed proportionally with rate that frequency changes. formula follow:
VCO_divider
Where: VCO_divider either predefined frequency table through Byte 23-25
BUILT-IN WATCHDOG TIMER (WDT) Watchdog timer used perform safe recovery frequency switching causes system enter into "Hang-up" state within reasonable period time Watchdog time interval). While disabled, watchdog time interval programmed between 250ms seconds setting timer unit timer interval. Once Enabled, disabled within period that shorter than programmed watchdog interval; otherwise will generate 500ms watchdog reset pulse provoke system reset. After system restarts, PLL202-107 will start from predefined Fall-back Frequency system reason fails again Fall-back Frequency, internal hardware will then generate watchdog reset restart system from value external hardware jumper setting ensure safe recovery.
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PLL202-107
Programmable Clock Generator 645/650 Chip Sets
OPERATIONAL FLOW CHART
START Register Loading: Fall-Back, WD-TIMER, WD-ENABLE
Disable WDEnable Target Setting
SUCCESS
Wait System Response
Copy Fall-Back Frequency Setting Frequency Setting Disable WDEnable Fall-Back Frequency Setting
FAIL After specified WD-Timer Expired
SUCCESS
System Restart Fall-back Frequency
FAIL After specified WD-Timer Expired
System Restart Jumper-Setting Frequency
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PLL202-107
Programmable Clock Generator 645/650 Chip Sets
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings PARAMETERS
Supply Voltage Input Voltage, Output Voltage, Storage Temperature Ambient Operating Temperature Junction Temperature Voltage
SYMBOL
MIN.
MAX.
UNITS
Exposure device under conditions beyond limits specified Maximum Ratings extended periods cause permanent damage device affect product reliability. These conditions represent stress rating only, functional operations device these other conditions above operational limits noted this specification implied.
DC/AC Electrical Specifications PARAMETERS
Input High Voltage Input Voltage Input High Current Input Current Input Current
SYMBOL
CONDITIONS
Inputs except inputs except with pull-up resistor with pull-up resistor pF@66MHz, 3.3V±5% pF@133MHz, 3.3V±5% pF@66MHz, 2.5V±5% pF@133MHz, 2.5V±5% crossing target Freq. 3.3V Logic Inputs XOUT pins
MIN.
-0.3
TYP.
MAX.
+0.3
UNITS
-200 14.318
Supply Current
Transition Time Input frequency Input Capacitance
trans
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PLL202-107
Programmable Clock Generator 645/650 Chip Sets
DC/AC Electrical Specifications (continued)
Unless otherwise stated, power supplies 3.3V±5%, ambient temperature range 70°C
PARAMETERS
SYMBOL
OUTPUTS
CONDITIONS
Measured 0.4V 2.0V, =10-20pf, 2.5V±5% Measured 0.4V 2.4V, =10-20pf Measured 0.4V 2.4V, =10-30pf Measured 0.4V, =10-20pf, 2.5V±5% Measured 2.4V 0.4V, =10-20pf Measured 2.4V 0.4V, =10-30pf Measured 1.5V =20pf Measured 1.5V, =20~30pf Rising edge 1.25V, =20pf Rising edge 1.5V, =30pf Rising edge 1.5V, =30pf Measured 1.25V Measured 1.5V Measured 1.5V Assumes full supply voltage reached within from power-up. Short cycle exist prior frequency stabilization. =3.3V(2.5V)±5% =3.3V±5% =3.3V±5%
MIN.
TYP.
MAX.
UNITS
Output Rise time
REF, 48MHz, 24MHz PCIF, PCI, AGP, APIC
Output Fall time
REF, 48MHz, 24MHz PCIF, PCI, AGP, APIC CPU,APIC,REF, 48MHz,24MHz PCI,
Duty Cycle
Clock Skew
SKEW
Jitter(Cycle Cycle)
cyc-cyc
PCI,
Frequency Stabilization Time
CPU,PCIF,PCI, APIC,AGP,REF, 48MHz,24MHz
output impedance
PCI,AGP REF,48MHz,24MHz
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PLL202-107
Programmable Clock Generator 645/650 Chip Sets
PACKAGE INFORMATION
0.400 0.410 10.160 10.414
0.292 0.299 7.417 7.595
0.008 0.0135 0.203 0.343
0.025 0.635
0.015 (0.381) 0.010 0.016 (0.254 0.406)
0.620 0.630 (15.75 16.00)
0.088 0.096 (2.235 2.438)
0.097 0.104 (2.464 2.642) 30-60 0.050 (1.27) 0.008 0.016 (0.203 0.406)
48PIN SSOP
ORDERING INFORMATION
part ordering, please contact Sales Department:
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PART NUMBER
order number this device combination following: Device number, Package type Operating temperature range
PLL202-107
PART NUMBER TEMPERATURATURE C=COMMERCIAL M=MILITARY I=INDUSTRAL PACKAGE TYPE X=SSOP
PhaseLink Corporation, reserves right make changes products specifications, both time without notice. information furnished Phaselink believed accurate reliable. However, PhaseLink makes guarantee warranty concerning accuracy said information shall responsible loss damage whatever nature resulting from reliance upon this product. LIFE SUPPORT POLICY: PhaseLink's products authorized critical components life support devices systems without express written approval President PhaseLink Corporation.
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10/28/02 Page

Programmable Clock Generator 645/650 Chip Sets Supports 645/650,

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