10/100BASE PCMCIA Fast Ethernet Controller Document No.: AX190-16
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AX88190P PCMCIA Fast Ethernet Controller
10/100BASE PCMCIA Fast Ethernet Controller
Document No.: AX190-16 V1.6 May.
IEEE 802.3u 100BASE-T, Compatible Single chip PCMCIA 10/100Mbps Fast Ethernet Controller NE2000 register level compatible instruction Compliant with Card Standard February 1995 Support both 10Mbps 100Mbps data rate Support both full-duplex half-duplex operation Provides port both 10/100Mbps operation Support 256/512 bytes EEPROM (used saving CIS) Support automatic loading Ethernet Adapter Configuration from EEPROM poweron initialization External internal loop-back capability 128-pin LQFP profile package 25MHz Operation, Dual 3.3V CMOS process with tolerance. pure 3.3V operation
*IEEE registered trademark Institute Electrical Electronic Engineers, Inc. *All other trademarks registered trademark property their respective holders.
Product description
AX88190 Fast Ethernet Controller high performance PCMCIA Ethernet Controller. AX88190 contains PCMCIA interfaces host compliant with Card Standard February 1995. AX88190 implements both 10Mbps 100Mbps Ethernet function based IEEE802.3 IEEE802.3u standard. AX88190 supports 10Mbps/100Mbps media-independent interface (MII) simplify design. AX88190 built interface connect FAX/MODEM chipset with parallel interface.
System Block Diagram
RJ11
RJ45
MAGNETIC
MODEM
PHY/TxRx
EEPROM AX88190 SRAM
PCMCIA
Always contact ASIX possible updates before starting design.
This data sheet contains products information. ASIX ELECTRONICS reserves rights modify product specification without notice. liability assumed result this product. rights under patent accompany sale product.
ASIX ELECTRONICS CORPORATION
Frist Released Date Oct/02/1998
http://www.asix.com.tw
NO.13, Industry East Science-based Industrial Park, Hsin-Chu City, Taiwan, R.O.C. TEL: 886-3-579-9500 FAX: 886-3-579-9558
AX88190
PCMCIA Fast Ethernet Controller CONTENTS
INTRODUCTION GENERAL DESCRIPTION: AX88190 BLOCK DIAGRAM:.5 AX88190 CONNECTION DIAGRAM SIGNAL DESCRIPTION.7 PCMCIA INTERFACE SIGNALS GROUP EEPROM SIGNALS GROUP INTERFACE SIGNALS GROUP MODEM INTERFACE PINS GROUP SRAM INTERFACE PINS GROUP MISCELLANEOUS PINS GROUP POWER CONFIGURATION SETUP SIGNALS CROSS REFERENCE TABLE MEMORY MAPPING EEPROM MEMORY MAPPING ATTRIBUTE MEMORY MAPPING.11 MAPPING.12 SRAM MEMORY MAPPING REGISTERS OPERATION.13 PCMCIA FUNCTION CONFIGURATION REGISTER LAN.13 4.1.1 Configuration Option Register (LCOR) Offset 3C0H (Read/Write).14 4.1.2 Configuration Status Register (LCSR) Offset 3C2H (Read/Write) 4.1.3 Base Register (LIOBASE0/1) Offset 3CAH/3CCH (Read/Write) PCMCIA FUNCTION CONFIGURATION REGISTER MODEM.16 4.2.1 Configuration Option Register MODEM (MCOR) Offset 3E0H (Read/Write).16 4.2.2 Configuration Status Register MODEM (MCSR) Offset 3E2H (Read/Write) 4.2.3 Base Register MODEM (MIOBASE0/1) Offset 3EAH/3ECH (Read/Write) REGISTERS OPERATION 4.3.1 Command Register (CR) Offset (Read/Write).20 4.3.2 Interrupt Status Register (ISR) Offset (Read/Write).20 4.3.3 Interrupt mask register (IMR) Offset (Write) 4.3.4 Data Configuration Register (DCR) Offset (Write).21 4.3.5 Transmit Configuration Register (TCR) Offset (Write) 4.3.6 Transmit Status Register (TSR) Offset (Read) 4.3.7 Receive Configuration (RCR) Offset (Write) 4.3.8 Receive Status Register (RSR) Offset (Read) 4.3.9 Inter-frame (IFG) Offset (Read/Write).22 4.3.10 Inter-frame Segment 1(IFGS1) Offset (Read/Write).23 4.3.11 Inter-frame Segment 2(IFGS2) Offset (Read/Write).23 4.3.12 MII/EEPROM Management Register (MEMR) Offset (Read/Write) 4.3.13 Test Register (TR) Offset (Write).23 PCMCIA DEVICE ACCESS FUNCTIONS ATTRIBUTE MEMORY ACCESS FUNCTION FUNCTIONS. ACCESS FUNCTION FUNCTIONS. ELECTRICAL SPECIFICATION TIMINGS ABSOLUTE MAXIMUM RATINGS GENERAL OPERATION CONDITIONS CHARACTERISTICS.25 ASIX ELECTRONICS CORPORATION
AX88190
PCMCIA Fast Ethernet Controller
A.C. TIMING CHARACTERISTICS.26 6.4.1 XTAL CLOCK.26 6.4.2 Reset Timing.26 6.4.3 Attribute Memory Read Timing.27 6.4.4 Attribute Memory Write Timing 6.4.5 Read Timing 6.4.6 Write Timing.30 6.4.7 Timing.31 6.4.8 Asynchronous Memory Access Timing.32 PACKAGE INFORMATION APPENDIX APPLICATION NOTE 1.34 USING CRYSTAL USING OSCILLATOR DUAL POWER 3.3V) APPLICATION SINGLE POWER (3.3V) APPLICATION DUAL POWER 3.3V) APPLICATION WITH 3.3V APPENDIX APPLICATION NOTE 2.37 ADVANCE APPLICATION USING CRYSTAL ERRATA AX88190
ASIX ELECTRONICS CORPORATION
AX88190
PCMCIA Fast Ethernet Controller FIGURES
AX88190 BLOCK DIAGRAM AX88190 CONNECTION DIAGRAM.6
TABLES
PCMCIA INTERFACE SIGNALS GROUP EEPROM INTERFACE SIGNALS GROUP.8 INTERFACE SIGNALS GROUP.8 MODEM INTERFACE SIGNALS GROUP.9 SRAM INTERFACE PINS GROUP.9 MISCELLANEOUS PINS GROUP.10 POWER CONFIGURATION SETUP TABLE EEPROM MEMORY MAPPING.11 ATTRIBUTE MEMORY MAPPING ADDRESS MAPPING LOCAL MEMORY MAPPING PCMCIA FUNCTION CONFIGURATION REGISTER MAPPING LAN.13 PCMCIA FUNCTION CONFIGURATION REGISTER MAPPING MODEM.16 PAGE CORE REGISTERS MAPPING.18 PAGE CORE REGISTERS MAPPING.19
ASIX ELECTRONICS CORPORATION
AX88190
PCMCIA Fast Ethernet Controller
Introduction
General Description:
AX88190 provides industrial standard NE2000 registers level compatable instruction set. Various drivers easy acquired, maintenance usage with pain tears AX88190 Fast Ethernet Controller high performance PCMCIA Ethernet Controller. AX88190 contains PCMCIA interfaces host compliant with Card Standard February 1995. AX88190 implements both 10Mbps 100Mbps Ethernet function based IEEE802.3 IEEE802.3u standard. AX88190 supports 10Mbps/100Mbps media-independent interface (MII) simplify design. AX88190 built interface connect FAX/MODEM chipset with parallel interface. AX88190A 128-pin LQFP profile package, 25MHz operation frequency, dual 3.3V CMOS process with tolerance pure 3.3V operation.
AX88190 Block Diagram:
MEMA[15:1]
MEMD[15:0] SMDC SMDIO
MODEM EECS EECK EEDI EEDO SEEPROM LOADER NE2000 Registers
SRAM Arbiter
Remote FIFOs Core
PCMCIA Interface
AX88190 Block Diagram
SA[9:0]
SD[15:0]
ASIX ELECTRONICS CORPORATION
AX88190
PCMCIA Fast Ethernet Controller
AX88190 Connection Diagram
AX88190 housed 128-pin plastic light quad flat packFig AX88190 Connection Diagram shows AX88190 assignment.
TXD[0] TX_EN TX_CLK MDIO RXD[3] RXD[2] RXD[1] RXD[0] RX_CLK RX_DV RX_ER MEMD[0] MEMD[1] MEMD[2] MEMD[3] MEMD[4] HVDD MEMD[5] MEMD[6] MEMD[7] MEMD[8] MEMD[9] MEMD[10] MEMD[11] MEMD[12] MEMD[13] TXD[1] TXD[2] TXD[3] LVDD CLKO25M LCLK/XTALIN XTALOUT EECS EECK EEDI EEDO LVDD MDCS# MINT MAUDIO PPWDN MRIN# MPWDN MRESET# MRDY IOIS16# STSCHG# SPKR# REG# INPACK# WAIT# LVDD RESET LVDD
AX88190 PCMCIA 10/100BASE CONTROLLER
HVDD MEMD[14] MEMD[15] MEMA[1] MEMA[2] MEMA[3] MEMA[4] MEMA[5] MEMA[6] LVDD MEMA[7] MEMA[8] MEMA[9] MEMA[10] MEMA[11] MEMA[12] MEMA[13] MEMA[14] LVDD MEMA[15] MEMRD# MEMWR# SD[0] SD[1] SD[2] SD[3] SD[4]
AX88190 Connection Diagram
SA[0] SA[1] SA[2] SA[3] SA[4] SA[5] SA[6] SA[7] SA[8] SA[9] IREQ# IOWR# IORD# CE2# CE1# HVDD SD[15] SD[14] SD[13] SD[12] SD[11] SD[10] SD[9] SD[8] HVDD SD[7] SD[6] SD[5]
ASIX ELECTRONICS CORPORATION
AX88190
PCMCIA Fast Ethernet Controller
Signal Description
following terms describe AX88190 pin-out: names with suffix asserted low. following abbreviations used following Tables. Input Output Input/Output Open Drain Pull Pull Down Power
PCMCIA Interface Signals Group
SIGNAL SA[9:0] SD[15:0] TYPE DESCRIPTION System Address Signals SA[9:0] address input lines which enable direct address memory spaces card. System Data Signals SD[15:0] constitute bi-directional data bus.
IREQ# WAIT# REG# IORD# IOWR# IOIS16#
INPACK#
CE1#-CE2# BVD1_STSCHG# BVD2_SPKR#
Interrupt Request IREQ# asserted indicate host system that Card device requires host software service. Wait This signal insert wait states during Remote transfer. Attribute Memory Space Select When REG# signal asserted, access limited Attribute Memory space. Read host asserts IORD# read data from AX88190 space. Write host asserts IOWR# write data into AX88190 space. Output Enable line used gate Memory Read data from memory Card Write Enable signal used strobing Memory Write data into memory Card. Port IOIS16# asserted when address socket corresponds address which card responds, port addressed capable 16-bit access. Input Port Acknowledge signal asserted when AX88190 selected respond read cycle address address bus. Card Enable CE1# enables even numbered address bytes CE2# enables numbered address bytes Battery Voltage Detect Status Change Battery Voltage Detect Audio speaker
PCMCIA interface signals group
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AX88190
PCMCIA Fast Ethernet Controller
EEPROM Signals Group
SIGNAL EECS EECK EEDI EEDO TYPE I/PU DESCRIPTION EEPROM Chip Select EEPROM chip select signal. EEPROM Clock Signal connected EEPROM clock pin. EEPROM Data Signal connected EEPROM data input pin. EEPROM Data Signal connected EEPROM data output pin.
EEPROM interface signals group
interface signals group
SIGNAL RXD[3:0] RX_DV TYPE DESCRIPTION Receive Data RXD[3:0] driven synchronously with respect RX_CLK. Carrier Sense Asynchronous signal asserted when either transmit receive medium non-idle. Receive Data Valid RX_DV driven synchronously with respect RX_CLK. Asserted high when valid data present [3:0]. Receive Error RX_ER driven synchronous RX_CLK, asserted more RX_CLK periods indicate port that error detected. Receive Clock RX_CLK continuous clock that provides timing reference transfer RX_DV,RXD[3:0] RX_ER signals from port repeater. Collision this signal driven when collision detected. Transmit Enable TX_EN transition synchronously with respect rising edge TX_CLK. TX_EN indicates that port presenting nibbles [3:0] transmission. Transmit Data TXD[3:0] transition synchronously with respect rising edge TX_CLK. each TX_CLK period which TX_EN asserted, TXD[3:0] accepted transmission PHY. Transmit Clock TX_CLK continuous clock from PHY. provides timing reference transfer TX_EN TXD[3:0] signals from port PHY. Station Management Data Clock timing reference MDIO. data transfers MDIO synchronized rising edge this clock. 2.5MHz frequency clock output. Station Management Data Input Output Serial data input/output transfers from/to PHYs transfer protocol conforms IEEE 802.3u specification.
RX_ER
RX_CLK
TX_EN
TXD[3:0]
TX_CLK
MDIO
I/O/PU
interface signals group
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AX88190
PCMCIA Fast Ethernet Controller
Modem interface pins group
Signal Name
MRDY
Type
I/PU
Description
Modem Ready MRDY indicates that modem initializing modem after reset signal asserted modem SLEEP/STOP mode. Modem Reset :This signal asserts reset modem chipset. Modem Chip Select This signal connected modem chip select pin. Modem Power Down Rockwell modem chipset, this signal asserts modem chipset into power down mode. AT&T modem chipset, this signal asserts high modem chipset into power down mode. Modem Interrupt This signal driven modem chipset active interrupt. Ring Input :This signal driven DAA's ring detect circuit. When telephone ringing signal being received. Modem Audio This signal passed PCMCIA interface SPKR.
MRESET# MDCS# MPWDN
MINT MRIN# MAUDIO
I/PD I/PU I/PD
Modem interface signals group
SRAM Interface pins group
SIGNAL MEMA[15:1] TYPE -53' DESCRIPTION SRAM Address
MEMD[15:0]
I/O/PU
SRAM Data
MEMRD# MEMWR#
SRAM Read SRAM Write
SRAM Interface pins group
ASIX ELECTRONICS CORPORATION
AX88190
PCMCIA Fast Ethernet Controller
Miscellaneous pins group
SIGNAL LCLK/XTALIN TYPE DESCRIPTION CMOS Local Clock 25Mhz clock, ppm, 40%-60% duty cycle. Crystal Oscillator Input 25Mhz crystal, connected across XTALIN XTALOUT. Crystal Oscillator Output 25Mhz crystal, connected across XTALIN XTALOUT. single-ended external clock (LCLK) connected XTALIN, crystal output should left floating. Clock Output 25MHz This clock source from LCLK/XTALIN. Power Down This connects chip power down mode control input. Reset Reset active high then place AX88190 into reset mode immediately. During Falling edge AX88190 loads EEPROM data. Power Supply +3.3V
XTALOUT
CLKO25M PPWDN RESET
I/PD
LVDD
HVDD
100, 110, 126, Power Supply Note pure 3.3V single power solution, HVDD connect +3.3V. Care should taken that HVDD input power must greater equal than LVDD. Power Supply Ground Power. 102, 105,
Miscellaneous pins group
Power configuration setup signals cross reference table
Signal Name
EEPROM SIZE MPD_SET PPD_SET TEST
Share with
MEMD[6] MEMD[5] MEMD[4] MEMD[3]
Description
EEPROM SIZE Test mode. EEPROM SIZE Normal operation. (Default) MPD_SET MPWDN active high. MPD_SET MPWDN active low. PPD_SET PPWDN active high. PPD_SET PPWDN active low. TEST Test mode. TEST Normal operation. (Default)
above signals pull-up default values.
Power Configuration Setup Table
ASIX ELECTRONICS CORPORATION
AX88190
PCMCIA Fast Ethernet Controller
Memory Mapping
There four memory mapping used AX88190. EEPROM Memory Mapping Attribute Memory Mapping Mapping Local Memory Mapping
EEPROM Memory Mapping
EEPROM OFFSET EEPROM Memory Mapping HIGH BYTE RESERVED NODE-ID1 NODE NODE CHECKSUM RESERVED BYTE WORD COUNT NODE NODE NODE RESERVED RESERVED
Attribute Memory Mapping
ATTRIBUTE MEMORY OFFSET 0000H 03BFH 03C0H 03C2H 03C4H 03C6H 03CAH 03CCH 03CEH 03DFH 03E0H 03E2H 03E4H 03E6H 03EAH 03ECH 03EEH 03FFH Attribute Memory Mapping CONTENTS LCOR LCCSR LIOBASE0 LIOBASE1 RESERVED MCOR MCCSR MIOBASE0 MIOBASE1 RESERVED
ASIX ELECTRONICS CORPORATION
AX88190 Mapping
SYSTEM OFFSET 0000H 001FH Address Mapping
PCMCIA Fast Ethernet Controller
FUNCTION CORE REGISTER
SRAM Memory Mapping
OFFSET 0000H 03BFH 03C0H 03C2H 03C4H 03C6H 03CAH 03CCH 03CEH 03DFH 03E0H 03E2H 03E4H 03E6H 03EAH 03ECH 03EEH 03FFH 0400H 0401H 0402H 0403H 0404H 0405H 0406H 07FFH 0800H FFFFH FUNCTION LCOR LCCSR LIOBASE0 LIOBASE1 RESERVED MCOR MCCSR MIOBASE0 MIOBASE1 RESERVED NODE NODE NODE NODE NODE NODE RESERVED SRAM BUFFER
Local Memory Mapping
ASIX ELECTRONICS CORPORATION
AX88190
PCMCIA Fast Ethernet Controller
Registers Operation
There four register sets AX88190 PCMCIA function configuration registers LAN. PCMCIA function configuration registers MODEM. core register. special registers.
PCMCIA Function Configuration Register
REGISTER LCOR LCSR LIOBASE0 LIOBASE1 NAME CONFIGURATION OPTION REGISTER CONFIGURATION STATUS REGISTER BASED REGISTER BASED REGISTER OFFSET 3C0H 3C2H 3CAH 3CCH
PCMCIA Function Configuration Register Mapping
ASIX ELECTRONICS CORPORATION
AX88190
PCMCIA Fast Ethernet Controller
4.1.1 Configuration Option Register (LCOR) Offset 3C0H (Read/Write)
FIELD R/W/C DESCRIPTION Software Reset Assert this will reset function AX88190. Return this will leave function AX88190 post-reset state same that following hardware reset. value this power-on. Level This should AX88190 always generates Level Mode Interrupt. Function Configuration Index These bits used indicate entry card configuration table locate CIS. default value multifunction Card, MODEM base registers MODEM base Decided MIOBASE registers section 4.2.3 2f8H 3e8H 2e8H Enable Power Down mode LCOR this ignored. LCOR this will into power down mode. power down mode AX88190 will disable transmitting receiving operation. host interface will affected. Enable IREQ# Routing LCOR this ignored. LCOR this will generate interrupt request IREQ# signal. this will generate interrupt request IREQ# line. Enable Base Limit Registers LCOR this ignored. LCOR this 1,only addresses that qualified Base Limit registers passed function. this 0,all addresses passed function. Enable Function this function disabled. this function enabled.
ASIX ELECTRONICS CORPORATION
AX88190
PCMCIA Fast Ethernet Controller
4.1.2 Configuration Status Register (LCSR) Offset 3C2H (Read/Write)
FIELD R/W/C DESCRIPTION Reserved PPwrDwn power down setting While this PPWDN (pin 114) will active force chip into power down mode. PPWDN active high active low. Please refer section Power configuration setup signal cross reference table. Intr Interrupt Request function will this when need interrupt service when request interrupt service. IntrAck Interrupt Acknowledge This will Intr will reflect status interrupt requesting.
4.1.3 Base Register (LIOBASE0/1) Offset 3CAH/3CCH (Read/Write)
Base registers (LIOBASE0 LIOBASE1) determine base address range used access specific registers (MAC Core Registers). Base Register
FIELD R/W/C Base address DESCRIPTION
Base Register
FIELD R/W/C Base address DESCRIPTION
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AX88190
PCMCIA Fast Ethernet Controller
PCMCIA Function Configuration Register MODEM
REGISTER MCOR MCSR MIOBASE0 MIOBASE1 NAME CONFIGURATION OPTION REGISTER CONFIGURATION STATUS REGISTER BASED REGISTER BASED REGISTER OFFSET 3E0H 3E2H 3EAH 3ECH
PCMCIA Function Configuration Register Mapping MODEM
4.2.1 Configuration Option Register MODEM (MCOR) Offset 3E0H (Read/Write)
FIELD R/W/C DESCRIPTION Software Reset Assert this will reset MODEM function AX88190. Return this will leave MODEM function AX88190 post-reset state same that following hardware reset. value this power-on. Level This should AX88190 always generates Level Mode Interrupt. Function Configuration Index These bits used indicate entry card configuration table locate CIS. default value multifunction Card, Bit4 Reserved IREQ# route STSCHG# MCOR this ignored. both MCOR this MODEM will route interrupt request STSCHG# signal. this MODEM will generate interrupt request IREQ# line. Enable IREQ# Routing MCOR this ignored. MCOR this MODEM will generate interrupt request IREQ# signal. this MODEM will generate interrupt request IREQ# line. Enable Base Limit Registers MCOR this ignored. MCOR this 1,only addresses that qualified Base Limit registers passed MODEM function. this 0,all addresses passed function. Enable Function this MODEM function disabled. this MODEM function enabled.
ASIX ELECTRONICS CORPORATION
AX88190
PCMCIA Fast Ethernet Controller
4.2.2 Configuration Status Register MODEM (MCSR) Offset 3E2H (Read/Write)
FIELD R/W/C DESCRIPTION Reserved MPwrDwn Modem power down setting While this MPWDN (pin 116) will active force modem chip into power down mode. MPWDN active high active low. Please refer section Power configuration setup signal cross reference table. Intr Interrupt Request function will this when need interrupt service when request interrupt service. IntrAck Interrupt Acknowledge This will Intr will reflect status interrupt requesting.
4.2.3 Base Register MODEM (MIOBASE0/1) Offset 3EAH/3ECH (Read/Write)
Base registers (MIOBASE0 MIOBASE1) determine base address range used access MODEM specific registers. Base Register
FIELD R/W/C Base address DESCRIPTION
Base Register
FIELD R/W/C Base address DESCRIPTION
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AX88190 Registers Operation
PCMCIA Fast Ethernet Controller
registers Core 8-bit wide mapped into pages which selected Command Register. PAGE (PS1=0,PS0=0)
OFFSET READ Command Register Page Start Register PSTART Page Stop Register PSTOP Boundary Pointer BNRY Transmit Status Register Number Collisions Register Current Page Register Interrupt Status Register Current Remote Address CRDA0 Current Remote Address CRDA1 Reserved Reserved Receive Status Register Frame Alignment Errors CNTR0 Errors CNTR1 Missed Packet Errors CNTR2 Data Port IFGS1 IFGS2 MII/EEPROM Access Inter-frame (IFG) Reserved WRITE Command Register Page Start Register PSTART Page Stop Register PSTOP Boundary Pointer BNRY Transmit Page Start Address TPSR Transmit Byte Count Register TBCR0 Transmit Byte Count Register TBCR1 Interrupt Status Register Remote Start Address Register RSAR0 Remote Start Address Register RSAR1 Remote Byte Count RBCR0 Remote Byte Count RBCR1 Receive Configuration Register Transmit Configuration Register Data Configuration Register Interrupt Mask Register Data Port IFGS1 IFGS2 MII/EEPROM Access Test Register Inter-frame (IFG) Reserved
Reset
Reserved
Page Core Registers Mapping
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AX88190
PAGE (PS1=0,PS0=1)
OFFSET
PCMCIA Fast Ethernet Controller
WRITE Command Register Physical Address Register PAR0 Physical Address Register PAR1 Physical Address Register PAR2 Physical Address Register PAR3 Physical Address Register PAR4 Physical Address Register PAR5 Current Page Register Multicast Address Register MAR0 Multicast Address Register MAR1 Multicast Address Register MAR2 Multicast Address Register MAR3 Multicast Address Register MAR4 Multicast Address Register MAR5 Multicast Address Register MAR6 Multicast Address Register MAR7 Data Port Inter-frame Segment IFGS1 Inter-frame Segment IFGS2 MII/EEPROM Access Test Register Inter-frame (IFG) Reserved
READ Command Register Physical Address Register PARA0 Physical Address Register PARA1 Physical Address Register PARA2 Physical Address Register PARA3 Physical Address Register PARA4 Physical Address Register PARA5 Current Page Register Multicast Address Register MAR0 Multicast Address Register MAR1 Multicast Address Register MAR2 Multicast Address Register MAR3 Multicast Address Register MAR4 Multicast Address Register MAR5 Multicast Address Register MAR6 Multicast Address Register MAR7 Data Port Inter-frame Segment IFGS1 Inter-frame Segment IFGS2 MII/EEPROM Access Inter-frame (IFG) Reserved
Reset
Reserved
Page Core Registers Mapping
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AX88190
FIELD
PCMCIA Fast Ethernet Controller
4.3.1 Command Register (CR) Offset (Read/Write)
NAME DESCRIPTION PS1,PS0 PS1,PS0 Page Select selects which register page accessed. page page RD2,RD1 RD2,RD1,RD0 Remote Command ,RD0 These three encoded bits control operation Remote channel. could abort Remote command process. reset AX88190 when Remote been completed. Remote Byte Count should cleared when Remote been aborted. Remote Start Address restored starting address Remote aborted. allowed Remote Read Remote Write allowed Abort Complete Remote Transmit Packet This could initiate transmission packet START START This used active AX88190 operation. STOP STOP Stop AX88190 This used stop AX88190 operation.
4.3.2 Interrupt Status Register (ISR) Offset (Read/Write)
FIELD NAME DESCRIPTION Reset Status when AX88190 enters reset state cleared when start command issued Writing this effect. Remote Complete when remote operation been completed Counter Overflow when more Tally Counters been set. OVERWRITE when receive buffer ring storage resources have been exhausted. Transmit Error when packet transmitted with more following errors Excessive collisions FIFO Under-run Receive Error Indicates that packet received with more following errors error Frame Alignment Error FIFO Overrun Missed Packet Packet Transmitted Indicates packet transmitted with error Packet Received Indicates packet received with error.
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AX88190
FIELD NAME RDCE CNTE OVWE TXEE RXEE PTXE PRXE
PCMCIA Fast Ethernet Controller
4.3.3 Interrupt mask register (IMR) Offset (Write)
DESCRIPTION Reserved Complete Interrupt Enable. Default "low" disabled. Counter Overflow Interrupt Enable. Default "low" disabled. Overwrite Interrupt Enable. Default "low" disabled. Transmit Error Interrupt Enable. Default "low" disabled. Receive Error Interrupt Enable. Default "low" disabled. Packet Transmitted Interrupt Enable. Default "low" disabled. Packet Received Interrupt Enable. Default "low" disabled.
4.3.4 Data Configuration Register (DCR) Offset (Write)
FIELD NAME DESCRIPTION RDCR Remote always completed Reserved Byte Order Select byte placed AD15:AD8 byte AD7-AD0 (80X86). byte placed AD7::AD0 byte AD15:AD0(68K) Word Transfer Select Selects byte-wide transfers. Selects word-wide transfers.
4.3.5 Transmit Configuration Register (TCR) Offset (Write)
FIELD NAME DESCRIPTION Full Duplex This indicates current media mode Full Duplex not. Half duplex Full duplex Disable will added when packet length less than will added when packet length less than Retry late collision Don't retransmit packet when late collision happens. Retransmit packet when late collision happens. Reserved LB1,LB0 Encoded Loop-back Control These encoded configuration bits type loop-back that performed. Mode Normal operation Mode Internal loop-back Mode PHYcevisor loop-back Inhibit appended transmitter. inhibited transmitter.
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AX88190
FIELD
PCMCIA Fast Ethernet Controller
4.3.6 Transmit Status Register (TSR) Offset (Read)
NAME DESCRIPTION window collision Reserved Transmit Aborted Indicates AX88190 aborted transmission because excessive collision. Transmit Collided Indicates that transmission collided least once with another station network. Reserved Packet Transmitted Indicates transmission without error.
4.3.7 Receive Configuration (RCR) Offset (Write)
FIELD NAME DESCRIPTION Reserved INTT Interrupt Trigger Mode Must setting "1". Monitor Mode Normal Operation Monitor Mode, input packet will checked NODE ADDRESS buffered into memory. Promiscuous Mode Enable receiver accept packets with physical address. Accept Multicast Enable receiver accept packets with multicast address. That multicast address must pass hashing array. Accept Broadcast Enable receiver accept broadcast packet. Accept Runt Enable receiver accept runt packet. Save Error Packet Enable receiver accept save packets with error.
4.3.8 Receive Status Register (RSR) Offset (Read)
FIELD NAME DESCRIPTION Reserved Receiver Disabled Multicast Address Received. Missed Packet FIFO Overrun Frame alignment error. error. Packet Received Intact
4.3.9 Inter-frame (IFG) Offset (Read/Write)
FIELD NAME DESCRIPTION Reserved Inter-frame Gap. Default value 15H.
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AX88190
FIELD
PCMCIA Fast Ethernet Controller
4.3.10 Inter-frame Segment 1(IFGS1) Offset (Read/Write)
NAME DESCRIPTION Reserved Inter-frame Segment Default value 0cH.
4.3.11 Inter-frame Segment 2(IFGS2) Offset (Read/Write)
FIELD NAME DESCRIPTION Reserved Inter-frame Segment Default value 11H.
4.3.12 MII/EEPROM Management Register (MEMR) Offset (Read/Write)
FIELD NAME DESCRIPTION EECLK EECLK: EEPROM Clock (Read only) EEPROM Data value. That reflects Pin-109 EEDO value. EEPROM Data That output Pin-108 EEDI EEPROM data input value. EECS EECS EEPROM Chip Select Data MDI: (Read only) Data That reflects Pin-91 MDIO value. MDIR MDIO signal Direction Read Control Bit, assert this MDIO signal input signal. Deassert this MDIO output signal. Clock
4.3.13 Test Register (TR) Offset (Write)
FIELD NAME TF16T DESCRIPTION Reserved Test Collision Test Enable Select Test Pins Output
ASIX ELECTRONICS CORPORATION
AX88190
PCMCIA Fast Ethernet Controller
PCMCIA Device Access Functions
AX88190 PCMCIA device needs support both Attribute Memory access function access function. Access methods described following sections.
Attribute Memory access function functions.
Attribute Memory Read function Function Mode REG# Standby Mode Byte Access bits) Word Access bits) Byte Only Access Attribute Memory Write function Function Mode REG# Standby Mode Byte Access bits) Word Access bits) Byte Only Access CE2# CE1# SD[15:8] High-Z High-Z High-Z Valid Valid SD[7:0] High-Z Even-Byte Valid Even-Byte High-Z
CE2#
CE1#
SD[15:8]
SD[7:0] Even-Byte Even-Byte
access function functions.
Read function Function Mode Standby Mode Byte Access bits) Word Access bits) Inhibit Byte Only Access Write function Function Mode Standby Mode Byte Access bits) Word Access bits) Inhibit Byte Only Access REG# CE2# CE1# SD[15:8] High-Z High-Z High-Z Odd-Byte High-Z Odd-Byte SD[7:0] High-Z Even-Byte Odd-Byte Even-Byte High-Z High-Z
REG#
CE2#
CE1#
IORD# IOWR#
SD[15:8] Odd-Byte Odd-Byte
SD[7:0] Even-Byte Odd-Byte Even-Byte
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AX88190
PCMCIA Fast Ethernet Controller
Electrical Specification Timings
Absolute Maximum Ratings
Units +150 HVdd -0.3 LVdd -0.3 +4.6 HVin -0.3 HVdd+0.5 LVin -0.3 LVdd+0.5 Output Voltage HVout -0.3 HVdd+0.5 LVin -0.3 LVdd+0.5 Lead Temperature (soldering seconds maximum) +220 Note Stress above those listed under Absolute Maximum Ratings cause permanent damage device. Exposure Absolute Maximum Ratings conditions extended period, adversely affect device life reliability. Note power supply voltages must always fulfill HVdd LVdd inequality. Operating Temperature Storage Temperature Supply Voltage Supply Voltage Input Voltage Description
General Operation Conditions
Description Operating Temperature Supply Voltage HVdd +4.75V LVdd +2.70 +3.00 +5.00V +3.00 +3.30 +5.25V +3.30 +3.60 Units
Note power supply voltages must always fulfill HVdd LVdd inequality.
Characteristics
(Vdd=5.0V, Vss=0V, Ta=0°C 75°C) Description Input Voltage High Input Voltage Output Voltage High Output Voltage Input Leakage Current Output Leakage Current (Vdd=3.0V 3.6V, Vss=0V, Ta=0°C 75°C) Description Input Voltage High Input Voltage Output Voltage High Output Voltage Input Leakage Current Output Leakage Current Description Power Consumption (Dual power) Power Consumption (Single power 3.3V) Vdd-0.4 Units
DPt5v DPt3v SPt3v
Vdd-0.4
Units Units
ASIX ELECTRONICS CORPORATION
AX88190
PCMCIA Fast Ethernet Controller
A.C. Timing Characteristics
6.4.1 XTAL CLOCK
Thigh LCLK/XTALIN
Tcyc
Tlow
CLK25M
Symbol
Tcyc Thigh Tlow Tr/Tf
Description
CYCLE TIME HIGH TIME TIME SLEW RATE LCLK/XTALIN CLK25M DELAY
Typ.
Units
6.4.2 Reset Timing
LCLK RESET
Symbol
Trst Reset pulse width
Description
Typ.
Units LClk
ASIX ELECTRONICS CORPORATION
AX88190
PCMCIA Fast Ethernet Controller
6.4.3 Attribute Memory Read Timing
Ta(A) A[9:0], REG# Ta(CE) Tsu(CE) Tsu(A) Ta(OE) Th(CE) Tv(A) Th(A)
Tv(WT-OE) WAIT# Ten(OE) D[15:0]
Tw(WT)
Tdis(CE)
Tv(WT)
Tdis(OE) DATA Valid
Symbol
Ta(A) Ta(CE) Ta(OE) Tdis(OE) Ten(OE) Tv(A) Tsu(A) Th(A) Tsu(CE) Th(CE) Tv(WT-OE) Tw(WT) Tv(WT)
Description
READ CYCLE TIME ADDRESS ACCESS TIME CARD ENABLE ACCESS TIME OUTPUT ENABLE ACCESS TIME OUTPUT DISABLE TIME FROM OUTPUT ENABLE TIME FROM DATA VALID FROM ADDRESS CHANGE ADDRESS SETUP TIME ADDRESS HOLD TIME CARD ENABLE SETUP TIME CARD ENABLE HOLD TIME WAIT# VALID FROM WAIT# PULSE WIDTH DATA SETUP WAIT# RELEASED
Typ.
Units
ASIX ELECTRONICS CORPORATION
AX88190
PCMCIA Fast Ethernet Controller
6.4.4 Attribute Memory Write Timing
A[9:0], REG# Tsu(CE-WEH) Tsu(CE) Tsu(A-WEH) Tsu(A) Tv(WT-WE) Tw(WT) WAIT# Tsu(OE-WE) D[15:0](Din) Tdis(WE) Tdis(OE) D[15:0](Dout) Tsu(D-WEH) DATA Input Establish Ten(OE) Ten(WE) Th(D) Tv(WT) Th(OE-WE) Tw(WE) Trec(WE) Th(CE)
Symbol
Tw(WE) Tsu(A) Tsu(A-WEH) Tsu(CE-WEH) Tsu(D-WEH) Th(D) Trec(WE) Tdis(WE) Tdis(OE) Ten(WE) Ten(OE) Tsu(OE-WE) Th(OE-WE) Tsu(CE) Th(CE) Tv(WT-WE) Tw(WT) Tv(WT)
Description
WRITE CYCLE TIME WRITE PULSE WIDTH ADDRESS SETUP TIME ADDRESS SETUP TIME CARD ENABLE SETUP TIME DATA SETUP TIME DATA HOLD TIME WRITE RECOVER TIME OUTPUT DISABLE TIME FROM OUTPUT DISABLE TIME FROM OUTPUT ENABLE TIME FROM OUTPUT ENABLE TIME FROM OUTPUT ENABLE SETUP TIME FROM OUTPUT ENABLE HOLD TIME FROM CARD ENABLE SETUP TIME CARD ENABLE HOLD TIME WAIT# VALID FROM WAIT# PULSE WIDTH HIGH FROM WAIT# RELEASED
Typ.
Units
ASIX ELECTRONICS CORPORATION
AX88190
6.4.5 Read Timing
A[9:0]
PCMCIA Fast Ethernet Controller
TsuREG REG#
ThREG
TsuCE IORD# TsuA
ThCE
TdrINPACK
INPACK# TdfINPACK TdrIOIS16
IOIS16# TdfIOIS16 Tdr(WT) WAIT# TdfWT Tw(WT)
D[15:0]
DATA Valid
Symbol
TsuA TsuCE ThCE TsuREG ThREG TdfINPACK TdrINPACK TdfIOIS16 TdrIOIS16 TdfWT Tdr(WT) Tw(WT)
Description
DATA DELAY AFTER IORD# DATA HOLD FOLLOWING IORD# IORD# WIDTH TIME ADDRESS SETUP BEFORE IORD# ADDRESS HOLD BEFORE IORD# SETUP BEFORE IORD# HOLD BEFORE IORD# REG# SETUP BEFORE IORD# REG# HOLD BEFORE IORD# INPACK# DELAY FALLING FROM IORD# INPACK# DELAY RISING FROM IORD# IOIS16# DELAY FALLING FROM ADDRESS* IOIS16# DELAY RISING FROM ADDRESS* WAIT# DELAY FALLING FROM IORD# DATA DELAY FROM WAIT# RISING WAIT# WIDTH TIME
Typ.
Units
Note address includes REG# CE1# signal
ASIX ELECTRONICS CORPORATION
AX88190
6.4.6 Write Timing
A[9:0]
PCMCIA Fast Ethernet Controller
TsuREG REG#
ThREG
TsuCE IOWR# TsuA
ThCE
TdrIOIS16
IOIS16# TdfIOIS16 TdrIOWR WAIT# TdfWT Tw(WT) D[15:0] DATA
Symbol
TsuA TsuCE ThCE TsuREG ThREG TdfIOIS16 TdrIOIS16 TdfWT Tw(WT) TdrIOWR
Description
DATA SETUP BEFORE IOWR# DATA HOLD FOLLOWING IOWR# IOWR# WIDTH TIME ADDRESS SETUP BEFORE IOWR# ADDRESS HOLD BEFORE IOWR# SETUP BEFORE IOWR# HOLD BEFORE IOWR# REG# SETUP BEFORE IOWR# REG# HOLD BEFORE IOWR# IOIS16# DELAY FALLING FROM ADDRESS* IOIS16# DELAY RISING FROM ADDRESS* WAIT# DELAY FALLING FROM IOWR# WAIT# WIDTH TIME IOWR# HIGH FROM WAIT# HIGH
Typ.
Units
*Note address includes REG# CE1# signal Note There wait state while Write operation
ASIX ELECTRONICS CORPORATION
AX88190
6.4.7 Timing
PCMCIA Fast Ethernet Controller
Ttclk
Ttch
Ttcl
TXCLK TXD<3:0>
TXEN Trclk Trch Trcl
RXCLK RXD<3:0>
RXDV Trs1 RXER
Symbol
Ttclk Ttclk Ttch Ttch Trch Trch Trclk Trclk Trch Trch Trcl Trcl Trs1
Description
Cycle time(100Mbps) Cycle time(10Mbps) high time(100Mbps) high time(10Mbps) time(100Mbps) time(10Mbps) Clock data valid Data output hold time Cycle time(100Mbps) Cycle time(10Mbps) high time(100Mbps) high time(10Mbps) time(100Mbps) time(10Mbps) data setup time data hold time RXER data setup time
Typ.
Units
ASIX ELECTRONICS CORPORATION
AX88190
MEMORY WRITE
PCMCIA Fast Ethernet Controller
6.4.8 Asynchronous Memory Access Timing
Tsu(A) MEMA[15:1] Tw(WR) /MEMWR Td(WtoR) Tw(RDdis) /MEMRD Tsu(D) Write Data SD[15:0](Dout) DATA Valid Th(D) Th(A)
Symbol
Tsu(A) Th(A) Tw(WR) Tw(RDdis) Td(WtoR) Tsu(D) Th(D)
Description
ADDRESS SETUP TIME ADDRESS HOLD TIME WRITE PULSE WIDTH READ DISABLE PULSE WIDTH WRITE READ DEALY DATA SETUP TIME DATA HOLD TIME
Typ.
Units
MEMORY READ
Tsu(A) MEMA[15:1] Th(A)
Referance Internal "/MEMRD"
Tw(RD)
High Level /MEMWR
Level /MEMRD Tsu(RD) Read Data MEMD[15:1] Th(RD)
Valid DATA
Typ. Units NOTE pulse width seen LCLK/XTALIN high time. also 6.4.1 "Thigh" parameter. NOTE most brand asynchronous SRAM access time under into specification.
Tsu(A) Th(A) Tw(RD) Tsu(D) Th(D) ADDRESS SETUP TIME ADDRESS HOLD TIME READ PULSE WIDTH DATA SETUP TIME DATA HOLD TIME
Symbol
Description
ASIX ELECTRONICS CORPORATION
AX88190
PCMCIA Fast Ethernet Controller
Package Information
SYMBOL MIN.
15.60 15.60 0.30 0.155 13.90 13.90
MILIMETER
0.16 14.00 14.00 0.40 16.00 16.00 0.50 1.00 16.40 16.40 0.70 0.26 14.10 14.10
ASIX ELECTRONICS CORPORATION
AX88190
PCMCIA Fast Ethernet Controller
Appendix Application Note
Using Crystal
AX88190
CLKO25M
XTALIN XTALOUT 25MHz Crystal
2Mohm
Note capacitors (8pf) various depend specification crystal. While designing, please refer suggest circuit provided crystal supplier.
Using Oscillator
AX88190
CLKO25M
XTALIN
XTALOUT
3.3V Power
25MHz
ASIX ELECTRONICS CORPORATION
AX88190
PCMCIA Fast Ethernet Controller
Dual power 3.3V) application
RJ11
RJ45
MAGNETIC
MODEM
PHY/TxRx
+3.3V (option core logic) EEPROM
HVdd AX88190
+3.3V LVdd
SRAM
PCMCIA
Single power (3.3V) application
RJ11
RJ45
MAGNETIC
+3.3V
MODEM
PHY/TxRx
+3.3V
+3.3V HVdd +3.3V LVdd AX88190
EEPROM SRAM
+3.3V +3.3V
+3.3V PCMCIA
ASIX ELECTRONICS CORPORATION
AX88190
PCMCIA Fast Ethernet Controller
Dual power 3.3V) application with 3.3V
resisters just voltage adjustment
RXD[3:0] RX_DV RX_ER RX_CLK TX_EN TXD[3:0] TX_CLK MDIO AX88190
RXD[3:0] RX_DV RX_ER RX_CLK TX_EN TXD[3:0] TX_CLK MDIO
ASIX ELECTRONICS CORPORATION
AX88190
PCMCIA Fast Ethernet Controller
Appendix Application Note
Advance Application Using Crystal
Date: 1999
Condition: short cable, AX88190 Phyceiver can't link 5308 Switch. Conclusion: After measuring verifying, found it's relevant clock source. ascertain problem caused matching issues between crystal capacitor. Solution: Change value capacitors beside crystal below:
25MHZ XOUT
Note: capacitors various depend specification crystal. While designing, please refer circuit provided crystal supplier.
ASIX ELECTRONICS CORPORATION
AX88190
PCMCIA Fast Ethernet Controller Errata AX88190
synchronous problem result hang Solution Using hardware pre-sync signal below.
From AX88190
CLK25M 74F86
74F74
OE_#
74F74
OE_M#
From PCMCIA Connector
AX88190
Jumper future
Interrupt Status can't always clean Solution Using software clean check iteration until clean IOBASE=300 Clear Tx/Rx interrupt. dx,307h ClrISR al,3 dx,al al,dx Test al,3 ClrISRDone al,0 dx,al ClrISR clear Tx/Rx interrupt output clear read Check cleared Clear not, clear again
ClrISRDone:
clear successful
CE1# decoder problem Solution Dis-connect AX88190 CE1# (pin from PCMCIA connector CE1# (pin connect AX88190 CE1# (pin logic always enable this signal.
ASIX ELECTRONICS CORPORATION
ASIX
(AX88190 APPLICATION USED LUC6612) CE1# IREQ# VPP1 IOIS16# PCMCIA CD1# CE2# VS1# IORD# VPP2 VS2# RESET WAIT# INPACK# REG# SPKR# STSCHG# CD2# SD11 SD12 SD13 SD14 SD15 CE2# IORD# IREQ#
AX88190 PCMCIA Fast Ethernet Controller
MEMRD# MA12 MA10 MA14 MA15 MA13 IS61C256AH RESET# LVDD EEDO EEDI EESK EECS LVDD (OPTION TEST) MEMRD# MA12 MA10 MA14 MA15 MA13 IS61C256AH I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 MA11 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 MA11 MD15 MD14 MD13 MD12 MD11 MD10
IREQ# IORD# OE_M# CE2# SD15 SD14 SD13 SD12 SD11 SD10 MEMRD# MA15 LVDD MA14 MA13 MA12 MA11 MA10 LVDD MD15 MD14 SA[0] SA[1] SA[2] SA[3] SA[4] SA[5] SA[6] SA[7] SA[8] SA[9] IREQ# IORD# CE2# CE1# SD[15] SD[14] SD[13] SD[12] SD[11] SD[10] SD[9] SD[8] SD[7] SD[6] SD[5] SD[4] SD[3] SD[2] SD[1] SD[0] MEMRD# MEMA[15] LVDD MEMA[14] MEMA[13] MEMA[12] MEMA[11] MEMA[10] MEMA[9] MEMA[8] MEMA[7] LVDD MEMA[6] MEMA[5] MEMA[4] MEMA[3] MEMA[2] MEMA[1] MEMD[15] MEMD[14] LVDD RESET LVDD WAIT# INPACK# REG# SPKR# STSCHG# IOIS16# MRDY MRESET# MAUDIO MINT LVDD EEDO EEDI EECK EECS TALOUT LCLK/XT ALIN CLKO25M LVDD TXD[3] TXD[2] TXD[1] TXD[0] _CLK MDIO RXD[3] RXD[2] RXD[1] RXD[0] MEMD[0] MEMD[1] MEMD[2] MEMD[3] MEMD[4] MEMD[5] MEMD[6] MEMD[7] MEMD[8] MEMD[9] MEMD[11] MEMD[11] MEMD[12] MEMD[13] LVDD RESET LVDD WAIT# INPACK# REG# SPKR# STSCHG# IOIS16#
IOIS16#
RESET WAIT# INPACK# REG# SPKR# STSCHG# SD10
MDIO PCLK
PCLK
74F86
EECS EESK EEDI EEDO 93C56R
74F74
25MHZ
.7u/16V 0.01u .7u/16V 0.01u XC62FP .7u/16V 0.01u LVDD .7u/16V 0.01u Size Date: Document Number 190LU1A. Tuesday, December 1998 Sheet Title AX88190 MEMORY LVDD .7u/16V ASIX TRONICS CORPORATION 0.01u |LINK |190LU1A1.SCH
ASIX ELECTRONICS CORPORATION
NO.13, Industry East Science-based Industrial Park, Hsin-Chu City, Taiwan, R.O.C. TEL: 886-3-579-9500 FAX: 886-3-579-9558 http://www.asix.com.tw
MD10 MD11 MD12 MD13
OE_M#
74F74
AX88190
24.9K VDDA LLED ALED VDDA 1000p VDDA PAD4 VDDPLL MDIO RESET# 22.1K PCLK
PCMCIA Fast Ethernet Controller
VCCBG ISET_100 GNDBG LED_LINK/PHAD0 LED_ACT/PHAD1 VCCIOA GNDIOA TDGNDT VCCT CLKREF GNDBT VCCBT TEST0 TEST1 PHAD4 PCSEN# TEST2 VCCPLL LSCLK1 LSCLK2 GNDPLL ISET_10 MDIO RESET# TX_ER/T LUC6612 GNDEQAP RDVCCEQAP VCCREC GNDREC BGREF0 BGREF1 LED_SPD/PHAD2 LED_FDX/PHAD3 VCCIOB GNDIOB MODE2 MODE1 MODE0 VCCDIGB GNDDIGB GNDIOC GNDDIGA VCCDIGA VDDA SLED FLED 24.9k 24.9K ADDRESS 10000 PAD4 PHYAD4 FLED PHYAD3 SLED PHYAD2 ALED PHYAD1 LLED PHYAD0 PCMJ15 Connect FLED SLED ALED LLED FDLED SPLED ACLED LILED
PASS WITH DIGITAL POWER SUPPLY
0.01u 0.1u 0.1u 0.1u 0.1u 0.1u
4.7u/16V
49.9 49.9
PASS WITH ANALOG POWER SUPPLY 0.1u 4.7u/16V VDDA 0.01u PCMJ15 Size Date: 0.1u 0.1u 0.1u 0.1u 0.1u
49.9 49.9
TDRD+ RDCT 14ST9012P
0.1u ASIX TRONICS Title LUC6612 Document Number 190LU1A1.SCH Tuesday, December 1998 Sheet VDDPLL
0.01u 0.01u 0.01u
SPLED LILED ACLED FDLED
0.01u/2KV CHASSIS
0.01u
ASIX ELECTRONICS CORPORATION
AX88190
CON12
PCMCIA Fast Ethernet Controller
RJ45N
SPLED
CHASSIS 0.01
LILED
ACLED
FDLED
ASIX ELECTRONICS CORPORATION Title RJ45 Size Date: Document Number 190LED.SCH Tuesday December 1998 Sheet
ASIX ELECTRONICS CORPORATION
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