AMERICAN MICROSYSTEMS, June, 1998 Preliminary Differential F
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CMLDF021
AMERICAN MICROSYSTEMS,
June, 1998 Preliminary
Differential Flip Flop with Features limited voltage swing useful noise applications positive edge triggered asynchronous input Description high speed, low-power positive edge triggered flip flop. Limited voltage swing implemented reduce power consumption noise transients characteristic common CMOS rail-to-rail outputs. Useful frequency synthesis circuits. Requires voltage reference.
micron CMOS
micron CMOS
Dinf clkf
Differential Flip Flop
VREF
DESCRIPTION
NAME TYPE Digital Input Digital Input Digital Output Digital Supply Digital Input Digital Output Digital Output Analog input Digital Supply Digital Supply Digital data input (true) Digital data input (false) Digital clock input (true) Digital clock input (false) Digital data input Digital output (true) Digital output (false) Voltage reference current mirror supply 3.6V) Digital ground DESCRIPTION
Dinf clkf VREF
ELECTRICAL CHARACTERISTICS Unless otherwise stated 25°C,
SYMBOL ftog tSET tHOLD PARAMETER Power supply voltage Range current consumption Toggle frequency Setup time Hold time input pulse width Output voltage fCL= 100Mhz, clock inputs =0.5 VIH=2.0 typical, =0.87 VOH=1.45 worst case models worst case models worst case models CONDITIONS UNITS
1.72
1.90
CMLDF021
AMERICAN MICROSYSTEMS,
June, 1998 Preliminary
Output high voltage worst case models worst case models worst case models worst case models Data inputs only Input high voltage Input voltage Clock inputs only Input high voltage Input voltage
micron CMOS
0.56 0.60
Load 50/0.6 NFET connected each output.
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