28F800C3, 28F160C3, 28F320C3, 28F640C3 (x16) Flexible SmartVoltag
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Volt Advanced+ Boot Block Flash Memory
28F800C3, 28F160C3, 28F320C3, 28F640C3 (x16)
Flexible SmartVoltage Technology V-3.6 Read/Program/Erase Fast Production Programming High Performance V-3.6 Access Time Optimized Architecture Code Plus Data Storage Eight 4-Kword Blocks, Bottom Locations Hundred-Twenty-Seven 32Kword Blocks Fast Program Suspend Capability Fast Erase Suspend Capability Flexible Block Locking Lock/Unlock Block Full Protection Power-Up Hardware Block Protection Option Lockout Voltage Power Consumption Typical Read Power Typical Standby Power with Automatic Power Savings Feature Fast Production Program Extended Temperature Operation
128-bit Protection Register 64-bit Unique Device Identifier 64-bit User Programmable Cells Extended Cycling Capability Minimum 100,000 Block Erase Cycles Supports Intel® Flash Data Integrator Software Flash Memory Manager System Interrupt Manager Supports Parameter Storage, Streaming Data (e.g., voice) Automated Word/Byte Program Block Erase Command User Interface Status Registers Cross-Compatible Command Support Intel Basic Command Common Flash Interface Standard Surface Mount Packaging 48-Ball Packages 64-Ball Easy Packages 48-Lead TSOP Package ETOXVII (0.18 Flash Technology 28F160/320/640C3xC 32-Mbit also exist ETOXVI (0.25 Flash Technology
Volt Advanced+ Boot Block Flash memory, manufactured Intel's latest 0.18 technology, represents feature-rich solution power applications. Volt Advanced+ Boot Block Flash memory devices incorporate voltage capability (2.7 read, program erase) with high-speed, low-power operation. Flexible block locking allows block independently locked unlocked. this Intel® Flash Data Integrator (IFDI) software have cost-effective, flexible, monolithic code plus data storage solution. Intel® Volt Advanced+ Boot Block products will available 48-lead TSOP, 48-ball CSP, 64-ball Easy packages. Additional information this product family obtained accessing Intel® Flash website:
Notice: This document contains preliminary information products production. specifications subject change without notice. Verify with your local Intel sales office that have latest datasheet before finalizing design.
Order Number: 290645-010 October 2000
Information this document provided connection with Intel® products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. 28F800C3, 28F160C3, 28F320C3, 28F640C3 contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata available request. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature obtained calling 1-800548-4725 visiting Intel's website http://www.intel.com. Copyright Intel Corporation, 1998 2000. *Other brands names property their respective owners.
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Contents
Introduction
Product Overview Package Pinouts Block Organization 2.2.1 Parameter Blocks 2.2.2 Main Blocks Operation 3.1.1 Read. 3.1.2 Output Disable. 3.1.3 Standby 3.1.4 Reset 3.1.5 Write Modes Operation. 3.2.1 Read Array 3.2.2 Read Configuration 3.2.3 Read Status Register 3.2.4 Read Query 3.2.5 Program Mode.11 3.2.6 Erase Mode Flexible Block Locking.15 3.3.1 Locking Operation 3.3.2 Unlocked State 3.3.3 Lock-Down State 3.3.4 Reading Block's Lock Status 3.3.5 Locking Operations during Erase Suspend.17 3.3.6 Status Register Error Checking.17 128-Bit Protection Register 3.4.1 Reading Protection Register 3.4.2 Programming Protection Register 3.4.3 Locking Protection Register Program Erase Voltages 3.5.1 Improved Volt Production Programming 3.5.2 VPPLK Complete Protection.20 Power Consumption 3.6.1 Active Power (Program/Erase/Read) 3.6.2 Automatic Power Savings (APS).21 3.6.3 Standby Power 3.6.4 Deep Power-Down Mode Power-Up/Down Operation 3.7.1 Connected System Reset.21 3.7.2 VCC, Transitions Power Supply Decoupling
Product Description
Principles Operation
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Electrical Specifications.
Absolute Maximum Ratings Operating Conditions Capacitance Characteristics Characteristics, Continued. Characteristics-Read Operations. Characteristics-Write Operations. Erase Program Timings Reset Operations
Ordering Information Additional Information Current/Next States Program/Erase Flowcharts Common Flash Interface Query Structure Architecture Block Diagram Word-Wide Memory Diagrams. Device Table Protection Register Addressing
Appendix Appendix Appendix Appendix Appendix Appendix Appendix
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Revision History
Date Revision 05/12/98 Version -001 Original version 48-Lead TSOP package diagram change µBGA package diagrams change 32-Mbit ordering information change (Section Query Structure Output Table Change (Table Primary-Vendor Specific Extended Query Table Change Optional Features Command Support change (Table Protection Register Address Change IPPD test conditions clarification (Section 4.3) µBGA package side mark information clarification (Section Byte-Wide Protection Register Address change Specification change (Section 4.3) Maximum Specification change (Section 4.3) ICCS test conditions clarification (Section 4.3) Added Command Sequence Error Note (Table Datasheet renamed from Volt Advanced Boot Block, 16-, 32-Mbit Flash Memory Family. Added tBHWH/tBHEH tQVBL (Section 4.6) Programming Protection Register clarification (Section 3.4.2) Removed references configurations Removed reference 40-Lead TSOP from front page Added Easy package (Section 1.2) Removed references Locking Operations Flowchart changed (Appendix Added tWHGL (Section 4.6) Primary Vendor-Specific Extended Query changed (Appendix ICCD changed Table added note indicating VCCMax 32-Mbit device Added specifications 0.18 micron product offerings throughout document Added 64-Mbit density Changed references 32Mbit 80ns devices 70ns devices reflect faster product offering. 10/12/00 -010 Changed VccMax=3.3V reference indicate that affected product 0.25µm 32Mbit device. Minor text edits throughout document. Description
07/21/98
-002
10/03/98
-003
12/04/98 12/31/98 02/24/99
-004 -005 -006
06/10/99
-007
03/20/00 04/24/00
-008 -009
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Introduction
This document contains specifications Volt Advanced+ Boot Block flash memory family. These flash memories features which used enhance security systems: instant block locking protection register. Throughout this document, term "2.7 refers full voltage range V-3.6 (except where noted otherwise) "VPP refers ±5%. Section Section provide overview flash memory family including applications, pinouts, descriptions memory organization. Section describes operation these products, with Section providing operating specifications. Ordering information outlined Section 5.0, additional reference material located Section 6.0. Volt Advanced+ Boot Block flash memory features:
Zero-latency, flexible block locking 128-bit Protection Register Simple system implementation production programming with in-field
programming
Ultra-low power operation Minimum 100,000 block erase cycles Common Flash Interface software query device specs features
Table
Feature Operating Voltage Voltage VCCQ Voltage Width
Volt Advanced+ Boot Block Feature Summary
Mbit(1), Mbit, Mbit(2) V(3) Provides complete write protection with optional Fast Programming 16-bit Mbit: Mbit: Mbit: 100, Mbit: 4-Kword parameter 8-Mb: 32-Kword main 16-Mb: 32-Kword main 32-Mb: 32-Kword main 64-Mb: 32-Kword main Extended: 100,000 cycles 48-Lead TSOP 48-Ball µBGA* (1), 48-Ball BGA, Easy Flexible locking block with zero latency 64-bit unique device number, 64-bit user programmable Table Reference Table Table
Speed (ns)
Section
Blocking (top bottom)
Appendix Appendix
Operating Temperature Program/Erase Cycling Packages Block Locking Protection Register
Table Table Figure Section Section
NOTES: 8-Mbit density available µBGA* CSP. Specification Update changes 32-Mbit devices (order 297938). VCCMax 0.25µm 32-Mbit devices.
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Product Overview
Intel provides secure voltage memory solutions with Advanced Boot Block family products. block locking feature allows instant locking/unlocking block with zerolatency. 128-bit protection register allows unique flash device identification. Discrete supply pins provide single voltage read, program, erase capability while also allowing faster production programming. Improved feature designed reduce external logic, simplifies board designs when combining production programming with in-field programming. Volt Advanced+ Boot Block flash memory products available packages following densities: (see Section 5.0, "Ordering Information" page
8-Mbit (8,388,608 bit) flash memories organized Kwords bits each 16-Mbit (16,777,216 bit) flash memories organized 1024 Kwords bits each 32-Mbit (33,554,432 bit) flash memories organized 2048 Kwords bits each 64-Mbit (67,108,864 bit) flash memories organized 4096 Kwords bits each
Eight 4-Kword parameter blocks located either (denoted suffix) bottom suffix) address order accommodate different microprocessor protocols kernel code location. remaining memory grouped into 64-Kbyte main blocks (see Appendix blocks locked unlocked instantly provide complete protection code data (see Section 3.3, "Flexible Block Locking" page details). Command User Interface (CUI) serves interface between microprocessor microcontroller internal operation flash memory. internal Write State Machine (WSM) automatically executes algorithms timings necessary program erase operations, including verification, thereby unburdening microprocessor microcontroller. status register indicates status signifying block erase word program completion status. Program erase automation allows program erase operations executed using industry-standard two-write command sequence CUI. Program operations performed word increments. Erase operations erase locations within block simultaneously. Both program erase operations suspended system software order read from other block. addition, data programmed another block during erase suspend. Volt Advanced+ Boot Block flash memories offer power savings features: Automatic Power Savings (APS) standby mode. device automatically enters mode following completion read cycle. Standby mode initiated when system deselects device driving inactive. Combined, these power savings features significantly reduce power consumption. device reset lowering GND. This provides CPU-memory reset synchronization additional protection against noise that occur during system reset power-up/down sequences (see Section Section 3.6). Refer Section 4.4, Characteristics" page complete current voltage specifications. Refer Section Section read write performance specifications. Program erase times shown Section 4.7.
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Product Description
This section provides device descriptions package pinouts Volt Advanced+ Boot Block flash memory family, which available 48-lead TSOP (x16) 48-ball µBGA Easy packages (Figures respectively).
Package Pinouts
Figure 48-Lead TSOP Package
VCCQ DQ15 DQ14 DQ13 DQ12 DQ11 DQ10
0645_02
Advanced+ Boot Block 48-Lead TSOP VIEW
NOTE: Lower densities will have upper address pins. example, 16-Mbit device will have Pins
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Figure 48-Ball µBGA* 48-Ball Very Thin Profile Fine Pitch Chip Size Package (Top View, Ball Down)
VCCQ
NOTES: Shaded connections indicate upgrade address connections. Lower density devices will have upper address solder balls. Routing recommended this area. upgrade address 16-Mbit device. upgrade address 32-Mbit device. upgrade address 64-Mbit device. 8-Mbit available µBGA* CSP.
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Figure Easy Package
DQ10 DQ11 DQ14 A22(2) VCCQ VSSQ VCCQ VSSQ DQ15 VCCQ VSSQ VCCQ A22(2) VSSQ DQ14 DQ11 DQ10 DQ12 A21(1) A19(1) A20(1) A21(1) A20(1) A19(1)
View Ball Side Down
Bottom View Ball Side
16fast
NOTES: denotes Mbit; denotes Mbit; denotes Mbit. indicates future density upgrade path to128 Mbit (not available).
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Table
Symbol A0-A21
Volt Advanced+ Boot Block Descriptions
Type INPUT Name Function ADDRESS INPUTS: Memory addresses internally latched during program erase cycle. 8-Mbit: A[0-18], 16-Mbit: A[0-19], 32-Mbit: A[0-20], 64-Mbit: A[0-21] DATA INPUTS/OUTPUTS: Inputs array data second cycle during Program command. Inputs commands Command User Interface when active. Data internally latched. Outputs array, configuration status register data. data pins float tri-state when chip de-selected outputs disabled. DATA INPUTS/OUTPUTS: Inputs array data second cycle during Program command. Data internally latched. Outputs array configuration data. data pins float tri-state when chip de-selected. CHIP ENABLE: Activates internal control logic, input buffers, decoders sense amplifiers. active low. high de-selects memory device reduces power consumption standby levels. OUTPUT ENABLE: Enables device's outputs through data buffers during read operation. active low. WRITE ENABLE: Controls writes command register memory array. active low. Addresses data latched rising edge second pulse. RESET/DEEP POWER-DOWN: Uses voltage levels (VIL, VIH) control reset/deep powerdown mode.
DQ0-DQ7
INPUT/ OUTPUT
DQ8-DQ15
INPUT/ OUTPUT
INPUT
INPUT INPUT
INPUT
When logic low, device reset/deep power-down mode, which drives outputs High-Z, resets Write State Machine, minimizes current levels (ICCD). When logic high, device standard operation. When transitions from logic-low logic-high, device resets blocks locked defaults read array mode. WRITE PROTECT: Controls lock-down function flexible Locking feature. When logic low, lock-down mechanism enabled blocks marked lock-down cannot unlocked through software.
INPUT
When logic high, lock-down mechanism disabled blocks previously lockeddown locked unlocked locked through software. After goes low, blocks previously marked lock-down revert that state. Section details block locking. DEVICE POWER SUPPLY: [2.7 V-3.6 Supplies power device operations. POWER SUPPLY: Supplies power input/output buffers. [2.7 V-3.6 This input should tied directly VCC. PROGRAM/ERASE POWER SUPPLY: [1.65 V-3.6 11.4 V-12.6 Operates input logic levels control complete device protection. Supplies power accelerated program erase operations range. This cannot left floating. Lower VPPLK, protect contents against Program Erase commands. in-system read, program erase operations. this configuration, drop 1.65 allow resistor diode drop from system supply. Note that driven logic signal, 1.65. That must remain above 1.65 perform insystem flash modifications. Raise faster program erase production environment. Applying only done maximum 1000 cycles main blocks 2500 cycles parameter blocks. connected total hours maximum. Section details voltage configurations.
VCCQ
SUPPLY INPUT
INPUT/ SUPPLY
SUPPLY
GROUND: internal circuitry. ground inputs must connected. CONNECT: driven left floating.
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Block Organization
Volt Advanced+ Boot Block asymmetrically-blocked architecture that enables system integration code data within single flash device. Each block erased independently others 100,000 times. address locations each block, memory maps Appendix
2.2.1
Parameter Blocks
Volt Advanced+ Boot Block flash memory architecture includes parameter blocks facilitate storage frequently updated small parameters (i.e., data that would normally stored EEPROM). Each device contains eight parameter blocks Kwords (4,096 words).
2.2.2
Main Blocks
After parameter blocks, remainder array divided into 32-Kword (32,768 words) main blocks data code storage. Each 8-Mbit, 16-Mbit, 32-Mbit, 64-Mbit device contains main blocks, respectively.
Principles Operation
Volt Advanced+ Boot Block flash memory family utilizes automated algorithms simplify program erase operations. allows 100% CMOS-level control inputs fixed power supplies during erasure programming. internal completely automates program erase operations while signals start operation status register reports status. handles interface data address latches, well system status requests during operation.
Operation
Volt Advanced+ Boot Block flash memory devices read, program erase in-system local microcontroller. cycles from flash memory conform standard microcontroller cycles. Four control pins dictate data flow flash component: CE#, OE#, RP#. These operations summarized Table page
3.1.1
Read
flash memory four read modes available: read array, read configuration, read status read query. These modes accessible independent voltage. appropriate read mode command must issued enter corresponding mode. Upon initial device powerup after exit from reset, device automatically defaults read array mode. must driven active obtain data outputs. device selection control; when active enables flash memory device. data output control drives selected memory data onto bus. read modes, must VIH. Figure Waveform: Read Operations" page illustrates read cycle.
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3.1.2
Output Disable
With logic-high level (VIH), device outputs disabled. Output pins placed high-impedance state.
3.1.3
Standby
Deselecting device bringing logic-high level (VIH) places device standby mode, which substantially reduces device power consumption without latency subsequent read accesses. standby, outputs placed high-impedance state independent OE#. deselected during program erase operation, device continues consume active power until program erase operation complete.
Table
Operations
Mode Notes 1,4,5,6 DQ0-7 DOUT High High High DQ8-15 DOUT High High High
Read (Array, Status, Configuration, Query) Output Disable Standby Reset Write
NOTES: must VIL, control pins addresses. Characteristics VPPLK, VPP1, VPP2, VPP3, voltages. Manufacturer device codes also accessed read configuration mode (A1-A20 Table page program erase lockable blocks, hold VIH. Refer Table page valid during write operation. must meet maximum deep power-down current specified. 8-bit devices only [0:7], 16-bit devices [0:15].
3.1.4
Reset
From read mode, time tPLPH deselects memory, places output drivers highimpedance state, turns internal circuits. After return from reset, time tPHQV required until initial read access outputs valid. delay (tPHWL tPHEL) required after return from reset before write initiated. After this wake-up interval, normal operation restored. resets read array mode, status register 80H, blocks locked. This case shown Figure Waveform: Reset Operations" page (section taken time tPLPH during program erase operation, operation will aborted memory contents aborted location (for program) block (for erase) longer valid, since data partially erased written. abort process goes through following sequence: When goes low, device shuts down operation progress, process which takes time tPLRH complete. After this time tPLRH, part will either reset read array mode gone high during tPLRH, Figure section enter reset mode still logic after tPLRH, Figure section both cases, after returning from aborted operation, relevant time tPHQV tPHWL/tPHEL must observed before read write operation initiated, discussed previous paragraph. However, this case, these delays referenced tPLRH rather than when goes high.
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Similar automated device, important assert during system reset. When system comes reset, processor expects read from flash memory. Automated flash memories provide status information when read during program block erase operations. reset occurs with flash memory reset, proper initialization occur because flash memory providing status information instead array data. Intel® Flash memories allow proper initialization following system reset through input. this application, controlled same RESET# signal that resets system CPU.
3.1.5
Write
write takes place when both high. Commands written Command User Interface (CUI) using standard microprocessor write timings control flash operations. does occupy addressable memory location. address data buses latched rising edge second pulse, whichever occurs first. Figure Waveform: Program Erase Operations" page available commands shown Table page Appendix provides detailed information moving between different modes operation using commands. There commands that modify array data: Program (40H) Erase (20H). Writing either these commands internal Command User Interface (CUI) initiates sequence internallytimed functions that culminate completion requested task (unless that operation aborted either being driven tPLRH appropriate suspend command).
Modes Operation
flash memory four read modes write modes. read modes read array, read configuration, read status, read query. write modes program erase. Three additional modes (erase suspend program, erase suspend read program suspend read) available only during suspended operations. These modes reached using commands summarized Tables comprehensive chart showing state transitions, Appendix
3.2.1
Read Array
When transitions from (reset) VIH, device defaults read array mode will respond read control inputs (CE#, address inputs, OE#) without additional commands. When device read array mode, four control signals control data output:
must logic high (VIH) must logic (VIL) must logic (VIL) must logic high (VIH)
addition, address desired location must applied address pins. device read array mode, would case after program erase operation, Read Array command (FFH) must written before array reads take place.
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3.2.2
Read Configuration
Read Configuration mode outputs three types information: manufacturer/device identifier, block locking status, protection register. device switched this mode writing Read Configuration command (90H). Once this mode, read cycles from addresses shown Table retrieve specified information. return read array mode, write Read Array command (FFH).
Table
Read Configuration Table
Item Manufacturer Code (x16) Device (See Appendix Block Lock Configuration(1) Block Unlocked Block Locked Block Locked-Down Protection Register Lock(3) Protection Register (x16) 81-88 Address 00000 00001 XX002(2) Data 0089 LOCK PR-LK
NOTES: Section 3.3.4 valid lock status outputs. "XX" specifies block address lock configuration being read. Section protection register information. Other locations within configuration address space reserved Intel future use.
3.2.3
Read Status Register
status register indicates status device operations, success/failure that operation. Read Status Register (70H) command causes subsequent reads output data from status register until another command issued. return reading from array, issue Read Array (FFH) command. status register bits output DQ0-DQ7. upper byte, DQ8-DQ15, outputs during Read Status Register command. contents status register latched falling edge CE#, whichever occurs last. This prevents possible errors which might occur status register contents change while being read. must toggled with each subsequent status read, status register will indicate completion program erase operation. When active, SR.7 will indicate status WSM; remaining bits status register indicate whether successful performing desired operation (see Table "Status Register Definition" page 15).
3.2.3.1
Clearing Status Register
sets status bits through "1," clears bits "0," cannot clear status bits through "0." Because bits indicate various error conditions, these bits only cleared through Clear Status Register (50H) command. allowing system software control resetting these bits, several operations performed (such cumulatively programming several addresses erasing multiple blocks sequence)
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before reading status register determine error occurred during that series. Clear status register before beginning another command sequence. Note that this different from burst device. Read Array command must issued before data read from memory array. Resetting device also clears status register.
3.2.4
Read Query
read query mode outputs Common Flash Interface (CFI) data when device read. This accessed writing Read Query Command (98H). data structure contains information such block size, density, command electrical specifications. Once this mode, read cycles from addresses shown Appendix retrieve specified information. return read array mode, write Read Array command (FFH).
3.2.5
Program Mode
Programming executed using two-write sequence. Program Setup command (40H) written followed second write which specifies address data programmed. will execute sequence internally timed events program desired bits addressed location, then verify bits sufficiently programmed. Programming memory results specific bits within address location being changed "0." user attempts program "1"s, memory cell contents change error occurs. status register indicates programming status: while program sequence executes, status "0." status register polled toggling either OE#. While programming, only valid commands Read Status Register, Program Suspend, Program Resume. When programming complete, program status bits should checked. programming operation unsuccessful, SR.4 status register indicate program failure. SR.3 then within acceptable limits, execute program command. SR.1 set, program operation attempted locked block operation aborted. status register should cleared before attempting next operation. instruction follow after programming completed; however, prevent inadvertent status register reads, sure reset read array mode.
3.2.5.1
Suspending Resuming Program
Program Suspend command halts in-progress program operation that data read from other locations memory. Once programming process starts, writing Program Suspend command requests that suspend program sequence predetermined points program algorithm). device continues output status register data after Program Suspend command written. Polling status register bits SR.7 SR.2 will determine when program operation been suspended (both will "1"). tWHRH1/ tEHRH1 specify program suspend latency. Read Array command written read data from blocks other than that which suspended. only other valid commands while program suspended Read Status Register, Read Configuration, Read Query, Program Resume. After Program Resume command written flash memory, will continue with programming process status register bits SR.2 SR.7 will automatically cleared. device automatically outputs status register data when read (see Figure "Program Suspend/Resume Flowchart" page after Program Resume command written. must remain same level used program while program suspend mode. must also remain VIH.
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3.2.6
Erase Mode
erase block, write Erase Set-up Erase Confirm commands CUI, along with address identifying block erased. This address latched internally when Erase Confirm command issued. Block erasure results bits within block being "1." Only block erased time. will execute sequence internally timed events program bits within block "0," erase bits within block "1," then verify that bits within block sufficiently erased. While erase executes, status "0." When status register indicates that erasure complete, check erase status verify that erase operation successful. Erase operation unsuccessful, SR.5 status register will "1," indicating erase failure. within acceptable limits after Erase Confirm command issued, will execute erase sequence; instead, SR.5 status register indicate erase error, SR.3 identify that supply voltage within acceptable limits. After erase operation, clear status register (50H) before attempting next operation. instruction follow after erasure completed; however, prevent inadvertent status register reads, advisable place flash read array mode after erase complete.
3.2.6.1
Suspending Resuming Erase
Since erase operation requires order seconds complete, Erase Suspend command provided allow erase-sequence interruption order read data from program data another block memory. Once erase sequence started, writing Erase Suspend command suspends erase sequence predetermined point erase algorithm. status register will indicate if/when erase operation been suspended. Erase suspend latency specified tWHRH2/tEHRH2. Read Array/Program command written read/program data from/to blocks other than that which suspended. This nested Program command subsequently suspended read another location. only valid commands while erase suspended Read Status Register, Read Configuration, Read Query, Program Setup, Program Resume, Erase Resume, Lock Block, Unlock Block Lock-Down Block. During erase suspend mode, chip placed pseudo-standby mode taking VIH. This reduces active current consumption. Erase Resume continues erase sequence when VIL. Similar standard erase operation, status register must read cleared before next instruction issued.
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Table
Command Operations
First Cycle Command Read Array Read Configuration Read Query Read Status Register Clear Status Register Program Block Erase/Confirm Program/Erase Suspend Program/Erase Resume Lock Block Unlock Block Lock-Down Block Protection Program Don't Care Status Reg. Data Notes Oper Prog Addr Prog Data Write Write Write Write Write Write Write Write Write Write Write Write Write Addr Data 40H/10H Write Write Write Write Write Write Read Read Read Oper Addr Data Second Cycle
Block Addr
Identifier Addr. Identifier Data
Query Addr. Query Data
NOTES: Following Read Configuration Read Query commands, read operations output device configuration query information, respectively. Section 3.2.2 Section 3.2.4. Either command valid, Intel standard 40H. When writing commands, upper data [DQ8-DQ15] should either VIH, minimize current draw. operations defined Table "Bus Operations" page
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Table
Code
Command Codes Descriptions
Device Mode Read Array Description This command places device read array mode which outputs array data data pins. This two-cycle command. first cycle prepares program operation. second cycle latches addresses data information initiates execute Program algorithm. flash outputs status register data when toggled. Read Array command required after programming read array data. Section 3.2.5. Prepares Erase Confirm command. next command Erase Confirm command, then will both SR.4 SR.5 status register "1," place device into read status register mode, wait another command. Section 3.2.6. previous command Erase Set-Up command, then will close address data latches begin erasing block indicated address pins. During program/ erase, device will respond only Read Status Register, Program Suspend Erase Suspend commands will output status register data when toggled. program erase operation previously suspended, this command will resume that operation. previous command Configuration Set-Up, will latch address unlock block indicated address pins. block been previously Lock-Down, this operation will have effect. (Section 3.3) Issuing this command will begin suspend currently executing program/erase operation. status register will indicate when operation been successfully suspended setting either program suspend (SR.2) erase suspend (SR.6) status (SR.7) (ready). will continue idle SUSPEND state, regardless state input control pins except RP#, which will immediately shut down remainder chip driven VIL. Sections 3.2.5.1 3.2.6.1. This command places device into read status register mode. Reading device will output contents status register, regardless address presented device. device automatically enters this mode after program erase operation been initiated. Section 3.2.3. block lock status (SR.1) Status (SR.3), program status (SR.4), erase status (SR.5) bits status register "1," cannot clear them "0." Issuing this command clears those bits "0." Puts device into read configuration mode that reading device will output manufacturer/device codes block lock status. Section 3.2.2. Prepares changes device configuration, such block locking changes. next command Block Unlock, Block Lock, Block Lock-Down, then will both program erase status register bits indicate command sequence error. Section 3.2. previous command Configuration Set-Up, will latch address lock block indicated address pins. (Section 3.3) previous command Configuration Set-Up command, will latch address lock-down block indicated address pins. (Section 3.3) Puts device into read query mode that reading device will output Common Flash Interface information. Section 3.2.4 Appendix This two-cycle command. first cycle prepares program operation protection register. second cycle latches addresses data information initiates execute Protection Program algorithm protection register. flash outputs status register data when toggled. Read Array command required after programming read array data. Section 3.4. Operates same Program Set-up command. (See 40H/Program Set-Up) Unassigned commands that should used. Intel reserves right redefine these codes future functions.
Program Set-Up
Erase Set-Up
Erase Confirm Program/Erase Resume Unlock Block
Program Suspend Erase Suspend
Read Status Register Clear Status Register Read Configuration Configuration Set-Up Lock-Block Lock-Down Read Query Protection Program Setup Alt. Prog Set-Up Invalid/ Reserved
NOTE: Appendix mode transition information.
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Table
WSMS
Status Register Definition
VPPS NOTES:
SR.7 WRITE STATE MACHINE STATUS (WSMS) Ready Busy SR.6 ERASE-SUSPEND STATUS (ESS) Erase Suspended Erase Progress/Completed SR.5 ERASE STATUS (ES) Error Block Erase Successful Block Erase SR.4 PROGRAM STATUS (PS) Error Programming Successful Programming
Check Write State Machine first determine Word Program Block Erase completion, before checking Program Erase Status bits. When Erase Suspend issued, halts execution sets both WSMS bits "1." remains until Erase Resume command issued. When this "1," applied max. number erase pulses block still unable verify successful block erasure. When this "1," attempted failed program word/byte. status does provide continuous indication level. interrogates level only after Program Erase command sequences have been entered, informs system been switched also checked before operation verified WSM. status guaranteed report accurate feedback between VPPLK VPP1Min. When Program Suspend issued, halts execution sets both WSMS bits "1." remains until Program Resume command issued. program erase operation attempted locked blocks, this WSM. operation specified aborted device returned read status mode. This reserved future should masked when polling status register.
SR.3 STATUS (VPPS) Detect, Operation Abort
SR.2 PROGRAM SUSPEND STATUS (PSS) Program Suspended Program Progress/Completed SR.1 BLOCK LOCK STATUS Prog/Erase attempted locked block; Operation aborted. operation locked blocks SR.0 RESERVED FUTURE ENHANCEMENTS
NOTE: Command Sequence Error indicated when both SR.4, SR.5 SR.7 set.
Flexible Block Locking
Intel Volt Advanced+ Boot Block products offer instant, individual block locking scheme that allows block locked unlocked with latency, enabling instant code data protection. This locking scheme offers levels protection. first level allows software-only control block locking (useful data blocks that change frequently), while second level requires hardware interaction before locking changed (useful code blocks that change infrequently). following sections will discuss operation locking system. term "state [XYZ]" will used specify locking states; e.g., "state [001]," where value WP#, Block Lock status register, Block Lock status register. Table "Block Locking State Transitions" page defines these possible locking states.
3UHOLPLQDU\
28F800C3, 28F160C3, 28F320C3, 28F640C3
3.3.1
Locking Operation
following concisely summarizes locking functionality.
blocks power-up locked, then unlocked locked with Unlock Lock
commands.
Lock-Down command locks block prevents from being unlocked when
When Lock-Down overridden commands unlock/lock locked-down blocks. When returns locked-down blocks return Lock-Down. Lock-Down cleared only when device reset powered-down. locking status each block Locked, Unlocked, Lock-Down, each which will described following sections. comprehensive state table locking functions shown Table page flowchart locking operations shown Figure page
3.3.1.1
Locked State
default status blocks upon power-up reset locked (states [001] [101]). Locked blocks fully protected from alteration. program erase operations attempted locked block will return error SR.1 status register. status locked block changed Unlocked Lock-Down using appropriate software commands. Unlocked block locked writing Lock command sequence, followed 01H.
3.3.2
Unlocked State
Unlocked blocks (states [000], [100], [110]) programmed erased. unlocked blocks return Locked state when device reset powered down. status unlocked block changed Locked Locked-Down using appropriate software commands. Locked block unlocked writing Unlock command sequence, followed D0H.
3.3.3
Lock-Down State
Blocks that Locked-Down (state [011]) protected from program erase operations (just like Locked blocks), their protection status cannot changed using software commands alone. Locked Unlocked block Locked-down writing Lock-Down command sequence, followed 2FH. Locked-Down blocks revert Locked state when device reset powered down. Lock-Down function dependent input pin. When blocks LockDown [011] protected from program, erase, lock status changes. When LockDown function disabled ([111]) locked-down blocks individually unlocked software command [110] state, where they erased programmed. These blocks then relocked [111] unlocked [110] desired while remains high. When goes low, blocks that were previously locked-down return Lock-Down state [011] regardless changes made while high. Device reset power-down resets blocks, including those Lock-Down, Locked state.
3UHOLPLQDU\
28F800C3, 28F160C3, 28F320C3, 28F640C3
3.3.4
Reading Block's Lock Status
lock status every block read configuration read mode device. enter this mode, write device. Subsequent reads Block Address 00002 will output lock status that block. lock status represented DQ1. indicates Block Lock/Unlock status Lock command cleared Unlock command. also automatically when entering Lock-Down. indicates Lock-Down status Lock-Down command. cannot cleared software, only device reset power-down.
Table
Block Lock Status
Item Block Lock Configuration Block Unlocked Block Locked Block Locked-Down Address XX002 Data LOCK
3.3.5
Locking Operations during Erase Suspend
Changes block lock status performed during erase suspend using standard locking command sequences unlock, lock, lock-down block. This useful case when another block needs updated while erase operation progress. change block locking during erase operation, first write erase suspend command (B0H), then check status register until indicates that erase operation been suspended. Next write desired lock command sequence block lock status will changed. After completing desired lock, read, program operations, resume erase operation with Erase Resume command (D0H). block locked locked-down during suspended erase same block, locking status bits will changed immediately, when erase resumed, erase operation will complete. Locking operations cannot performed during program suspend. Refer Appendix detailed information which commands valid during erase suspend.
3.3.6
Status Register Error Checking
Using nested locking program command sequences during erase suspend introduce ambiguity into status register results. Since locking changes performed using cycle command sequence, e.g., followed lock block, following Configuration Setup command (60H) with invalid command will produce lock command error (SR.4 SR.5 will status register. lock command error occurs during erase suspend, SR.4 SR.5 will will remain after erase resumed. When erase complete, possible error during erase cannot detected status register because previous locking command error. similar situation happens error occurs during program operation error nested within erase suspend.
3UHOLPLQDU\
28F800C3, 28F160C3, 28F320C3, 28F640C3
Table
Block Locking State Transitions
Current State Lock Command Input Result (Next State) Erase/Prog Allowed? Name "Unlocked" "Locked" (Default) "Locked-Down" "Unlocked" "Locked" Lock-Down Disabled Lock-Down Disabled Goes [001] Change Change Goes [101] Change Goes [111] Change Change Goes [000] Change Change Goes [100] Change Goes [110] Goes [011] Goes [011] Change Goes [111] Goes [111] Goes [111] Change
Lock
Unlock
Lock-Down
NOTES: this table, notation [XYZ] denotes locking state block, where WP#, DQ1, DQ0. current locking state block defined state bits block lock status (DQ0, DQ1). indicates block locked unlocked (0). indicates block been lockeddown (0). power-up device reset, blocks default Locked state [001] Holding recommended default. "Erase/Program Allowed?" column shows whether erase program operations enabled (Yes) disabled (No) that block's current locking state. "Lock Command Input Result [Next State]" column shows result writing three locking commands (Lock, Unlock, Lock-Down) current locking state. example, "Goes [001]" would mean that writing command block current locking state would change [001].
128-Bit Protection Register
Volt Advanced+ Boot Block architecture includes 128-bit protection register than used increase security system design. example, number contained protection register used "mate" flash component with other system components such ASIC, preventing device substitution. Additional application information found Intel application note AP-657 Designing with Advanced+ Boot Block Flash Memory Architecture. 128-bits protection register divided into 64-bit segments. segments programmed Intel factory with unique 64-bit number, which unchangeable. other segment left blank customer designs program desired. Once customer segment programmed, locked prevent reprogramming.
3.4.1
Reading Protection Register
protection register read configuration read mode. device switched this mode writing Read Configuration command (90H). Once this mode, read cycles from addresses shown Appendix retrieve specified information. return read array mode, write Read Array command (FFH).
3UHOLPLQDU\
28F800C3, 28F160C3, 28F320C3, 28F640C3
3.4.2
Programming Protection Register
protection register bits programmed using two-cycle Protection Program command. 64-bit number programmed bits time word-wide parts eight bits time byte-wide parts. First write Protection Program Setup command, C0H. next write device will latch address data program specified location. allowable addresses shown Appendix Figure "Protection Register Programming Flowchart" page Attempts address Protection Program commands outside defined protection register address space should attempted. This space reserved future use. Attempting program previously locked protection register segment will result status register error (program error SR.4 lock error SR.1 will
3.4.3
Locking Protection Register
user-programmable segment protection register lockable programming PR-LOCK location this location programmed Intel factory protect unique device number. This using Protection Program command program "FFFD" PR-LOCK location. After these bits have been programmed, further changes made values stored protection register. Protection Program commands locked section will result status register error (program error SR.4 Lock Error SR.1 will Protection register lockout state reversible.
Figure Protection Register Memory
Words User Programmed Words Factory Programmed Lock
0645_05
Program Erase Voltages
Intel Volt Advanced+ Boot Block products provide in-system programming erase 1.65 V-3.6 range. fast production programming, also includes low-cost, backwardcompatible programming feature.
3.5.1
Improved Volt Production Programming
When between 1.65 program erase current drawn through pin. Note that driven logic signal, 1.65 That must remain above 1.65 perform in-system flash modifications. When connected power supply, device draws program erase current directly from pin. This eliminates need external switching transistor control voltage VPP. Figure page shows examples flash power supplies configured various usage models.
3UHOLPLQDU\
28F800C3, 28F160C3, 28F320C3, 28F640C3
mode enhances programming performance during short period time typically found manufacturing processes; however, intended extended use. applied during program erase operations maximum 1000 cycles main blocks 2500 cycles parameter blocks. connected total hours maximum. Stressing device beyond these limits cause permanent damage.
3.5.2
VPPLK Complete Protection
addition flexible block locking, programming voltage held absolute hardware write protection blocks flash device. When below VPPLK, program erase operation will result error, prompting corresponding status register (SR.3) set.
Figure Example Power Supply Configurations
System Supply Supply Fast Programming Absolute Write Protection With VPPLK System Supply
(Note
System Supply
Prot# (Logic Signal)
Low-Voltage Programming Absolute Write Protection Logic Signal System Supply
Low-Voltage Programming
Supply Voltage Fast Programming
0645_06
NOTE: resistor used supply sink adequate current based resistor value. AP-657 Designing with Advanced+ Boot Block Flash Memory Architecture details.
Power Consumption
Intel Flash devices have tiered approach power savings that significantly reduce overall system power consumption. Automatic Power Savings (APS) feature reduces power consumption when device selected idle. deasserted, flash enters standby mode, where current consumption even lower. combination these features minimize memory power consumption, therefore, overall system power consumption.
3.6.1
Active Power (Program/Erase/Read)
With logic-low level logic-high level, device active mode. Refer Characteristic tables current values. Active power largest contributor overall system power consumption. Minimizing active current could have profound effect system power consumption, especially battery-operated devices.
3UHOLPLQDU\
28F800C3, 28F160C3, 28F320C3, 28F640C3
3.6.2
Automatic Power Savings (APS)
Automatic Power Savings provides low-power operation during read mode. After data read from memory array address lines quiescent, circuitry places device mode where typical current comparable ICCS. flash stays this static state with outputs valid until location read.
3.6.3
Standby Power
When logic-high level (VIH) device read mode, flash memory standby mode, which disables much device's circuitry substantially reduces power consumption. Outputs placed high-impedance state independent status signal. transitions logic-high level during erase program operations, device will continue perform operation consume corresponding active power until operation completed. System engineers should analyze breakdown standby time versus active time quantify respective power consumption each mode their specific application. This will provide more accurate measure application-specific power energy requirements.
3.6.4
Deep Power-Down Mode
deep power-down mode activated when (GND During read modes, going de-selects memory places outputs high impedance state. Recovery from deep power-down requires minimum time tPHQV read operations tPHWL/tPHEL write operations. During program erase modes, transitioning will abort in-progress operation. memory contents address being programmed block being erased longer valid data integrity been compromised abort. During deep power-down, internal circuits switched power savings mode (RP# transitioning turning power device clears status register).
Power-Up/Down Operation
device protected against accidental block erasure programming during power transitions. Power supply sequencing required, since device indifferent which power supply, VCC, powers-up first.
3.7.1
Connected System Reset
during system reset important with automated program/erase devices since system expects read from flash memory when comes reset. reset occurs without flash memory reset, proper initialization will occur because flash memory providing status information instead array data. Intel recommends connecting system RESET# signal allow proper CPU/flash initialization following system reset. System designers must guard against spurious writes when voltages above VLKO. Since both must command write, driving either signal will inhibit writes device. architecture provides additional protection since alteration memory contents only occur after successful completion two-step command sequences. device also disabled until brought VIH, regardless state control inputs.
3UHOLPLQDU\
28F800C3, 28F160C3, 28F320C3, 28F640C3
holding device reset (RP# connected system PowerGood) during power-up/down, invalid conditions during power-up masked, providing another level memory protection.
3.7.2
VCC, Transitions
latches commands issued system software altered transitions actions. default state upon power-up, after exit from reset mode after transitions above VLKO (Lockout voltage), read array mode. After program block erase operation complete (even after transitions down VPPLK), must reset read array mode Read Array command access flash memory array desired.
Power Supply Decoupling
Flash memory's power switching characteristics require careful device decoupling. System designers should consider three supply current issues:
Standby current levels (ICCS) Read current levels (ICCR) Transient peaks produced falling rising edges CE#.
Transient current magnitudes depend device outputs' capacitive inductive loading. Twoline control proper decoupling capacitor selection will suppress these transient voltage peaks. Each flash device should have ceramic capacitor connected between each GND, between GND. These high- frequency, inherently low-inductance capacitors should placed close possible package leads.
3UHOLPLQDU\
28F800C3, 28F160C3, 28F320C3, 28F640C3
Electrical Specifications
Absolute Maximum Ratings
Parameter Extended Operating Temperature During Read During Block Erase Program Temperature under Bias Storage Temperature Voltage (except VPP) with Respect Voltage (for Block Erase Program) with Respect VCCQ Supply Voltage with Respect Output Short Circuit Current +125 -0.5 +3.7 V(1) -0.5 +13.5 V(1,2,3) -0.2 +3.6 mA(4) Maximum Rating
NOTES: Minimum voltage -0.5 input/output pins. During transitions, this level undershoot -2.0 periods Maximum voltage input/output pins +0.5 which, during transitions, overshoot +2.0 periods Maximum voltage overshoot +14.0 periods Program voltage normally 1.65 V-3.6 Connection 11.4 V-12.6 supply done maximum 1000 cycles main blocks 2500 cycles parameter blocks during program/erase. connected total hours maximum. Section details. Output shorted more than second. more than output shorted time.
NOTICE: This datasheet contains preliminary information products production. Specifications subject change without notice. Verify with your local Intel Sales office that have latest datasheet before finalizing design.
Warning:
Stressing device beyond "Absolute Maximum Ratings" cause permanent damage. These stress ratings only. Operation beyond "Operating Conditions" recommended extended exposure beyond "Operating Conditions" affect device reliability.
3UHOLPLQDU\
28F800C3, 28F160C3, 28F320C3, 28F640C3
Operating Conditions
Table Temperature Voltage Operating Conditions
Symbol VCC1 VCC2 VCCQ1 VPP1 VPP2 Cycling Block Erase Cycling Supply Voltage Supply Voltage Parameter Operating Temperature Supply Voltage Notes 1.65 11.4 100,000 12.6 Volts Volts Volts Cycles Units Volts
NOTES: VCCQ must share same supply when they VCC1 range. VCCMax 0.25µm 32-Mbit devices. Applying 11.4 V-12.6 during program/erase only done maximum 1000 cycles main blocks 2500 cycles parameter blocks. connected total hours maximum. Section details.
Capacitance
COUT Parameter Input Capacitance Output Capacitance Notes Units Conditions VOUT
NOTE: Sampled, 100% tested.
3UHOLPLQDU\
28F800C3, 28F160C3, 28F320C3, 28F640C3
Characteristics
V-3.6 V(2) Unit VCCMax, VCCQ VCCQMax VCCQ VCCMax, VCCQ VCCQMax VCCQ VCCMax, VCCQ VCCQ VCCMax, VCCQ VCCQ VCCMax, VCCQ VCCQMax VCCQ GND, VCCMax, VCCQ VCCQMax VCCQ GND, VCCMax, VCCQ VCCQMax Test Conditions
Parameter
VCCQ Notes
Input Load Current Output Leakage Current Standby Current 0.18 Micron Product
ICCS
Standby Current 0.25 Micron Micron Product Deep Power-Down Current 0.18 Micron Product
ICCD
Deep Power-Down Current 0.25 Micron Micron Product Read Current
ICCR
1,2,3
VIL, MHz, IOUT Inputs VPP1, Program Progress VPP2 Program Progress VPP1, Erase Progress VPP2 Erase Progress VIH, Erase Suspend Progress VIH, Erase Suspend Progress VIH, Program Suspend Progress VIH, Program Suspend Progress =VPP1, Program Progress VPP2 Program Progress VPP1, Program Progress VPP2 Program Progress
ICCW
Program Current
1,4,5
ICCE
Erase Current Erase Suspend Current 0.18 Micron Product
ICCES
Erase Suspend Current 0.25 Micron Micron Product Program Suspend Current 0.18 Micron Product
1,4,5
1,4,5
ICCWS
Program Suspend Current 0.25 Micron Micron Product Deep Power-Down Current Standby Current Read Current
1,4,5
0.05
IPPD IPPS IPPR
IPPW
Program Current
0.05
IPPE
Erase Current
3UHOLPLQDU\
28F800C3, 28F160C3, 28F320C3, 28F640C3
Parameter VCCQ Notes
V-3.6 V(2) Unit VPP1, Erase Suspend Progress VPP2 Erase Suspend Progress VPP1 Program Suspend Progress VPP2 Program Suspend Progress Test Conditions
IPPES
Erase Suspend Current
IPPWS
Program Suspend Current
Characteristics, Continued
Parameter VCCQ Notes Input Voltage Input High Voltage Output Voltage -0.4 -0.10 *0.22 VCCQ +0.3 0.10 VCCMin VCCQ VCCQMin VCCMin VPPLK VPP1 VPP2 VLKO VLKO2 Output High Voltage Lock-Out Voltage during Program Erase Operations Prog/Erase Lock Voltage VCCQ Prog/Erase Lock Voltage 1.65 11.4 VCCQ -0.1 12.6 VCCQ VCCQMin -100 Complete Write Protection Unit Test Conditions
NOTES: currents unless otherwise noted. Typical values nominal VCC, test conditions VCCMax, VCCQMax, VCCMin, VCCQMin refer maximum minimum VCCQ voltage listed each column. VCCMax 0.25µm 32-Mbit devices. Automatic Power Savings (APS) reduces ICCR approximately standby levels static operation (CMOS inputs). Sampled, 100% tested. ICCES ICCWS specified with device de-selected. device read while erase suspend, current draw ICCES ICCR. device read while program suspend, current draw ICCWS ICCR. Erase Program inhibited when VPPLK guaranteed outside valid ranges VPP1 VPP2. Applying 11.4 V-12.6 during program/erase only done maximum 1000 cycles main blocks 2500 cycles parameter blocks. connected total hours maximum. Section details.
3UHOLPLQDU\
28F800C3, 28F160C3, 28F320C3, 28F640C3
Figure Input/Output Reference Waveform
VCCQ INPUT VCCQ TEST POINTS VCCQ OUTPUT
0645_07
Figure Test Configuration
VCCQ Device Under Test
0645_08
Test Configuration V-3.6 Standard Test
(pF)
NOTE: includes capacitance.
3UHOLPLQDU\
28F800C3, 28F160C3, 28F320C3, 28F640C3
Characteristics-Read Operations
Density Product Mbit Unit Note
Parameter
tAVAV tAVQV tELQV tGLQV tPHQV tELQX tGLQX tEHQZ tGHQZ
Read Cycle Time Address Output Delay Output Delay Output Delay Output Delay Output Output Output High Output High Output Hold from Address, CE#, Change, Whichever Occurs First
NOTES: delayed tELQV-tGLQV after falling edge without impact tELQV. Sampled, 100% tested. Figure Waveform: Read Operations" page Figure "Input/Output Reference Waveform" page timing measurements maximum allowable input slew rate.
3UHOLPLQDU\
28F800C3, 28F160C3, 28F320C3, 28F640C3
Characteristics-Read Operations, continued
Density Parameter Product V-3.6 tAVAV tAVQV tELQV tGLQV tPHQV tELQX tGLQX tEHQZ Read Cycle Time Address Output Delay Output Delay(1) Output Delay(1) Output Delay Output Z(2) Output Z(2) Output High Z(2) V-3.6 Mbit V-3.6 V-3.6 Unit V-3.6 V-3.6
Output tGHQZ to(2) High Output Hold from Address, CE#, Change, Whichever Occurs First(2)
NOTES: delayed tELQV-tGLQV after falling edge without impact tELQV. Sampled, 100% tested. Figure Waveform: Read Operations" page Figure "Input/Output Reference Waveform" page timing measurements maximum allowable input slew rate.
3UHOLPLQDU\
28F800C3, 28F160C3, 28F320C3, 28F640C3
Characteristics-Read Operations, continued
Density Parameter Product V-3.6 tAVAV tAVQV tELQV tGLQV tPHQV tELQX tGLQX tEHQZ tGHQZ Read Cycle Time Address Output Delay Output Delay(1) Output Delay(1) Output Delay Output Z(2) Output Z(2) Output High Z(2) Output High Z(2) Output Hold from Address, CE#, Change, Whichever Occurs First(2) V-3.6 Mbit V-3.3 V-3.3 Unit V-3.3 V-3.3
NOTES: delayed tELQV-tGLQV after falling edge without impact tELQV. Sampled, 100% tested. Figure Waveform: Read Operations" page Figure "Input/Output Reference Waveform" page timing measurements maximum allowable input slew rate.
3UHOLPLQDU\
28F800C3, 28F160C3, 28F320C3, 28F640C3
Characteristics-Read Operations, continued
Density Product Parameter Note tAVAV tAVQV tELQV tGLQV tPHQV tELQX tGLQX tEHQZ tGHQZ Read Cycle Time Address Output Delay Output Delay Output Delay Output Delay Output Output Output High Output High Output Hold from Address, CE#, Change, Whichever Occurs First V-3.6 V-3.6 Mbit Unit
NOTES: delayed tELQV-tGLQV after falling edge without impact tELQV. Sampled, 100% tested. Figure Waveform: Read Operations" page Figure "Input/Output Reference Waveform" page timing measurements maximum allowable input slew rate.
3UHOLPLQDU\
28F800C3, 28F160C3, 28F320C3, 28F640C3
Figure Waveform: Read Operations
Standby
Device Address Selection Address Stable
Data Valid
ADDRESSES
High Valid Output High
DATA (D/Q)
3UHOLPLQDU\
28F800C3, 28F160C3, 28F320C3, 28F640C3
Characteristics-Write Operations
Density Product Parameter Note Mbit Unit
tPHWL tPHEL tELWL tWLEL tWLWH tELEH tDVWH tDVEH tAVWH tAVEH tWHEH tEHWH tWHDX tEHDX tWHAX tEHAX tWHWL tEHEL tVPWH tVPEH tQVVL tBHWH tBHEH tQVBL tWHGL
High Recovery (CE#) Going (WE#) Setup (CE#) Going (CE#) Pulse Width Data Setup (CE#) Going High Address Setup (CE#) Going High (WE#) Hold Time from (CE#) High Data Hold Time from (CE#) High Address Hold Time from (CE#) High (CE#) Pulse Width High Setup (CE#) Going High Hold from Valid Setup (CE#) Going High Hold from Valid High Going
NOTES: Write pulse width (tWP) defined from going (whichever goes last) going high (whichever goes high first). Hence, tWLWH tELEH tWLEH tELWH. Similarly, write pulse width high (tWPH) defined from going high (whichever goes high first) going (whichever goes first). Hence, tWPH tWHWL tEHEL tWHEL tEHWL. Refer Table "Command Operations" page valid DIN. Sampled, 100% tested. Write timing characteristics during erase suspend same during write-only operations. Figure "Input/Output Reference Waveform" page timing measurements maximum allowable input slew rate. Figure Waveform: Read Operations" page VCCMax 32-Mbit 64-Mbit densities.
3UHOLPLQDU\
28F800C3, 28F160C3, 28F320C3, 28F640C3
Characteristics-Write Operations, continued
Density Product Parameter Note tPHWL tPHEL tELWL tWLEL tWLWH tELEH tDVWH tDVEH tAVWH tAVEH tWHEH tEHWH tWHDX tEHDX tWHAX tEHAX tWHWL tEHEL tVPWH tVPEH tQVVL tBHWH tBHEH tQVBL tWHGL High Recovery (CE#) Going (WE#) Setup (CE#) Going (CE#) Pulse Width Data Setup (CE#) Going High Address Setup (CE#) Going High (WE#) Hold Time from (CE#) High Data Hold Time from (CE#) High Address Hold Time from (CE#) High (CE#) Pulse Width High Setup (CE#) Going High Hold from Valid Setup (CE#) Going High Hold from Valid High Going Mbit Unit
NOTES: Write pulse width (tWP) defined from going (whichever goes last) going high (whichever goes high first). Hence, tWLWH tELEH tWLEH tELWH. Similarly, write pulse width high (tWPH) defined from going high (whichever goes high first) going (whichever goes first). Hence, tWPH tWHWL tEHEL tWHEL tEHWL. Refer Table "Command Operations" page valid DIN. Sampled, 100% tested. Write timing characteristics during erase suspend same during write-only operations. Figure "Input/Output Reference Waveform" page timing measurements maximum allowable input slew rate. Figure Waveform: Read Operations" page VCCMax 32-Mbit 64-Mbit densities.
3UHOLPLQDU\
28F800C3, 28F160C3, 28F320C3, 28F640C3
Characteristics-Write Operations, continued
Density Product Parameter V(4) V(4) Note tPHWL tPHEL tELWL tWLEL tWLWH tELEH tDVWH tDVEH tAVWH tAVEH tWHEH tEHWH tWHDX tEHDX tWHAX tEHAX tWHWL tEHEL tVPWH tVPEH tQVVL tBHWH tBHEH tQVBL tWHGL High Recovery (CE#) Going (WE#) Setup (CE#) Going (CE#) Pulse Width Data Setup (CE#) Going High Address Setup (CE#) Going High (WE#) Hold Time from (CE#) High Data Hold Time from (CE#) High Address Hold Time from (CE#) High (CE#) Pulse Width High Setup (CE#) Going High Hold from Valid Setup (CE#) Going High Hold from Valid High Going Mbit Unit
NOTES: Write pulse width (tWP) defined from going (whichever goes last) going high (whichever goes high first). Hence, tWLWH tELEH tWLEH tELWH. Similarly, write pulse width high (tWPH) defined from going high (whichever goes high first) going (whichever goes first). Hence, tWPH tWHWL tEHEL tWHEL tEHWL. Refer Table "Command Operations" page valid DIN. Sampled, 100% tested. Write timing characteristics during erase suspend same during write-only operations. Figure "Input/Output Reference Waveform" page timing measurements maximum allowable input slew rate. Figure Waveform: Read Operations" page VCCMax 0.25µm 32-Mbit devices.
3UHOLPLQDU\
28F800C3, 28F160C3, 28F320C3, 28F640C3
Characteristics-Write Operations, continued
Density Product Parameter Note tPHWL tPHEL tELWL tWLEL tWLWH tELEH tDVWH tDVEH tAVWH tAVEH tWHEH tEHWH tWHDX tEHDX tWHAX tEHAX tWHWL tEHEL tVPWH tVPEH tQVVL tBHWH tBHEH tQVBL tWHGL High Recovery (CE#) Going (WE#) Setup (CE#) Going (CE#) Pulse Width Data Setup (CE#) Going High Address Setup (CE#) Going High (WE#) Hold Time from (CE#) High Data Hold Time from (CE#) High Address Hold Time from (CE#) High (CE#) Pulse Width High Setup (CE#) Going High Hold from Valid Setup (CE#) Going High Hold from Valid High Going Mbit Unit
NOTES: Write pulse width (tWP) defined from going (whichever goes last) going high (whichever goes high first). Hence, tWLWH tELEH tWLEH tELWH. Similarly, write pulse width high (tWPH) defined from going high (whichever goes high first) going (whichever goes first). Hence, tWPH tWHWL tEHEL tWHEL tEHWL. Refer Table "Command Operations" page valid DIN. Sampled, 100% tested. Write timing characteristics during erase suspend same during write-only operations. Figure "Input/Output Reference Waveform" page timing measurements maximum allowable input slew rate. Figure Waveform: Read Operations" page
3UHOLPLQDU\
28F800C3, 28F160C3, 28F320C3, 28F640C3
Erase Program Timings
Symbol Parameter Note tBWPB tBWMB 4-KW Parameter Block Word Program Time 32-KW Main Block Word Program Time Word Program Time 0.18 Micron Product tWHQV1 tEHQV1 Word Program Time 0.25 Micron Product 4-KW Parameter Block Erase Time 32-KW Main Block Erase Time Program Suspend Latency Erase Suspend Latency Typ(1) 0.10 0.30 Typ(1) 0.03 0.24 0.12 1.65 V-3.6 11.4 V-12.6 Unit
tWHQV2 tEHQV2 tWHQV3 tEHQV3 tWHRH1 tEHRH1 tWHRH2 tEHRH2
NOTES: Typical values measured nominal voltages. Excludes external system-level overhead. Sampled, 100% tested.
3UHOLPLQDU\
28F800C3, 28F160C3, 28F320C3, 28F640C3
Figure Waveform: Program Erase Operations
(WE#) [E(W)] (CE) [W(E)]
Valid High (Note
ADDRESSES
(Note
DATA [D/Q]
VPPH2 VPPLK
NOTES: must toggled when reading Status Register Data. must inactive (high) when reading Status Register Data. Power-Up Standby. Write Program Erase Setup Command. Write Valid Address Data (for Program) Erase Confirm Command. Automated Program Erase Delay. Read Status Register Data (SRD): reflects completed program/erase operation. Write Read Array Command.
3UHOLPLQDU\
28F800C3, 28F160C3, 28F320C3, 28F640C3
Reset Operations
Figure Waveform: Reset Operations
PLPH Reset during Read Mode
PHQV PHWL PHEL
Abort Complete
PLRH
PHQV PHWL PHEL
PLPH Reset during Program Block Erase, PLPH PLRH
Abort Deep Complete PowerDown
PLRH
PHQV PHWL PHEL
PLPH
Reset Program Block Erase, PLPH PLRH
Table Reset Specifications
Symbol Parameter Reset during Read tied VCC, this specification applicable) Reset during Block Erase Reset during Program Notes tPLPH tPLRH1 tPLRH2 Unit
NOTES: tPLPH device still reset this guaranteed. asserted while block erase word program operation executing, reset will complete within Sampled, 100% tested. Section 3.1.4 full description these conditions.
3UHOLPLQDU\
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Ordering Information
Package 48-Lead TSOP 48-Ball µBGA* Easy Product line designator Intel® Flash products Access Speed (ns) (70, 100, 110) Lithography 0.25 0.18 Blocking Bottom Blocking Product Family Volt Advanced+ Boot Block V-3.6 V-3.6 11.4 V-12.6
Device Density Mbit) Mbit) Mbit) Mbit)
VALID COMBINATIONS (All Extended Temperature)
48-Lead TSOP
Extended Mbit TE28F640C3TC90 TE28F640C3BC90 TE28F640C3TC100 TE28F640C3BC100 TE28F320C3TC70 TE28F320C3BC70 Extended Mbit TE28F320C3TC90 TE28F320C3BC90 TE28F320C3TA100 TE28F320C3BA100 TE28F320C3TA110 TE28F320C3BA110 TE28F160C3TC70 TE28F160C3BC70 Extended Mbit TE28F160C3TC80 TE28F160C3BC80 TE28F160C3TA90 TE28F160C3BA90 TE28F160C3TA110 TE28F160C3BA110 Extended Mbit TE28F800C3TA90 TE28F800C3BA90 TE28F800C3TA110 TE28F800C3BA110
48-Ball µBGA*
GT28F640C3TC90 GT28F640C3BC90 GT28F640C3TC100 GT28F640C3BC100
48-Ball
Easy
RC28F640C3TC90 RC28F640C3BC90 RC28F640C3TC100 RC28F640C3BC100
GE28F320C3TC70 GE28F320C3BC70 GE28F320C3TC90 GE28F320C3BC90 GT28F320C3TA100 GT28F320C3BA100 GT28F320C3TA110 GT28F320C3BA110 GE28F160C3TC70 GE28F160C3BC70 GE28F160C3TC80 GE28F160C3BC80 GT28F160C3TA90 GT28F160C3BA90 GT28F160C3TA110 GT28F160C3BA110
RC28F320C3TC70 RC28F320C3BC70 RC28F320C3TC90 RC28F320C3BC90 RC28F320C3TA100 RC28F320C3BA100 RC28F320C3TA110 RC28F320C3BA110 RC28F160C3TC70 RC28F160C3BC70 RC28F160C3TC80 RC28F160C3BC80 RC28F160C3TA90 RC28F160C3BA90 RC28F160C3TA110 RC28F160C3BA110 RC28F800C3TA90 RC28F800C3BA90 RC28F800C3TA110 RC28F800C3BA110
NOTE: second line 48-ball µBGA package side mark specifies assembly codes. samples only, first character signifies either engineering samples silicon daisy chain samples. other assembly codes without first character production units.
3UHOLPLQDU\
28F800C3, 28F160C3, 28F320C3, 28F640C3
Additional Information
Order Number 297938 292216 292215 Contact your Intel Representative 297874 Document/Tool
Volt Advanced+ Boot Block Flash Memory Specification Update AP-658 Designing Upgrade Advanced+ Boot Block Flash Memory AP-657 Designing with Advanced+ Boot Block Flash Memory Architecture Intel® Flash Data Integrator (IFDI) Software Developer's IFDI Interactive: Play with Intel® Flash Data Integrator Your
NOTES: Please call Intel Literature Center (800) 548-4725 request Intel documentation. International customers should contact their local Intel distribution sales office. Visit Intel's World Wide home page http://www.Intel.com http://developer.intel.com technical documentation tools.
3UHOLPLQDU\
28F800C3, 28F160C3, 28F320C3, 28F640C3
Appendix Current/Next States, Sheet
Command Input (and Next State) Data When Read Array Status Config Status Status Status Status Status Status Status Status Prog. Sus. Read Array Prog. Sus. Read Array Prog. Sus. Read Array Prog. Sus. Read Array Read Array Program (Not Done) Program Suspend Read Array Program Suspend Read Array Program Suspend Read Array Program Suspend Read Array Prog. Setup Ers. Setup Erase (Not Done) Prog. (Not Done) Prog. (Not Done) Prog. (Not Done) Prog. (Not Done) Read Array Prog. Setup Read Array (FFH) Read Array Read Array Read Array Read Array Program Setup (10/ 40H) Prog. Setup Prog. Setup Prog. Setup Prog. Setup Erase Setup (20H) Ers. Setup Ers. Setup Ers. Setup Ers. Setup Lock (Done) Ers. Setup Ers. Setup Erase Confirm (D0H) Prog/Ers Suspend (B0H) Read Array Read Array Read Array Read Array Lock Cmd. Error Read Array Read Array Protection Register Program Protection Register Program (Not Done) Ers. Setup Read Array Program Prog. Sus. Status Prog. Sus. Array Prog. Sus. Array Prog. Sus. Array Prog. Sus. Array Read Array Program (Not Done) Program (Not Done) Program (Not Done) Program (Not Done) Program (Not Done) Prog. Sus. Status Prog. Sus. Status Prog. Sus. Status Prog. Sus. Status Read Status Erase (Not Done) Prog. Sus. Array Prog. Sus. Array Prog. Sus. Array Prog. Sus. Array Read Array Read Sts. Read Array Lock (Done) Prog/Ers Resume (D0) Read Status (70H) Read Sts. Read Sts. Read Sts. Read Sts. Clear Status (50H) Read Array Read Array Read Array Read Array
Current State
Read Array Read Status Read Config. Read Query Lock Setup Lock Cmd. Error Lock Oper. (Done) Prot. Prog. Setup Prot. Prog. (Not Done) Prot. Prog. (Done) Prog. Setup Program (Not Done) Prog. Susp. Status Prog. Susp. Read Array Prog. Susp. Read Config Prog. Susp. Read Query Program (Done)
Lock Command Error Read Array Read Array Prog. Setup Prog. Setup
Lock Cmd. Error Read Sts. Read Sts. Read Array Read Array
Status
Array
Config
Status
Erase Setup
Status
Erase Command Error
Erase Cmd. Error
Erase Command Error
Erase Cmd. Error
Status
Read Array
Prog. Setup
Ers. Setup
Read Array Erase Sus. Status Erase Ers. Sus. Array Ers. Sus. Array Ers. Sus. Array Ers. Sus. Array Read Array Erase
Read Status Erase (Not Done) Erase Sus. Status Erase Sus. Status Erase Sus. Status Erase Sus. Status Read Sts.
Read Array
Erase (Not Done)
Status Erase Sus. Read Array Erase Sus. Read Array Erase Sus. Read Array Erase Sus. Read Array Read Array
Erase (Not Done) Ers. Sus. Array Ers. Sus. Array Ers. Sus. Array Ers. Sus. Array Ers. Setup
Ers. Susp. Status
Status
Prog. Setup
Ers. Sus. Array Ers. Sus. Array Ers. Sus. Array Ers. Sus. Array Read Array
Erase Susp. Array Ers. Susp. Read Config Ers. Susp. Read Query Erase (Done)
Array
Prog. Setup
Erase
Erase
Config
Prog. Setup
Erase
Erase
Status
Prog. Setup Prog. Setup
Erase
Erase
3UHOLPLQDU\
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Appendix Current/Next States, Sheet
Command Input (and Next State) Lock Setup (60H) Lock Down Confirm (2FH) Read Array Read Array Read Array Read Array Lock Operation (Done) Prot. Prog. Setup Prot. Prog. Setup Protection Register Program Protection Register Program (Not Done) Read Array Read Array
Current State
Read Config (90H)
Read Query (98H)
Prot. Prog. Setup (C0H)
Lock Confirm (01H)
Unlock Confirm (D0H)
Read Array Read Status Read Config. Read Query Lock Setup Lock Cmd. Error Lock Oper. (Done) Prot. Prog. Setup Prot. Prog. (Not Done) Prot. Prog. (Done) Prog. Setup Program (Not Done) Prog. Susp. Status Prog. Susp. Read Array Prog. Susp. Read Config. Prog. Susp. Read Query. Program (Done) Erase Setup Erase Cmd. Error Erase (Not Done) Erase Susp. Status Erase Suspend Array Eras Sus. Read Config Eras Sus. Read Query Ers.(Done)
Read Config. Read Config. Read Config. Read Config.
Read Query Read Query Read Query Read Query
Lock Setup Lock Setup Lock Setup Lock Setup
Prot. Prog. Setup Prot. Prog. Setup Prot. Prog. Setup Prot. Prog. Setup
Locking Command Error Read Config. Read Config. Read Query Read Query Lock Setup Lock Setup
Read Config.
Read Query
Lock Setup
Prot. Prog. Setup Program Program (Not Done)
Read Array
Prog. Susp. Read Config. Prog. Susp. Read Config. Prog. Susp. Read Config. Prog. Susp. Read Config. Read Config.
Prog. Susp. Read Query Prog. Susp. Read Query Prog. Susp. Read Query Prog. Susp. Read Query Read Query Lock Setup
Program Suspend Read Array
Program (Not Done) Program (Not Done) Program (Not Done) Program (Not Done) Read Array Erase (Not Done) Read Array
Program Suspend Read Array
Program Suspend Read Array
Program Suspend Read Array
Prot. Prog. Setup
Erase Command Error
Read Config.
Read Query
Lock Setup
Prot. Prog. Setup
Erase (Not Done) Ers. Susp. Read Config. Ers. Susp. Read Config. Erase Suspend Read Config. Erase Suspend Read Config. Read Config. Erase Suspend Read Query Erase Suspend Read Query Erase Suspend Read Query Erase Suspend Read Query Read Query Erase (Not Done) Erase (Not Done) Erase (Not Done) Erase (Not Done) Read Array
Lock Setup
Erase Suspend Read Array
Lock Setup
Erase Suspend Read Array
Lock Setup
Erase Suspend Read Array
Lock Setup Lock Setup
Erase Suspend Read Array Prot. Prog. Setup
3UHOLPLQDU\
28F800C3, 28F160C3, 28F320C3, 28F640C3
Appendix Program/Erase Flowcharts
Figure Automated Word Programming Flowchart
Start
Operation Write Write Command Program Setup Program Comments Data Data Data Program Addr Location Program Status Register Data Toggle Update Status Register Data Check SR.7 Ready Busy
Write
Program Address/Data
Read
Read Status Register
Standby
SR.7 Full Status Check Desired
Repeat subsequent programming operations. Full Status Check done after each program after sequence program operations. Write after last program operation reset device read array mode.
Program Complete
FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) SR.3 SR.4 SR.1 Program Successful
error detected, clear status register before attempting retry other error recovery.
Operation Standby
Command
Comments Check SR.3 Detect Check SR.4 Program Error Check SR.1 Attempted Program Locked Block Program Aborted
Range Error Programming Error
Standby
Standby
SR.3 MUST cleared, during program attempt, before further attempts allowed Write State Machine.
Attempted Program Locked Block Aborted
SR.1, SR.3 SR.4 only cleared Clear Staus Register Command, cases where multiple bytes programmed before full status checked.
3UHOLPLQDU\
28F800C3, 28F160C3, 28F320C3, 28F640C3
Figure Program Suspend/Resume Flowchart
Operation Write
Start
Command Program Suspend Read Status
Comments Data Addr Data=70H Addr=X Status Register Data Toggle Update Status Register Data Addr Check SR.7 Ready Busy Check SR.2 Program Suspended Program Completed
Write
Write
Write
Read
Read Status Register
Standby
SR.7 SR.2
Standby
Write
Read Array
Data Addr Read array data from block other than being programmed.
Program Completed
Read Program Resume
Write
Write
Data Addr
Read Array Data
Done Reading Write
Write
Program Resumed
Read Array Data
3UHOLPLQDU\
28F800C3, 28F160C3, 28F320C3, 28F640C3
Figure Automated Block Erase Flowchart
Start
Operation Command Comments Data Addr Within Block Erased Data Addr Within Block Erased Status Register Data Toggle Update Status Register Data Check SR.7 Ready Busy
Write
Write
Erase Setup
Write Block Address
Write
Erase Confirm
Read
Read Status Register
Suspend Erase Loop Suspend Erase
Standby
SR.7 Full Status Check Desired
Repeat subsequent block erasures. Full Status Check done after each block erase after sequence block erasures. Write after last write operation reset device read array mode.
Block Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) SR.3 SR.4,5 SR.5 SR.1 Block Erase Successful Attempted Erase Locked Block Aborted
SR.1, only cleared Clear Staus Register Command, cases where multiple bytes erased before full status checked. error detected, clear status register before attempting retry other error recovery. Operation Standby Command Comments Check SR.3 Detect Check SR.4,5 Both Command Sequence Error Check SR.5 Block Erase Error Check SR.1 Attempted Erase Locked Block Erase Aborted
Range Error
Standby
Command Sequence Error
Standby
Standby
Block Erase Error
MUST cleared, during erase attempt, before further attempts allowed Write State Machine.
3UHOLPLQDU\
28F800C3, 28F160C3, 28F320C3, 28F640C3
Figure Erase Suspend/Resume Flowchart
Operation Write
Start
Command Erase Suspend Read Status
Comments Data Addr Data=70H Addr=X Status Register Data Toggle Update Status Register Data Addr Check SR.7 Ready Busy Check SR.6 Erase Suspended Erase Completed
Write
Write
Write
Read
Read Status Register
Standby
SR.7 SR.6
Standby
Write
Read Array
Data Addr Read array data from block other than being erased.
Erase Completed
Read
Write
Erase Resume
Write
Data Addr
Read Array Data
Done Reading Write
Write
Erase Resumed
Read Array Data
3UHOLPLQDU\
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Figure Locking Operations Flowchart
Operation Write
Start
Command Config. Setup
Comments Data Addr Data= (Lock Block) (Unlock Block) (Lockdown Block) Addr=Within block lock Data Addr Block Lock Status Data Addr Second addr block Confirm Locking Change DQ1, DQ0. (See Block Locking State Table valid combinations.)
Write (Configuration Setup) Write 01H, D0H,
Write
Lock, Unlock, Lockdown Read Configuration Block Lock Status
Write (Optional) Read (Optional) Standby (Optional)
Write (Read Configuration)
Optional
Read Block Lock Status
Locking Change Confirmed? Write (Read Array)
Locking Change Complete
3UHOLPLQDU\
28F800C3, 28F160C3, 28F320C3, 28F640C3
Figure Protection Register Programming Flowchart
Start
Operation Write Write
Command Protection Program Setup Protection Program
Comments Data Data Data Program Addr Location Program Status Register Data Toggle Update Status Register Data Check SR.7 Ready Busy
Write (Protection Reg. Program Setup) Write Protect. Register Address/Data
Read
Standby
Read Status Register
SR.7 Full Status Check Desired
Protection Program operations only addressed within protection register address space. Addresses outside defined space will return error. Repeat subsequent programming operations. Full Status Check done after each program after sequence program operations. Write after last program operation reset device read array mode.
Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) SR.3, SR.4 Range Error SR.1, SR.4
Standby Operation Standby Command Comments SR.1 SR.3 SR.4 Prot. Reg. Prog. Error Register Locked: Aborted
Protection Register Programming Error Attempted Program Locked Register Aborted
Standby
SR.3 MUST cleared, during program attempt, before further attempts allowed Write State Machine.
SR.1, SR.4
SR.1, SR.3 SR.4 only cleared Clear Staus Register Command, cases multiple protection register program operations before full status checked. error detected, clear status register before attempting retry other error recovery.
Program Successful
3UHOLPLQDU\
28F800C3, 28F160C3, 28F320C3, 28F640C3
Appendix Common Flash Interface Query Structure
This appendix defines data structure "database" returned Common Flash Interface (CFI) Query command. System software should parse this structure gain critical information such block size, density, x8/x16, electrical specifications. Once this information been obtained, software will know which command sets enable flash writes, block erases, otherwise control flash component. Query part overall specification multiple command control interface descriptions called Common Flash Interface, CFI.
Query Structure Output
Query "database" allows system software gain information controlling flash component. This section describes device's CFI-compliant interface that allows host system access Query data. Query data always presented lowest-order data outputs (DQ0-7) only. numerical offset value address relative maximum width supported device. this family devices, Query table device starting address 10h, which word address devices. word-wide (x16) device, first bytes Query structure, ASCII, appear byte word addresses 11h. This CFI-compliant device outputs data upper bytes. Thus, device outputs ASCII byte (DQ0-7) high byte (DQ8-15). Query addresses containing more bytes information, least significant data byte presented lower address, most significant data byte presented higher address. following tables, addresses data represented hexadecimal notation, suffix been dropped. addition, since upper byte word-wide devices always "00h," leading "00" been dropped from table notation only lower byte value shown. device outputs assumed have upper byte this mode.
Table Summary Query Structure Output Function Device Mode
Device Offset Device Addresses Code ASCII Value
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Table Example Query Structure Output Devices
Word Addressing Offset A15-A0 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0051 0052 0059 P_IDLO P_IDHI A_IDLO A_IDHI Code D15-D0 PrVendor PrVendor TblAdr AltVendor Value Offset A7-A0 P_IDLO P_IDLO P_IDHI Byte Addressing Code D7-D0 PrVendor Value
Query Structure Overview
Query command causes flash component display Common Flash Interface (CFI) Query structure "database." structure sub-sections address locations summarized below.
Table Query Structure(1)
Offset (BA+2)h(2) 04-0Fh P(3) Block Status Register Reserved Query Identification String System Interface Information Device Geometry Definition Primary Intel-Specific Extended Query Table Sub-Section Name Description Manufacturer Code Device Code Block-Specific Information Reserved Vendor-Specific Information Command Vendor Data Offset Device Timing Voltage Information Flash Device Layout Vendor-Defined Additional Information Specific Primary Vendor Algorithm
NOTES: Refer Query Structure Output section offset detailed definition offset address function device width mode. beginning location Block Address (e.g., 08000h beginning location block when block size Kword). Offset defines which points Primary Intel-specific Extended Query Table.
3UHOLPLQDU\
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Block Lock Status Register
Block Status Register indicates whether erase operation completed successfully whether given block locked accessed flash program/erase operations. Block Erase Status (BSR.1) allows system software determine success last block erase operation. BSR.1 used just after power-up verify that supply accidentally removed during erase operation. This only reset issuing another erase operation block. Block Status Register accessed from word address within each block.
Table Block Status Register
Offset (BA+2)h
Length
Description Block Lock Status Register BSR.0 Block Lock Status Unlocked Locked BSR.1 Block Lock-Down Status locked down Locked down 2-7: Reserved future
Add. BA+2: BA+2:
Value (bit
BA+2: BA+2:
(bit (bit 2-7):
NOTE: beginning location Block Address (i.e., 008000h beginning location block word mode.)
Query Identification String
Identification String provides verification that component supports Common Flash Interface specification. also indicates specification version supported vendor-specified command set(s).
Table Identification
Offset Length Description Add. Code Value
Query-unique ASCII string "QRY" Primary vendor command control interface code 16-bit code vendor-specified algorithms Extended Query Table primary algorithm address Alternate vendor command control interface code 0000h means second vendor-specified algorithm exists Secondary algorithm Extended Query Table address 0000h means none exists
3UHOLPLQDU\
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System Interface Information
Table System Interface Information
Offset Length Description logic supply minimum program/erase voltage bits bits volts logic supply maximum program/erase voltage bits bits volts [programming] supply minimum program/erase voltage bits bits volts [programming] supply maximum program/erase voltage bits bits volts such that typical single word program time-out such that typical max. buffer write time-out such that typical block erase time-out such that typical full chip erase time-out such that maximum word program time-out times typical such that maximum buffer write time-out times typical such that maximum block erase time-out times typical such that maximum chip erase time-out times typical
Add.
Code
Value
11.4
12.6 512µs
3UHOLPLQDU\
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Device Geometry Definition
Table Device Geometry Definition
Offset Length Description such that device size number bytes Flash device interface: async async x8/x16 async 28:00,29:00 28:01,29:00 28:02,29:00 such that maximum number bytes write buffer Number erase block regions within device: means erase blocking; device erases "bulk" specifies number device partition regions with more contiguous same-size erase blocks. Symmetrically blocked partitions have blocking region Partition size (total blocks) (individual block size) Erase Block Region Information bits 0-15 number identical-size erase blocks bits 16-31 region erase block(s) size bytes Erase Block Region Information bits 0-15 number identical-size erase blocks bits 16-31 region erase block(s) size bytes Code table below
Device Geometry Definition Address Mbit Mbit Mbit Mbit
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Intel-Specific Extended Query Table
Certain flash features commands optional. Intel-Specific Extended Query table specifies this other similar types information.
Table Primary-Vendor Specific Extended Query
Offset(1) (P+0)h (P+1)h (P+2)h (P+3)h (P+4)h Length Description (Optional Flash Features Commands) Primary extended query table Unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Optional feature command support (1=yes, 0=no) bits 9-31 reserved; undefined bits "0." then another field optional features follows bit-30 field. (P+5)h (P+6)h (P+7)h (P+8)h Chip erase supported Suspend erase supported Suspend program supported Legacy lock/unlock supported Queued erase supported Instant individual block locking supported Protection bits supported Page mode read supported Synchronous read supported Address Code Value
(P+9)h
Supported functions after suspend: Read Array, Status, Query Other supported operations are: bits reserved; undefined bits Program supported after erase suspend
(P+A)h (P+B)h
Block status register mask bits 2-15 Reserved; undefined bits Block Lock-Bit Status Register active Block Lock-Down Status active logic supply highest performance program/ erase voltage bits value bits value volts optimum program/erase supply voltage bits value bits value volts
(P+C)h
(P+D)h
12.0
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Table Protection Register Information
Offset(1) (P+E)h (P+F)h (P+10)h (P+11)h Length Description (Optional Flash Features Commands) Number Protection register fields JEDEC space. "00h," indicates that protection bytes available Address Code Value byte
Protection Field Protection Description This field describes user-available Time Programmable (OTP) Protection register bytes. Some pre-programmed with deviceunique serial numbers. Others user programmable. Bits 0-15 point Protection register Lock byte, section's first byte. following bytes factory pre-programmed userprogrammable. bits Lock/bytes JEDEC-plane physical address bits 8-15 Lock/bytes JEDEC -plane physical high address bits 16-23 such that factory pre-programmed bytes bits 24-31 such that user programmable bytes Reserved future NOTE: variable pointer which defined offset 15h.
(P+12)h
byte
(P+13)h
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28F800C3, 28F160C3, 28F320C3, 28F640C3
Appendix Architecture Block Diagram
DQ0-DQ15
VCCQ Output Buffer Input Buffer
Output Multiplexer
Status Register
Data Register
Identifier Register
Logic Command User Interface
Power Reduction Control A0-A19 Y-Decoder Input Buffer 4-KWord Parameter Block
Data Comparator
Y-Gating/Sensing 4-KWord Parameter Block 32-KWord Main Block
Write State Machine 32-KWord Main Block
Program/Erase Voltage Switch
Address Latch Address Counter
X-Decoder
3UHOLPLQDU\
28F800C3, 28F160C3, 28F320C3, 28F640C3
Appendix Word-Wide Memory Diagrams
8-Mbit Word-Wide Memory Addressing Boot Size (KW)
Bottom Boot Size (KW)
Mbit
7F000-7FFFF 7E000-7EFFF 7D000-7DFFF 7C000-7CFFF 7B000-7BFFF 7A000-7AFFF 79000-79FFF 78000-78FFF 70000-77FFF 68000-6FFFF 60000-67FFF 58000-5FFFF 50000-57FFF 48000-4FFFF 40000-47FFF 38000-3FFFF 30000-37FFF 28000-2FFFF 20000-27FFF 18000-1FFFF 10000-17FFF 08000-0FFFF 00000-07FFF
Mbit
78000-7FFFF 70000-77FFF 68000-6FFFF 60000-67FFF 58000-5FFFF 50000-57FFF 48000-4FFFF 40000-47FFF 38000-3FFFF 30000-37FFF 28000-2FFFF 20000-27FFF 18000-1FFFF 10000-17FFF 08000-0FFFF 07000-07FFF 06000-06FFF 05000-05FFF 04000-04FFF 03000-03FFF 02000-02FFF 01000-01FFF 00000-00FFF
3UHOLPLQDU\
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16-Mbit, 32-Mbit, 64-Mbit Word-Wide Memory Addressing
Boot Size (KW) Mbit FF000-FFFFF FE000-FEFFF FD000-FDFFF FC000-FCFFF FB000-FBFFF FA000-FAFFF F9000-F9FFF F8000-F8FFF F0000-F7FFF E8000-EFFFF E0000-E7FFF D8000-DFFFF D0000-D7FFF C8000-CFFFF C0000-C7FFF B8000-BFFFF B0000-B7FFF A8000-AFFFF A0000-A7FFF 98000-9FFFF 90000-97FFF 88000-8FFFF 80000-87FFF 78000-7FFFF 70000-77FFF 68000-6FFFF 60000-67FFF 58000-5FFFF 50000-57FFF 48000-4FFFF 40000-47FFF 38000-3FFFF 30000-37FFF 28000-2FFFF 20000-27FFF 18000-1FFFF 10000-17FFF 08000-0FFFF 00000-07FFF Mbit Mbit Size (KW) This column continues next page Mbit Bottom Boot Mbit Mbit 3F8000-3FFFFF 3F0000-3F7FFF 3E8000-3EFFFF 3E0000-3E7FFF 3D8000-3DFFFF 3D0000-3D7FFF 3C8000-3CFFFF 3C0000-3C7FFF 3B8000-3BFFFF 3B0000-3B7FFF 3A8000-3AFFFF 3A0000-3A7FFF 398000-39FFFF 390000-397FFF 388000-38FFFF 380000-387FFF 378000-37FFFF 370000-377FFF 368000-36FFFF 360000-367FFF 358000-35FFFF 350000-357FFF 348000-34FFFF 340000-347FFF 338000-33FFFF 330000-337FFF 328000-32FFFF 320000-327FFF 318000-31FFFF 310000-317FFF 308000-30FFFF 300000-307FFF 2F8000-2FFFFF 2F0000-2F7FFF 2E8000-2EFFFF 2E0000-2E7FFF 2D8000-2DFFFF 2D0000-2D7FFF 2C8000-2CFFFF 2C0000-2C7FFF 2B8000-2BFFFF 2B0000-2B7FFF 2A8000-2AFFFF 2A0000-2A7FFF 298000-29FFFF 290000-297FFF 288000-28FFFF 280000-287FFF 278000-27FFFF 270000-277FFF
1FF000-1FFFFF 3FF000-3FFFFF 1FE000-1FEFFF 3FE000-3FEFFF 1FD000-1FDFFF 3FD000-3FDFFF 1FC000-1FCFFF 3FC000-3FCFFF 1FB000-1FBFFF 3FB000-3FBFFF 1FA000-1FAFFF 3FA000-3FAFFF 1F9000-1F9FFF 3F9000-3F9FFF 1F8000-1F8FFF 3F8000-3F8FFF 1F0000-1F7FFF 3F0000-3F7FFF 1E8000-1EFFFF 3E8000-3EFFFF 1E0000-1E7FFF 3E0000-3E7FFF 1D8000-1DFFFF 3D8000-3DFFFF 1D0000-1D7FFF 3D0000-3D7FFF 1C8000-1CFFFF 3C8000-3CFFFF 1C0000-1C7FFF 3C0000-3C7FFF 1B8000-1BFFFF 3B8000-3BFFFF 1B0000-1B7FFF 3B0000-3B7FFF 1A8000-1AFFFF 3A8000-3AFFFF 1A0000-1A7FFF 3A0000-3A7FFF 198000-19FFFF 398000-39FFFF 190000-197FFF 390000-397FFF 188000-18FFFF 388000-38FFFF 180000-187FFF 380000-387FFF 178000-17FFFF 378000-37FFFF 170000-177FFF 370000-377FFF 168000-16FFFF 368000-36FFFF 160000-167FFF 360000-367FFF 158000-15FFFF 358000-35FFFF 150000-157FFF 350000-357FFF 148000-14FFFF 348000-34FFFF 140000-147FFF 340000-347FFF 138000-13FFFF 338000-33FFFF 130000-137FFF 330000-337FFF 128000-12FFFF 328000-32FFFF 120000-127FFF 320000-327FFF 118000-11FFFF 318000-31FFFF 110000-117FFF 310000-317FFF 108000-10FFFF 308000-30FFFF 100000-107FFF 300000-307FFF 0F8000-0FFFFF 2F8000-2FFFFF 0F0000-0F7FFF 2F0000-2F7FFF 0E8000-0EFFFF 2E8000-2EFFFF 0E0000-0E7FFF 2E0000-2E7FFF 0D8000-0DFFFF 2D8000-2DFFFF 0D0000-0D7FFF 2D0000-2D7FFF 0C8000-0CFFFF 2C8000-2CFFFF 0C0000-0C7FFF 2C0000-2C7FFF 0B8000-0BFFFF 2B8000-2BFFFF 0B0000-0B7FFF 2B0000-2B7FFF 0A8000-0AFFFF 2A8000-2AFFFF This column continues next page
3UHOLPLQDU\
28F800C3, 28F160C3, 28F320C3, 28F640C3
16-Mbit, 32-Mbit, 64-Mbit Word-Wide Memory Addressing
Boot Size (KW) Mbit Mbit 0A0000-0A7FFF 098000-09FFFF 090000-097FFF 088000-08FFFF 080000-087FFF 078000-07FFFF 070000-077FFF 068000-06FFFF 060000-067FFF 058000-05FFFF 050000-057FFF 048000-04FFFF 040000-047FFF 038000-03FFFF 030000-037FFF 028000-02FFFF 020000-027FFF 018000-01FFFF 010000-017FFF 008000-00FFFF 000000-007FFF Mbit Size (KW) Mbit Bottom Boot Mbit Mbit 268000-26FFFF 260000-267FFF 258000-25FFFF 250000-257FFF 248000-24FFFF 240000-247FFF 238000-23FFFF 230000-237FFF 228000-22FFFF 220000-227FFF 218000-21FFFF 210000-217FFF 208000-20FFFF 200000-207FFF 1F8000-1FFFFF 1F0000-1F7FFF 1E8000-1EFFFF 1E0000-1E7FFF 1D8000-1DFFFF 1D0000-1D7FFF 1C8000-1CFFFF 1C0000-1C7FFF 1B8000-1BFFFF 1B0000-1B7FFF 1A8000-1AFFFF 1A0000-1A7FFF 198000-19FFFF 190000-197FFF 188000-18FFFF 180000-187FFF 178000-17FFFF 170000-177FFF 168000-16FFFF 160000-167FFF 158000-15FFFF 150000-157FFF 148000-14FFFF 140000-147FFF 138000-13FFFF 130000-137FFF 128000-12FFFF 120000-127FFF 118000-11FFFF 110000-117FFF 108000-10FFFF 100000-107FFF F8000-FFFFF F0000-F7FFF E8000-EFFFF E0000-E7FFF D8000-DFFFF D0000-D7FFF C8000-CFFFF C0000-C7FFF
2A0000-2A7FFF 298000-29FFFF 290000-297FFF 288000-28FFFF 280000-287FFF 278000-27FFFF 270000-277FFF 268000-26FFFF 260000-267FFF 258000-25FFFF 250000-257FFF 248000-24FFFF 240000-247FFF 238000-23FFFF 230000-237FFF 228000-22FFFF 220000-227FFF 218000-21FFFF 210000-217FFF 208000-21FFFF 200000-207FFF 1F8000-1FFFFF 1F0000-1F7FFF 1E8000-1EFFFF 1E0000-1E7FFF 1D8000-1DFFFF 1D0000-1D7FFF 1C8000-1CFFFF 1C0000-1C7FFF 1B8000-1BFFFF 1B0000-1B7FFF 1A8000-1AFFFF 1A0000-1A7FFF 198000-19FFFF 190000-197FFF 188000-18FFFF 180000-187FFF 178000-17FFFF 170000-177FFF 168000-16FFFF 160000-167FFF 158000-15FFFF 150000-157FFF 148000-14FFFF 140000-147FFF 138000-13FFFF 130000-137FFF 128000-12FFFF 120000-127FFF 118000-11FFFF 110000-117FFF 108000-10FFFF 100000-107FFF 0F8000-0FFFFF This column continues next page
1F8000-1FFFFF 1F0000-1F7FFF 1E8000-1EFFFF 1E0000-1E7FFF 1D8000-1DFFFF 1D0000-1D7FFF 1C8000-1CFFFF 1C0000-1C7FFF 1B8000-1BFFFF 1B0000-1B7FFF 1A8000-1AFFFF 1A0000-1A7FFF 198000-19FFFF 190000-197FFF 188000-18FFFF 180000-187FFF 178000-17FFFF 170000-177FFF 168000-16FFFF 160000-167FFF 158000-15FFFF 150000-157FFF 148000-14FFFF 140000-147FFF 138000-13FFFF 130000-137FFF 128000-12FFFF 120000-127FFF 118000-11FFFF 110000-117FFF 108000-10FFFF 100000-107FFF F8000-FFFFF F8000-FFFFF F0000-F7FFF F0000-F7FFF E8000-EFFFF E8000-EFFFF E0000-E7FFF E0000-E7FFF D8000-DFFFF D8000-DFFFF D0000-D7FFF D0000-D7FFF C8000-CFFFF C8000-CFFFF C0000-C7FFF C0000-C7FFF This column continues next page
3UHOLPLQDU\
28F800C3, 28F160C3, 28F320C3, 28F640C3
16-Mbit, 32-Mbit, 64-Mbit Word-Wide Memory Addressing
Boot Size (KW) Mbit Mbit Mbit 0F0000-0F7FFF 0E8000-0EFFFF 0E0000-0E7FFF 0D8000-0DFFFF 0D0000-0D7FFF 0C8000-0CFFFF 0C0000-0C7FFF 0B8000-0BFFFF 0B0000-0B7FFF 0A8000-0AFFFF 0A0000-0A7FFF 098000-09FFFF 090000-097FFF 088000-08FFFF 080000-087FFF 078000-07FFFF 070000-077FFF 068000-06FFFF 060000-067FFF 058000-05FFFF 050000-057FFF 048000-04FFFF 040000-047FFF 038000-03FFFF 030000-037FFF 028000-02FFFF 020000-027FFF 018000-01FFFF 010000-017FFF 008000-00FFFF 000000-007FFF Size (KW) Mbit B8000-BFFFF B0000-B7FFF A8000-AFFFF A0000-A7FFF 98000-9FFFF 90000-97FFF 88000-8FFFF 80000-87FFF 78000-7FFFF 70000-77FFF 68000-6FFFF 60000-67FFF 58000-5FFFF 50000-57FFF 48000-4FFFF 40000-47FFF 38000-3FFFF 30000-37FFF 28000-2FFFF 20000-27FFF 18000-1FFFF 10000-17FFF 08000-0FFFF 07000-07FFF 06000-06FFF 05000-05FFF 04000-04FFF 03000-03FFF 02000-02FFF 01000-01FFF 00000-00FFF Bottom Boot Mbit B8000-BFFFF B0000-B7FFF A8000-AFFFF A0000-A7FFF 98000-9FFFF 90000-97FFF 88000-8FFFF 80000-87FFF 78000-7FFFF 70000-77FFF 68000-6FFFF 60000-67FFF 58000-5FFFF 50000-57FFF 48000-4FFFF 40000-47FFF 38000-3FFFF 30000-37FFF 28000-2FFFF 20000-27FFF 18000-1FFFF 10000-17FFF 08000-0FFFF 07000-07FFF 06000-06FFF 05000-05FFF 04000-04FFF 03000-03FFF 02000-02FFF 01000-01FFF 00000-00FFF Mbit B8000-BFFFF B0000-B7FFF A8000-AFFFF A0000-A7FFF 98000-9FFFF 90000-97FFF 88000-8FFFF 80000-87FFF 78000-7FFFF 70000-77FFF 68000-6FFFF 60000-67FFF 58000-5FFFF 50000-57FFF 48000-4FFFF 40000-47FFF 38000-3FFFF 30000-37FFF 28000-2FFFF 20000-27FFF 18000-1FFFF 10000-17FFF 08000-0FFFF 07000-07FFF 06000-06FFF 05000-05FFF 04000-04FFF 03000-03FFF 02000-02FFF 01000-01FFF 00000-00FFF
3UHOLPLQDU\
28F800C3, 28F160C3, 28F320C3, 28F640C3
Appendix Device Table
Read Configuration Addresses Data Item Manufacturer Code Device Code 8-Mbit 16-T 8-Mbit 16-B 16-Mbit 16-T 16-Mbit 16-B 32-Mbit 16-T 32-Mbit 16-B 64-Mbit 16-T 64-Mbit 16-B 00001 00001 00001 00001 00001 00001 00001 00001 88C0 88C1 88C2 88C3 88C4 88C5 88CC 88CD Address 00000 Data 0089
NOTE: Other locations within configuration address space reserved Intel future use.
3UHOLPLQDU\
28F800C3, 28F160C3, 28F320C3, 28F640C3
Appendix Protection Register Addressing
Word-Wide Protection Register Addressing Word LOCK Both Factory Factory Factory Factory User User User User
NOTE: address lines specified above table must when accessing Protection Register, i.e., A21-A8
3UHOLPLQDU\
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