Differential Clock Distribution Chip Meets Exceeds Requirements A

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Differential Clock Distribution Chip Meets Exceeds Requirements A

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PI90LV211/PI90LVT211
Differential Clock Distribution Chip
Meets Exceeds Requirements ANSI TIA/EIA-644-1995 Designed Clocking Rates 320MHz Operates from single 3.3-V Supply Low-Voltage Differential Signaling (LVDS) with Output Voltages ±350mV into 100-ohm load Choice between LVDS clock input Synchronous Enable/Disable Multiplexed clock input Internal kohm pullup resistor control pins have 110-ohm termination (PI90LVT211) Common individual Enable/Disable control 50ps Output-to-Output Skew ±24ps Period Jitter Pins High Impedance when disabled with <1.5V Inputs Tolerant Power Dissipation (TBD) P190LV211 functionally compatible with Motorolas (PECL) 10E211/MC100E211 >12kV Protection 28-pin TSSOP QSOP packages
Product Description
PI90LV211 implements voltage differential signaling (LVDS) achieve clocking rates high with skew. PI90LV211 skew fanout device designed explicitly skew clock distribution applications. device features multiplexed clock input allow distribution lower speed scan test clock with high-speed system clock. When will select differential clock input. Both common enable individual output enables provided. When asserted positive output will next negative transition SCLK) input. enable function synchronous that outputs will only enabled/disabled when they already state. This avoids chance generating runt clock pulse when device enabled/disabled happen with asynchronous control. internal flip flop clocked falling edge input clock, therefore associated specification limits referenced negative edge clock input. Individual synchronous enable controls multiplexed clock inputs make this device ideal first level distribution unit distribution tree. individual enables could used allow disabling individual cards backplane fault tolerant designs.
Logic Block Diagram Pinout Assignment
Function Table
CLK/CLK SCLK SCLK
CLK1OUT+ CLK1OUT-
SCLK
CLK2OUT+ CLK2OUT-
PI90LVT211 Only
CLK3OUT+ CLK3OUT-
disables individual banks disables banks Negative transition SCLK High Impedance
CLK4OUT+ CLK4OUT-
CLK5OUT+ CLK5OUT-
CLK6OUT+ CLK6OUT-
PS8535A
09/11/01
PI90LV211/PI90LVT211 Differential Clock Distribution Chip
Electrical Characteristics over Recommended Operating Conditions (unless otherwise noted).
Symbol VOC(SS) VOC(SS) VOC(PP) IO(OFF) RTERM Parame Differential output voltage magnitude Change differential output voltage magnitude between logic states Steady- state common- mode output voltage Change steady- state common- mode output voltage between logic states Peak- peak common- mode output voltage Supply Current High- level input current Low- level input current Short- circuit output current High- impedance output current Power- output current Input capacitance, Output capacitance Termination Resistor Enabled, Disabled, 0.8V VODOUT+ VODOUT 1.5V, 2.4V (4E6t) +0.5V (4E6t) +0.5V, Disabled PI90LVT211 Figure Conditions Figures 1.125 1.30 Typ.(1) 1.60 Units
PS8535A
09/11/01
PI90LV211/PI90LVT211 Differential Clock Distribution Chip
Switching Characteristics over Recommended Operating Conditions (unless otherwise noted)(8,9).
Characte Propagation Output CLKOUT SCLK CLKOUT CLKOUT able Time SCLK CLKOUT Symbol tPLH tPHL Typ. 3.24 tPHZ tPLZ tPZH tPZL tskew 0.20 0.125 0.800 1200 Units Condition
Part-to-Part (Diff) (SE), SCLK With Device Skew Cycle -to-Cycle Jitte riod Jitte Time Hold Time ENx, inimum Input Swing (CLK) Com. Range (CLK) /Fall Time Duty Cycle tortion Puls tPLH tPHL) SCLK CLKOUT± CLKOUT± Channe l-to-Channe aximum rating
Figure Figure
tjit(cc) tjit(per)
VCMR tSK1R tSK1R tSK2R
Notes: Within-Device skew defined identical transitions similar paths through device. Setup, Hold, Disable times relative falling edge SCLK. Minimum input swing which parameters guaranteed. Full LVDS output swings will generated with only 50mV input swings. range which high level input swing must fall while meeting spec. tSKIR difference receiver propagation delay (tPLH-tPHL) device, duty cycle distortion output given temperature VCC. propagation delay specification device-to-device worst case over process, voltage, temperature. tSK2R difference receiver propagation delay between channels same device outputs switching same direction. This parameter guaranteed design characterization. Generator input conditions: trtf 1ns, duty cycle, differential (1.10V 1.35V peak-peak). Output Criteria: 60%/40% duty cycle, (max) 0-4V, (min) 2.7V, Load (stray plus probes). includes probe fixture capacitance. Generator waveform tests unless otherwise specified: MHz, ohms, 1ns, (35%-65%). ensure fastest propagation delay minimum skew, clock input edge rates should slower than 1ns/V; control signals slower than 3ns/V.
PS8535A
09/11/01
PI90LV211/PI90LVT211 Differential Clock Distribution Chip
Parameter Measurement Information
DOUT- VODOUT+ VODOUT-
DOUT+
(VODOUT++VODOUT-)/2
Figure Voltage Current Definitions
DOUT+ Input DOUT-
3.75k 3.75k
VTEST 2.4V
Figure Test Circuit
DOUT+ 49.9 places) Input DOUT-
VOC(PP) VOC(SS)
Note: input pulses supplied generator having following characteristics: 1ns, Pulse Repetition Rate (PRR) Mpps, Pulse width ±0.2ns. includes instrumentation fixture capacitance within 0.06m D.U.T. measurement VOC(PP) made test equipment with bandwidth least 300MHz. Figure Test Circuit Definitions Driver Common-Mode Output Voltage
PS8535A
09/11/01
PI90LV211/PI90LVT211 Differential Clock Distribution Chip
Parameter Measurement Information (continued)
1.4V 0.8V
tPLH tPHL
Input DOUT+ Input DOUT-
10pF places)
Output
VOD(H) VOD(L)
100%
Note: input pulses supplied generator having following characteristics: 1ns, Pulse Repetition Rate (PRR) Mpps, Pulse width ±0.2ns. includes instrumentation fixture capacitance within 0.06m D.U.T. Figure Test Circuit, Timing, Voltage Definitions Differential Output Signal
DOUT+ 0.8V DOUT- Input
49.9 places)
VODOUT+ VODOUT-
1.2V
Input 1.4V 0.8V
tPZH VODOUT+
VODOUT-
tPHZ 1.4V 1.3V 1.2V
tPZL VODOUT-
VODOUT+
tPLZ 1.2V 1.1V
Note: input pulses supplied generator having following characteristics: 1ns, Pulse Repetition Rate (PRR) Mpps, Pulse width ±10ns. includes instrumentation fixture capacitance within 0.06m D.U.T. Figure Enable Disable Time Circuit Definitions
PS8535A
09/11/01
Yx,FBOUT
Yx,FBOUT
FBOUT
FBOUT
FBOUT
FBOUT
jit(cc) cycle cycle
Figure Cycle-to-Cycle Jitter
cycle
Figure Period Jitter
jit(per) cycle
cycle
cycle
PI90LV211/PI90LVT211 Differential Clock Distribution Chip
PS8535A
09/11/01
BACKPLANE
PI90LV211/PI90LVT211 Differential Clock Distribution Chip
General Description
PI90LV211 fanout tree designed explicitly low-skew, high-speed clock distribution. device targeted work conjunction with PI90LV14 device provide another level flexibility design implementation clock distribution trees. individual synchronous enable controls multiplexed clock inputs make device ideal first level distribution unit distribution tree. device provides ability distribute lower speed scan test clock along with high-speed system clock ease design system diagnostics self test procedures. individual enables could used allow disabling individual cards backplane fault tolerant designs. Handling Open Inputs Outputs With simultaneous switching characteristics tight skew specifications P90LV211, handling unused outputs becomes critical. minimize noise generated outputs should terminated pairs, i.e. both true compliment outputs should terminated even only outputs will used system. With both complimentary pairs terminated, current pins will remain essentially constant thus inductance induced voltage glitches will occur. glitches will result distorted output waveforms degradations skew performance device. package parasitics 28-lead package cause signals given influenced signals adjacent pins. PI90LV211 characterized tested with outputs switching, therefore numbers data book guaranteed only this situation. outputs PI90LV211 needed there desire save power, unused output pairs left unterminated. Unterminated outputs influence propagation delay adjacent pins 15ps20ps. Therefore, under these conditions, this 15ps20ps needs added overall skew device. Pins which separated package corner considered adjacent pins context propagation delay influence. Therefore outputs single side package terminated, specification limits data sheet will apply. Using Enable Pins Both common enable (CEN) individual enables (ENx) synchronous SCLK input depending which selected. active signals clocked into enable flip flops negative edges PI90LV211 clock inputs. this way, devices will only disabled when outputs already state. internal propagation delays such that delay output through distribution buffers less than that through enable flip flops. This will ensure that disabling device will slice time clock pulse. initial power enable flip flops will randomly attain stable state; therefore precautions should taken initial power ensure PI90LV211 desired state.
PI90LV14 PI90LV211
PI90LV14
Figure Standard PI90LV211 LVDS Application
PS8535A 09/11/01
PI90LV211/PI90LVT211 Differential Clock Distribution Chip
28-Pin TSSOP Package
.169 .177
.378 .386 .047 1.20 SEATING PLANE 0.45 0.75 .018 .030
.004 .008
0.09 0.20
.252
X.XX DENOTES CONTROLLING X.XX DIMENSIONS MILLIMETERS
.0256 0.65
.007 .012 0.19 0.30
.002 .006
0.05 0.15
28-Pin QSOP Package
.008 0.20 MIN.
0.150 0.157
3.81 3.99
Guage Plane
.008 .013 0.20 0.33
.010 0.254
.386 9.804 .394 10.009
Detail
.016 .035 0.41 0.89
.041 1.04
0°-6°
.033 0.84
1.35 .053 1.75 .069 SEATING PLANE
.015
Detail
.007 0.178 .010 0.254 0.41 .016 1.27 .050 .228 .244 5.79 6.19
.025 0.635
.008 0.203 .012 0.305
.004 0.101 .010 0.254
X.XX DENOTES DIMENSIONS X.XX MILLIMETERS
Ordering Information
Orde ring Code PI90LV211L PI90LV211Q Package Type 173- TSSO 150- TSSOP rating Range 40°C 85°C
Pericom Semiconductor Corporation 2380 Bering Drive Jose, 95131 1-800-435-2336 (408) 435-1100 http://www.pericom.com
PS8535A 09/11/01

Differential Clock Distribution Chip Meets Exceeds Requirements A

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