S3098 power operation Silicon Germanium BiCMOS technology Complie

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S3098 power operation Silicon Germanium BiCMOS technology Complie

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Part Number S3098 Revision 2001
S3098
power operation Silicon Germanium BiCMOS technology Complies with Telcordia ITU-T specifications Supports G.709 Gigabit Ethernet rates Supports OC-192 OC-192 with Forward Error Correction (FEC) rates Integrated phase lock loop Postamp serial input Tunable from 9.953 10.709 155.52 REFCLK input equivalent rate) 16-bit parallel, 622.08 Mbps LVDS data path equivalent rate) Lock detect indicator jitter differential single-ended serial interface Recovered 622.08 clock output equivalent rate) Accepts Active High Active signal detect inputs loss light (programmable) Accepts LVCMOS LVPECL signal detect inputs Synthesizes parallel output clock during loss-of-signal conditions Power (typ) Compact 148-pin CBGA package
DEVICE SPECIFICATION
SONET/SDH/AOC-192 1:16 Power Receiver w/CDR/Postamp
APPLICATIONS
SONET/SDH-based transmission systems SONET/SDH modules SONET/SDH test equipment Aover SONET/SDH Section repeaters Drop Multiplexers (ADM) Broad-band cross-connects Fiber optic terminators Fiber optic test equipment
GENERAL DESCRIPTION
S3098 power 1:16 receiver with Clock/Data Recovery (CDR) integrated postamp fully integrated C-192 ialization/clock data recovery device. S3098 receives OC-192 scrambled serial signal recovers clock. This recovered clock then used re-time demultiplex data into parallel lines. loss-ofsignal condition occurs LCKREFN asserted Low), internal Phase Lock Loop (PLL) will lock local 155.52 Reference Clock (REFCLK) equivalent rate) provide stable clock down-stream purposes. S3098 limiting postamp serial input small signal gain. jitter LVDS interface guarantees compliance with error rate requirements Telcordia ITU-T standards. Figure System Block Diagram, shows typical network application.
Figure System Block Diagram
AMCC GANGES GANGES HUDSON
AMCC S3097 AMCC S3098 AMCC S3090
AMCC S3090
AMCC S3098 AMCC S3097
AMCC GANGES GANGES HUDSON
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S3098 SONET/SDH/AOC-192 1:16 Power Receiver w/CDR/Postamp
Revision 2001
DEVICE SPECIFICATION
CONTENTS
FEATURES. APPLICATIONS GENERAL DESCRIPTION CONTENTS FIGURES TABLES S3098 OVERVIEW Suggested Interface Devices S3098 DESCRIPTION Serial Data (SERDATIP/N) Reference Clock (REFCLKP/N) Loop Filter (CAP1, CAP2) Lock Reference (LCKREFN) Signal Detect (SDLVPECLN/SDLVCMOSN) Reset (RSTB) Factory Test (TSTSIG, TESTB) Parallel Output Clock (POCLKP/N) Parallel Output Data (POUTP/N[15:0]) Lock Detect (LOCKDET) Recovered 622.08 Clock (RX622MCKP/N) S3098 FUNCTIONAL DESCRIPTION Receiver Description Postamp Clock Recovery Lock Detect Serial-to-Parallel Converter Power Sequencing ORDERING INFORMATION
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S3098 SONET/SDH/AOC-192 1:16 Power Receiver w/CDR/Postamp
Revision 2001
DEVICE SPECIFICATION
FIGURES
Figure System Block Diagram Figure Functional Block Diagram Figure S3098 Pinout (Top View) Figure Compact 148-pin CBGA Package Figure Parallel Data Output Delay from POCLK Figure Differential Voltage Measurement Figure Single-Ended Data Input Voltage Measurement Figure S3098 LVDS Output LVDS Input Figure -5.2 Post S3098 Input Coupled Termination Figure -5.2 S3098 Coupled Termination Figure +3.3 Differential LVPECL Driver S3098 LVPECL Reference Clock Input, Coupled Termination Figure External Loop Filter Figure Single-Ended Termination Scheme
TABLES
Table Reference Frequency Table SDLVCMOSN Connections when using SDLVPECLN Input Table SDLVPECLN Connections when using SDLVCMOSN Input Table Input Description Assignment Table Output Descriptions Assignment Table Common Descriptions Assignment Table Package Thermals Table Performance Specifications Table Absolute Maximum Ratings Table Recommended Operating Conditions Table Internally Biased Differential Input Characteristics Table LVDS Output Characteristics Table Internally Biased Differential LVPECL Input Characteristics (REFCLKP/N) Table Single-Ended LVPECL Input Characteristics (SDLVPECLN) Table LVCMOS Input Characteristics Table LVCMOS Output Characteristics Table Characteristics Table External Loop Filter Components
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S3098 SONET/SDH/AOC-192 1:16 Power Receiver w/CDR/Postamp S3098 OVERVIEW
S3098 Clock Data Recovery Unit (CDR) with Demultiplexer (DeMUX) implements SONET/SDH deserialization functions. Figure Functional Block Diagram, shows basic operation chip. This chip used implement front SONET equipment, which consists primarily parallel transmit interface serial receive interface. chip includes clock data recovery, serial-to-parallel conversion system timing. sequence receiver operations S3098 follows: Serial input limiting postamp Clock data recovery Serial-to-parallel conversion 16-bit parallel output
Revision 2001
DEVICE SPECIFICATION
Suggested Interface Devices
AMCC AMCC AMCC AMCC AMCC AMCC AMCC AMCC AMCC GANGES (S19202) GANGES (S19202CBI20) HUDSON (S19203) MEKONG (S19204) S2509 S3090 S3095 S3097 S3196 OC-192 Mapper OC-192 Mapper Framer, Digital Wrapper OC-192 Pointer Processor Quad backplane device Gbps Gbps with OC-192 Transmitter Gbps Limiting
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SDLVCMOSN
Lock (Active High) BUFFER LEGEND LVDS LVPECL LVCMOS
SDLVPECLN
LCKREFN
S3098 SONET/SDH/AOC-192 1:16 Power Receiver w/CDR/Postamp
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POST
SERDATIP
Figure Functional Block Diagram
SERDATIN
Phase Frequency Detector
RSTB
CAP1
POUTP[15:0] POUTN[15:0]
Pass Filter
1:16 Serial Parallel
CAP2
VCC_3.3v
REFCLKP
VCC_3.3v
REFCLKN
RX622MCKP RX622MCKN
Voltage Controlled Oscillator Clock Divider
POCLKP
POCLKN
TSTSIG
Lock Detection Circuitry
LOCKDET
DEVICE SPECIFICATION
TESTB
Revision 2001
S3098 SONET/SDH/AOC-192 1:16 Power Receiver w/CDR/Postamp S3098 DESCRIPTION
Serial Data (SERDATIP/N) Serial Data (SERDATIP/N) pins differential Current Mode Logic (CML) inputs. They receive inputs from optics module other upstream logic device. S3098 extracts clock from SERDATIP/N inputs provides recovered clock (POCLKP/N) with re-timed parallel data. These pins internally biased terminated line-to-line. Reference Clock (REFCLKP/N) Reference Clock (REFCLKP/N) pins LVPECL 155.52 equivalent rate) input used establish initial operating frequency clock recovery PLL. REFCLKP/N also used absence data maintain lock. This input internally biased terminated line-to-line. Most implementations require coupling. requirements. Loop Filter (CAP1, CAP2) external loop filter capacitor resistors connected CAP1 CAP2 pins. These devices should surrounded ground shield. Component values should stated Table External Loop Filter Components. Lock Reference (LCKREFN) LVCMOS Lock Reference (LCKREFN) signal, when asserted Low, will force lock local Reference Clock (REFCLK) well de-assert LOCKDET. Signal Detect (SDLVPECLN/SDLVCMOSN) types signal detect inputs (SDLVPECLN/ SDLVCMOSN) provided, LVPECL LVCMOS. LVPECL input should driven optical transceivers with LVPECL signal detect output, LVCMOS input should driven optical transceivers with LVCMOS signal detect output. LVPECL input internally pulled down. These inputs used with optics modules that either active active High loss light. optics module with LVPECL output should connected SDLVPECLN input. Connect SDLVCM Connections when using SDLVPECLN Input. optics module with LVCMOS output should connected SDLVCMOSN input. Connect SDLVPECLN shown Table SDLVPECLN Connections when using SDLVCMOSN Input. Reset (RSTB)
SDLVCMOSN
Revision 2001
DEVICE SPECIFICATION
Table Reference Frequency
Input Data Rate (SERDATIP/N) 9.953 Gbps 10.234 Gbps 10.317 Gbps 10.402 Gbps 10.488 Gbps 10.575 Gbps 10.664 Gbps 10.709 Gbps Required Reference Frequency (REFCLK) 155.52 159.91 161.20 162.53 163.87 165.23 166.63 167.33
Table SDLVCMOSN Connections when using SDLVPECLN Input
Optics Device Active loss light Connect Optics Device Active High loss light Connect VCC_2.5V
Table SDLVPECLN Connections when using SDLVCMOSN Input
Optics Device Active loss light SDLVPECLN Connect Optics Device Active High loss light Connect VCC_3.3V1
Connecting VCC_3.3 permitted under static conditions.
master Reset (RSTB) LVCMOS pin, when asserted Low, asynchronously resets device. normal operation, connect VCC_2.5 through resistor. This should active accurately reset device. Factory Test (TSTSIG, TESTB) LVCMOS factory test (TSTSIG, TESTB) pins test factory purposes only. normal operation, connect VCC_2.5 through resistor.
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S3098 SONET/SDH/AOC-192 1:16 Power Receiver w/CDR/Postamp
Parallel Output Clock (POCLKP/N) Parallel Output Clock (POCLKP/N) LVDS output internally regenerated clock which used transfer demultiplexed data from internal holding register output register, which drives POUTP/N [15:0]. This clock synchronized with parallel output data must inverted (cross traces printed wire board) compliant from module perspective. parallel outputs internally terminated with ground (GND). Parallel Output Data (POUTP/N[15:0]) Parallel Output Data (POUTP/N[15:0]) LVDS outputs re-timed data, output from Demultiplexer (Demux) rate 622.08 Mbps equivalent rate). most significant first received. data re-timed synchronized Parallel Output Clock (POCLKP/N). These outputs internally terminated with GND. This typically connected framer, mapper digital wrapper e.g. HUDSON).
Revision 2001
DEVICE SPECIFICATION
Lock Detect (LOCKDET) When LVCMOS output Lock Detect (LOCKDET) signal inactive (Low), indicates that incoming data stream failed frequency test, dictated PLL, LCKREFN been asserted Low, SDLVCMOSN/SDLVPECL been asserted. This test used determine whether serial input activity valid data. When LOCKDET active, locked data stream. Recovered 622.08 Clock (RX622MCKP/N) LVDS 622.08 Clock equivalent rate) (RX622MCKP/N) clock which recovered from input data stream. During loss-of-signal conditions when LCKREFN been asserted, this output clock derived from Reference Clock Input (REFCLKP/N). This internally terminated with ground (GND).
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S3098 SONET/SDH/AOC-192 1:16 Power Receiver w/CDR/Postamp S3098 FUNCTIONAL DESCRIPTION
Receiver Description S3098 receiver chip provides first stage digital processing receive SONET OC-192 bitserial stream. converts bit-serial 9.953 Gbps data stream into 622.08 Mbps equivalent rate) 16-bit parallel data format. Postamp S3098 limiting postamp takes differential serial data from SERDATIP/N pins provides small signal gain. input postamp either coupled. Clock Recovery clock recovery circuitry generates clock that same frequency incoming data rate serial data input. clock phase aligned Phase Lock Loop (PLL) that samples data center data pattern. Clock Data Recovery (CDR) extracts synchronous signal from serial data input using PLL. consists Voltage Controlled Oscillator (VCO), Phase/Frequency Detectors (PFD), loop filter. frequency detector ensures predictable lock-up conditions. used during acquisition serves means pull into range data rate which phase detector capable acquiring lock. phase detector used designed give minimum static phase error PLL. When transition occurred, value sample vicinity transition tells whether clock leads lags incoming data, phase detector produces binary output accordingly. When loss-of-signal condition exists, Signal Detect (SDLVCMOSN SDLVPECLN) will de-asserted, locks onto Reference Clock (REFCLK) provide steady output clock. There pins (CAP1 CAP2) connect external capacitor resistors order adjust loop performance. phase relationship between edge transitions data those generated clock compared phase/frequency discriminator. Output pulses from discriminator indicate required direction phase corrections. These pulses
Revision 2001
DEVICE SPECIFICATION
smoothed integral loop filter. output loop filter controls frequency Voltage Control illator whic gener ates recovered clock. loop filter transfer function optimized enable track jitter, tolerate minimum transition density expected received SONET data signal. total loop dynamics clock recovery yield jitter tolerance that exceeds minimum tolerance proposed SONET equipment Telcordia TA-NWT-000253 standard. Lock Detect S3098 contains lock detect circuit, which monitors integrity serial data inputs. received serial data fails frequency test, will forced lock local reference clock. This will maintain correct frequency recovered clock output under loss-of-signal loss-of-lock conditions. recovered clock frequency deviates from local reference clock frequency more than typical value stated Table Performance Specifications, will declared lock. phase detect circuit will poll input data stream attempt reacquire lock data. recovered clock frequency determined within typical value stated Table Performance Specifications, will declared lock, lock detect output will active. de-asserted signal detect (SDLVCMOSN SDLVPECLN) will also cause out-of-lock condition. Serial-to-Parallel Converter serial-to-parallel converter consists three 16-bit registers. first serial-in, parallel-out shift register, which performs serial-to-parallel conversion. second 16-bit internal holding register, which transfers data from serial-to-parallel register byte boundaries. falling edge Parallel Output Clock (POCLK), data holding register transferred output holding register, which drives Parallel Output Data (POUTP/N[15:0]). Power Sequencing order avoid latch following power-up sequence required. Apply first, next -5.2 then positive supplies, +2.5 +3.3 These positive supplies brought simultaneously order.
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Table Input Description Assignment
Name SERDATIP SERDATIN REFCLKP REFCLKN CAP1 CAP2 LCKREFN Level Diff. Diff. LVPECL Analog
Revision 2001
DEVICE SPECIFICATION
Description Serial Data Input. Differential high frequency serial data input limiting postamp small signal gain. Internally biased terminated lineto-line. Reference Clock. Differential reference clock input 155.52 equivalent rate). will lock onto this reference absence serial input data. Internally biased terminated line-to-line. Loop Filter. external loop filter capacitor resistors connected these pins. Used adjust loop filter performance. Figure External Loop Filter Table External Loop Filter Components. Lock Reference. Active Low. When active, will forced lock local reference clock input (REFCLK). unused, connect VCC_2.5 through resistor normal operation. Master Reset. Active Low. Reset input device. correct reset, this input must asserted Connect VCC_2.5 through resistor used. Test Enable. Active Low. Used during production test bypass PLL. Connect VCC_2.5 through resistor normal operation. Test Input. Active Low. Signal used production test. Connect VCC_2.5 through resistor normal operation. Signal Detect. Single-Ended LVPECL input driven external optical receiver module indicate loss received optical power. This input utilized optics module that active active High loss light. active High device, SDLVCMOSN must connected VCC_2.5 through resistor. active optics module, SDLVCMOSN input must connected GND. optics module LVPECL signal detect output directly connected SDLVPECLN input. This input internally pulled Low. When loss light condition occurs, internal will forced lock REFCLK input signal. Signal Detect. LVCMOS input driven external optical receiver module indicate loss received optical power. This input utilized optics module that active active High loss light. active device, SDLVPECLN must connected GND. active High optics module, SDLVPECLN input must connected VCC_3.3 through resistor. optics module LVCMOS signal detect output directly connected SDLVCMOSN input. When loss light condition occurs, internal will forced lock REFCLK input signal.
LVCMOS
RSTB
LVCMOS
TESTB
LVCMOS
TSTSIG
LVCMOS
SDLVPECLN
SingleEnded LVPECL
SDLVCMOSN
LVCMOS
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Table Output Descriptions Assignment
Name POCLKP POCLKN Level LVDS
Revision 2001
DEVICE SPECIFICATION
Description Parallel Output Clock. Regenerated 622.08 equivalent rate) differential output clock, synchronized parallel output data. (See Figure Parallel Data Output Delay from POCLK). Internally terminated with GND. Parallel Output Data. Re-timed data from Demultiplexer (DeMUX) rate 622.08 Mbps equivalent rate). POUTP/N15 most significant (corresponding each word, first received.) POUTP/N0 least significant corresponding each word, last received). Internally terminated with GND.
POUT0P POUT0N POUT1P POUT1N POUT2P POUT2N POUT3P POUT3N POUT4P POUT4N POUT5P POUT5N POUT6P POUT6N POUT7P POUT7N POUT8P POUT8N POUT9P POUT9N POUT10P POUT10N POUT11P POUT11N POUT12P POUT12N POUT13P POUT13N POUT14P POUT14N POUT15P POUT15N LOCKDET
LVDS
LVCMOS
Lock Detect. Active High. Clock recovery indicator. Active when internal clock recovery locked onto incoming data stream. LOCKDET asynchronous output. 622.08 Clock equivalent rate) derived from clock. Internally terminated with GND.
RX622MCKP RX622MCKN
LVDS
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Table Common Descriptions Assignment
Name COREVCC LVDSVCC LVCMOSVCC CMLVEE SUBVEE ANALOG AVCC DIGITALVCC Level +2.5 +2.5 +2.5 -5.2 -5.2 +3.3 +3.3 C13, H13, B12, D13, J13, A10, A13, A14, B14, C10, C12, D14, E13, L14, M10, N10, P11, P12, P13, E10, F10, G10, H10, J10,
Revision 2001
DEVICE SPECIFICATION
Description Digital VCC_2.5 LVDS VCC_2.5 LVCMOS VCC_2.5 -5.2 Substrate -5.2 Analog VCC_3.3 Digital VCC_3.3 Analog/Digital Ground
THERMAL
Thermal Ground
Note: digital, analog, thermal grounds connected together package.
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Figure S3098 Pinout (Top View)
ANALOG AVCC +3.3V (FILTER)
Revision 2001
DEVICE SPECIFICATION
ANALOG AVCC +3.3V (VCO)
ANALOG
ANALOG
ANALOG
TSTSIG
RSTB
DIGITAL
SDLV PECLN
DIGITAL
RX622 MCKN
LOCKDET
DIGITAL
DIGITAL
REFCLKP
ANALOG
ANALOG
CAP1
ANALOG
ANALOG
DIGITAL
CORE +2.5V DIGITAL +3.3V (PD)
POCLKN
POCLKP
RX622 MCKP
-5.2V
SDLV CMOSN
DIGITAL
REFCLKN
ANALOG
ANALOG
CAP2
ANALOG
TESTB
LVCMOS +2.5V
LVDS +2.5V
DIGITAL
DIGITAL
CORE +2.5V -5.2V
LCKREFN
-5.2V
ANALOG
DIGITAL
ANALOG
-5.2V
THERMAL
THERMAL
THERMAL
THERMAL
THERMAL
DIGITAL
POUT15N
ANALOG
ANALOG
THERMAL
THERMAL
THERMAL
THERMAL
THERMAL
THERMAL
POUT14N
POUT15P
SERDATIP
THERMAL
THERMAL
THERMAL
THERMAL
THERMAL
THERMAL
POUT14P
POUT13N
ANALOG
ANALOG
THERMAL
THERMAL
THERMAL
THERMAL
THERMAL
THERMAL
LVDS +2.5V
POUT13P
SERDATIN
THERMAL
THERMAL
THERMAL
THERMAL
THERMAL
THERMAL
-5.2V
POUT12N
ANALOG
ANALOG
THERMAL
THERMAL
THERMAL
THERMAL THERMAL
THERMAL
POUT11N
POUT12P
ANALOG
-5.2V
PACKAGE VIEW
LVDS +2.5V DIGITAL DIGITAL LVDS +2.5V DIGITAL CORE +2.5V CORE +2.5V DIGITAL POUT8P POUT8N
POUT11P
DIGITAL
ANALOG
CORE +2.5V
LVDS +2.5V
POUT10N
DIGITAL
POUT0P
POUT0N
POUT2P
POUT2N
POUT4P
POUT4N
POUT6P
POUT6N
DIGITAL
-5.2V
POUT9P
POUT9N
POUT10P
DIGITAL
DIGITAL
POUT1P
POUT1N
POUT3P
POUT3N
POUT5P
POUT5N
POUT7P
POUT7N
DIGITAL
DIGITAL
DIGITAL
DIGITAL
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Figure Compact 148-pin CBGA Package
Revision 2001
DEVICE SPECIFICATION
Table Package Thermals
Package Power (85°C Ambient) (Assuming 125°C Junction Temp) 1.95
20.5°C/Watt
3.0°C/Watt
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Table Performance Specifications
Parameter Nominal Center Frequency 155.52 equivalent rate) Reference Clock Frequency Tolerance 155.52 equivalent rate) Reference Clock Input Duty Cycle 155.52 equivalent rate) Reference Clock Rise Fall Times SERDATIP/N Input Return Loss (S11) (when driven differentially) SERDATIP Input Return Loss (S11) (when driven single-ended using termination scheme Figure Acquisition Lock Time (RSTB deassertion LOCKDET assertion) Min. 9.953 -100 10.709 Units
Revision 2001
DEVICE SPECIFICATION
Conditions
required meet SONET output frequency specification.
0.080
amplitude.
Minimum transition density 50%. Guaranteed, tested. With device already powered valid REFCLK.
Frequency difference which goes out-of-lock (REFCLK compared divided down clock). Frequency difference which receive goes into lock (REFCLK compared divided down clock). Jtol Jitter Tolerance (SERDATIP/N)
±440
±600
±732
±220
±300
±366
15/(f 2400) 1.5/(f 103) 0.15
(p-p) (p-p) (p-p) (p-p) (p-p) bits
Hz-2.4 (Sinusoidal) kHz-24 (Sinusoidal) kHz-400 (Sinusoidal) kHz-4 (Sinusoidal) MHz-1 (Sinusoidal) Number bits with transitions. (SONET spec bits max.)
Lcid Consecutive identical digits Serial Data Input
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Table Absolute Maximum Ratings
Revision 2001
DEVICE SPECIFICATION
following absolute maximum stress ratings S3098 device. Stresses beyond those listed cause permanent damage device. Absolute maximum ratings stress ratings only, operation device maximums stated other conditions beyond those indicated "Recommended Operating Conditions" document inferred. Exposure absolute maximum rating conditions extended periods affect device reliability.
Parameter Storage Temperature VCC_2.5 Supply VCC_3.3 Supply -5.2 Supply LVCMOS Input Voltage LVPECL Input Voltage Input Voltage LVDS Output Current LVCMOS Output Current (source/sink) LVCMOS Input Current (source/sink) LVDS Input Current LVPECL Input Current Input Current
Min. -0.5 -0.5 -7.0 -0.5 -0.5 -0.25
-0.5 VCC_2.5 VCC_3.3 30/1000 200/65
Units
Electrostatic Discharge (ESD) Ratings S3098 rated following voltages based human body model JESD22-A114-B specification: pins rated
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Table Recommended Operating Conditions
Parameter Ambient Temperature Under Bias Junction Temperature Under Bias Voltage VCC_2.5 with Respect Voltage VCC_3.3 with Respect Voltage with Respect ICC_2.5 Supply Current IEE_CML Supply Current ICC_3.3 V_AVCC/VCC Supply Current Min. 2.375 3.135 -4.94 -5.2 2.625 3.465 -5.46 Units
Revision 2001
DEVICE SPECIFICATION
Conditions Over process, voltage temperature range. Over process, voltage temperature range. Over process, voltage temperature range. Over process, voltage temperature range. Over process, voltage temperature range. Outputs terminated. Outputs terminated. Outputs terminated. AVCC Outputs terminated. bandwidth
Power Dissipation Power Supply Noise Rejection
1.72
mVpp
Table Internally Biased Differential Input Characteristics
Parameter VIDIFF VISINGLE Description Input High Voltage Input Voltage Differential Input Voltage Swing Single-ended Input Voltage Swing (while driven differentially) Single-ended Input Voltage Swing (while driven singleended) Input Common Mode Voltage Differential Input Resistance Min. -1.195 -1.55 12.5 -0.305 1400 Units Conditions Over process, voltage temperature range. Over process, voltage temperature range. Figure Differential Voltage Measurement. Figure Differential Voltage Measurement. Figure Singleended Data Input Voltage Measurement. Over process, voltage temperature range. Over process, voltage temperature range. measurement.
VISINGLE
VICM RIDIFF
-1.2
-0.65
-0.3
Consult Single-Ended Termination Recommendation Application Note improvement input sensitivity.
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Table LVDS Output Characteristics
Parameter VODIFF Description Output High Voltage Output Voltage Output Differential Voltage Output Singleended Voltage Differential Output Impedance Min. 1.25 0.85 1.45 1100 Units
Revision 2001
DEVICE SPECIFICATION
Conditions Output loading line-to-line. Over process, voltage temperature range. Output loading line-to-line. Over process, voltage temperature range. Output loading line-to-line. Over process, voltage temperature range. Figure Differential Voltage Measurement Output loading line-to-line. Over process, voltage temperature range. Figure Differential Voltage Measurement. Over process, voltage temperature range. Guaranteed design.
VOSINGLE
RODIFF
Table Internally Biased Differential LVPECL Input Characteristics (REFCLKP/N)
Parameter VIDIFF Description Input High Voltage Min. VCC_3.3 -1.20 VCC_3.3 -2.00 VCC_3.3 -0.50 VCC_3.3 -1.40 1200 Units Conditions Over process, voltage temperature range. Over process, voltage temperature range. Over process, voltage temperature range. Figure Differential Voltage Measurement Over process, voltage temperature range. Figure Differential Voltage Measurement Over process, voltage temperature range. Over process, voltage temperature range.
Input Voltage
Differential Input Voltage Swing Single-ended Input Voltage Swing Input Common Mode Voltage Differential Input Impedance
VISINGLE
VICM RIDIFF
VCC_3.3 -1.60
VCC_3.3 -0.95
Table Single-Ended LVPECL Input Characteristics (SDLVPECLN)
Parameter Description Input High Voltage Min. VCC_3.3 -1.20 VCC_3.3 -2.00 VCC_3.3 -0.50 VCC_3.3 -1.40 Units Conditions Over process, voltage temperature range. Over process, voltage temperature range. Over process, voltage temperature range. VCC_3.3 Over process, voltage temperature range. VCC_3.3
Input Voltage
Input High Current
Input Current
-100
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Table LVCMOS Input Characteristics
Parameter Description Input High Voltage Input Voltage Input High Current Input Current Min. VCC_2.5 Units
Revision 2001
DEVICE SPECIFICATION
Conditions Over process, voltage temperature range. Over process, voltage temperature range.
Table LVCMOS Output Characteristics
Parameter Description Output High Voltage Min. VCC_2.5 Units Conditions Over process, voltage temperature range. Over process, voltage temperature range.
Output Voltage
Table Characteristics
Parameter CDUTY Description POCLKP/N RX622MCKP/N Duty Cycle POUTP/N Delay from POCLKP/N Min. Units Conditions Output loading line-to-line. Over process, voltage temperature range. Over process, voltage temperature range. Figure Parallel Data Output Delay from POCLK Over process, voltage temperature range. Figure Parallel Data Output Delay from POCLK Over process, voltage temperature range. Figure Parallel Data Output Delay from POCLK Over process, voltage temperature range. 80%. Over process, voltage temperature range. 80%. Over process, voltage temperature range. 80%. Guaranteed design. Guaranteed design.
POCLKP/N POUTP/N
POCLKP/N POUTP/N
tr/f
LVPECL Input rise fall time LVDS Output rise fall time LVCMOS Output rise fall time load load
RSTB Minimum Pulse Width
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Table External Loop Filter Components (See Figure External Loop Filter)
Symbol Resistor, Surface Mount, 0402 Capacitor, Surface Mount, Non-polarized, 0603 larger Description
Revision 2001
DEVICE SPECIFICATION
Value
Unit
Figure Parallel Data Output Delay from POCLK1,2
10.709 Gbps POCLKP (669.3125 MHz) 45/55 Duty Cycle 672.3
POUTP
POCLK duty cycle variation 74.7 Specification(S3098 meets exceeds) POUT receiving side setup/hold time compliance
When setup time specified LVDS signals between input clock, setup time picoseconds, from point input point clock. When hold time specified LVDS signals between input clock, hold time picoseconds, from point clock point input.
Figure Differential Voltage Measurement
V(+) Common Mode Voltage
VISINGLE V(-)
V(+) V(-) IDIFF VISINGLE
Note: with respect
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Figure Single-Ended Data Input Voltage Measurement
Revision 2001
DEVICE SPECIFICATION
V(+)
VISINGLE
Figure S3098 LVDS Output LVDS Input
+2.5 S3098 LVDS Output
+2.5 +3.3
LVDS Input
Figure -5.2 Post S3098 Input Coupled Termination
BIAS
-5.2
BIAS
-5.2
S3196 POST AMPLIFIER
S3098 SERDATIP/N
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S3098 SONET/SDH/AOC-192 1:16 Power Receiver w/CDR/Postamp
Figure -5.2 S3098 Coupled Termination
Revision 2001
DEVICE SPECIFICATION
BIAS
BIAS
-5.2 S3090 Transimpendance Amplifier
-5.2
S3098 SERDATIP/N
Figure +3.3 Differential LVPECL Driver S3098 LVPECL Reference Clock Input, Coupled Termination
+3.3 0.01 LVPECL REFCLK Output 0.01
Zo=50
BIAS
+3.3
Zo=50
BIAS
S3098 REFCLKP/N Input
Figure External Loop Filter (See Table External Loop Filter Components)
CAP1
CAP2
AMCC Confidential Proprietary
S3098 SONET/SDH/AOC-192 1:16 Power Receiver w/CDR/Postamp
Revision 2001
DEVICE SPECIFICATION
Figure Single-Ended Termination Scheme (Termination Scheme that characterized)1
0.01
BIAS BIAS
-5.2
0.01
-5.2
S3098 SERDATIP/N
S3098 Single-Ended Termination Recommendation Application Note more details improvement input sensitivity.
AMCC Confidential Proprietary
S3098 SONET/SDH/AOC-192 1:16 Power Receiver w/CDR/Postamp
Ordering Information
Prefix Integated Circuit Device 3098 Package
CBGA
Revision 2001
DEVICE SPECIFICATION
Revision
Prefix
XXXX
Device
Package
Revision
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S3098 power operation Silicon Germanium BiCMOS technology Complie

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