DesignObjects Purpose Master Interface Master Interface IIC_

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DesignObjects Purpose Master Interface Master Interface IIC_

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Master Interface
DesignObjects
Purpose Master Interface
Master Interface IIC_M provides interface between host bus. external components controlled host over Master Interface. Basically, Master Interface parallel serial serial parallel converter. parallel data received from host converted suitable serial form external components bus. Also serial data received from converted suitable parallel form host CPU. Master Interface also takes care interface timing, data structure error handling.
Support fast-mode System clock Reading writing data bursts Special mode read write access slave device internal register address Wait state generation supported Spike filtering
Master Interface
Master Interface supports four operating modes:
Direct Write, writing data burst Direct Read, reading data burst Random Access Write, writing data byte specified address Random Access Read, reading data byte from specified address
Some bits also used reference frequency clock signal generation programming spike filter.
Data Register
readable data register contains data received from Random Access Read mode Direct Read mode. This register contains also error bit, interrupt write_allowed bit. error generated (set `1') data transfer failed. interrupt `1', register includes data which read host CPU. After data been read, interrupt reset `0'. When interrupt signal disabled (irq configuration register `0'), interrupt information request from host polling. interrupt data register generated without respect configuration register. IICCLK signal stalled device that data transmitted bus. proceeding write access been completed, next write access will acknowledged. prevent this, readable data register provides write_allowed bit. This write_allowed `0', data register ready write access. host might read write_allowed register before write access.
DesignObjects
Master Interface supports both data transfer modes with data transfer rates kbit/s standard-mode kbit/s fast-mode.
Interface Host
Master Interface includes three register elements communication between host bus. They addressed with signal HIF_adr[1:0]:
Writeable data register, HIF_adr[1:0]: HIF_adr[1:0]: Writeable configuration register, HIF_adr[1:0]: Readable data register, HIF_adr[1:0]:
DATA Register
writeable data register divided into registers conform data host CPU. These separate parts register called data_reg_high[15:0] data_reg_low[15:0]. beginning read/write access this register loaded with information from host needed data transfer bus. This information consists device code, address, data read write mode. bits used. device number doesn't change, only lower part data register loaded start data transfer. Data transfer begins always, when data_reg_low[15:0] been loaded.
Gate Count Requirements
Master Interface Gate Count Estimation: about 2,000 Gates. required.
Related Patents
trademark Philips, Inc. Purchase Philips components conveys license under Philips patent components system, provided system conforms specifications defined Philips. licensing information please contact Philips Corporate Intellectual Property department.
Configuration Register
writeable configuration register needed some special configuration information, which changed host CPU. Interrupt masking example that kind configuration.
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DesignObjects Purpose Master Interface Master Interface IIC_

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