Mbit (128K Parallel EEPROM With Software Data Protection Fast Acc

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Mbit (128K Parallel EEPROM With Software Data Protection Fast Acc

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M28010
Mbit (128K Parallel EEPROM With Software Data Protection
Fast Access Time: Single Supply Voltage: M28010 M28010-W M28010-R
Power Consumption Fast BYTE PAGE WRITE Bytes) Enhanced Write Detection Monitoring: Data Polling Toggle Page Load Timer Status
PDIP32 (BA)
JEDEC Approved Bytewide Pin-Out Software Data Protection Hardware Data Protection Software Chip Erase 100000 Erase/Write Cycles (minimum) Data Retention (minimum): Years
PLCC32 (KA) TSOP32 (NA)
DESCRIPTION M28010 devices consist 128Kx8 bits power, parallel EEPROM, fabricated with STMicroelectronics' proprietary double polysilicon CMOS technology. devices offer fast access time, with power dissipation, require single voltage supply (5V, depending option chosen). Table Signal Names
A0-A16 DQ0-DQ7 Address Input Data Input Output Write Enable
Figure Logic Diagram
A0-A16
DQ0-DQ7
M28010
Chip Enable Output Enable Supply Voltage Ground
AI02221
January 1999
This preliminary information product development undergoing evaluation. Details subject change without notice.
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M28010
Figure Connections
M28010
AI02222
Figure TSOP Connections
M28010
AI02224
Note:
Note:
Figure PLCC Connections
M28010
data retention. organization data byte (32-bit) "word" format leads significant savings power consumption. Once byte been read, subsequent byte read cycles from same "word" (with addresses differing only least significant bits) fetched from previously loaded Read Buffer, from memory array. result, power consumption these subsequent read cycles much lower than power consumption first cycle. careful design memory access patterns, reduction power consumption possible. SIGNAL DESCRIPTION external connections device summarized Table their Table Addresses (A0-A16). address inputs used select byte from memory array during read write operation. Data In/Out (DQ0-DQ7). contents data byte written read from, memory array through Data pins. Chip Enable (E). chip enable input must held enable read write operations. When Chip Enable high, power consumption reduced. Output Enable (G). Output Enable input controls data output buffers, used initiate read operations. Write Enable (W). Write Enable input controls whether addressed location read, from written
AI02223
Note:
device been designed offer flexible microcontroller interface, featuring both hardware software hand-shaking, with Data Polling Toggle Bit. device supports byte Page Write operation. Software Data Protection (SDP) also supported, using standard JEDEC algorithm. M28010 designed applications requiring much 100,000 write cycles years
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M28010
Table Absolute Maximum Ratings
Symbol VESD Parameter Ambient Operating Temperature Storage Temperature Supply Voltage Input Output Voltage (except Input Voltage Electrostatic Discharge Voltage (Human Body model) Value -0.3 VCCMAX+1 -0.3 CC+0.6 -0.3 2000 Unit
Note: Except rating "Operating Temperature Range", stresses above those listed Table "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, operation device these other conditions above those indicated Operating sections this specification implied. Exposure Absolute Maximum Rating conditions extended periods affect device reliability. Refer also SURE Program other relevant quality documents. MIL-STD-883C, 3015.7 (100 1500
Figure Block Diagram
A7-A16 (Page Address)
ADDRESS LATCH
DECODE
1Mbit ARRAY
A0-A6
ADDRESS LATCH
LATCH PAGE DECODE
REFERENCES
VREAD
SENSE PAGE DATA LATCH
CONTROL LOGIC
PROGRAMMING STATE MACHINE
MULTIPLEXER
BUFFERS
DQ0-DQ7
AI02225
3/22
M28010
Table Operating Modes
Mode Read Write Stand-by Write Inhibit Write Inhibit Write Inhibit Output Disable
Note: VIL.
DQ0-DQ7 Data Data Hi-Z Data Hi-Z Data Hi-Z Hi-Z
DEVICE OPERATION order prevent data corruption inadvertent write operations, internal comparator inhibits Write operations voltage lower than (see Table Table 4C). Once voltage applied goes over threshold (VCC>VWI), write access memory allowed after time-out tPUW, specified Table Table
Further protection against data corruption offered pass filters: glitch, inputs, with pulse width less than (typical) internally filtered prevent inadvertent write operations memory. Read device accessed like static RAM. When low, high, contents addressed location presented pins.
Table Power-Up Timing1 M28010 range)
Symbol tPUR tPUW Parameter Time Delay Read Operation Time Delay Write Operation (once VWI) Write Inhibit Threshold Min. Max. Unit
Note: Sampled only, 100% tested.
Table Power-Up Timing1 M28010-W range)
Symbol tPUR tPUW Parameter Time Delay Read Operation Time Delay Write Operation (once VWI) Write Inhibit Threshold Min. Max. Unit
Note: Sampled only, 100% tested.
Table Power-Up Timing1 M28010-R range)
Symbol tPUR tPUW Parameter Time Delay Read Operation Time Delay Write Operation (once VWI) Write Inhibit Threshold Min. Max. Unit
Note: Sampled only, 100% tested.
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M28010
Otherwise, when either high, pins revert their high impedance state. Write Write operations initiated when both high. device supports both W-controlled E-controlled write cycles shown Figure Figure 13). address latched during falling edge (which ever occurs later) data latched rising edge (which ever occurs first). After delay, tWLQ5H, that cannot shorter than value specified Table Table internal write cycle starts. continues, under internal timing control, until write operation complete. commencement this period detected reading Page Load Timer Status DQ5. internal write cycle detected reading status Data Polling Toggle functions DQ6.
Figure Software Data Protection Enable Algorithms (with without Memory Write)
Disabled Application needs Enable Write Data Disabled Application needs Enable
Write Address 5555h Page Write Timing
Write Address 5555h
Write Address 2AAAh Page Write Timing
Write Address 2AAAh
Write Address 5555h
Write Address 5555h Write enabled
Time (tWLQ5H) Write data addresses within page
Wait write completion (tQ5HQ5X) Write Address 5555h
Time (tWLQ5H)
Wait write completion (tQ5HQ5X) DATA been written Enabled
Write Address 2AAAh Page Write Timing
Write Address 5555h Write enabled Write data addresses within page
Time (tWLQ5H)
Wait write completion (tQ5HQ5X) DATA been written Enabled
AI02227B
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M28010
Figure Software Data Protection Disable Algorithms (with without Memory Write)
Enabled Application needs Disable Enabled Application needs Write Data
Write Address 5555h
Write Address 5555h
Write Address 2AAAh
Write Address 2AAAh
Page Write Timing
Write Address 5555h
Page Write Timing
Write Address 5555h
Write Address 5555h
Write Address 5555h
Write Address 2AAAh
Write Address 2AAAh
Write Address 5555h
Write Address 5555h
Time (tWLQ5H)
Physical Write Instructions
Write data addresses within page
Wait write completion (tQ5HQ5X) Disabled Time (tWLQ5H)
Wait write completion (tQ5HQ5X) DATA been written Disabled
AI02226B
Page Write Page Write mode allows bytes written single page single This achieved through series successive Write operations, which separated more than tWLQ5H value specified Table Table 9C). page write initiated during byte write operation. Following first Byte Write instruction, host send another address data with minimum data transfer rate WLQ5H. internal write cycle start instant after tWLQ5H. Once initiated, write operation internally timed, continues, uninterrupted, until completion.
bytes must located same page address (A16-A7 must same bytes). Otherwise, Page Write operation executed. Page Write Abort event indicated application described page with single byte Write operation, described above, DQ5, lines used detect beginning internally controlled phase Page Write cycle. Software Data Protection (SDP) device offers software-controlled write-protection mechanism that allows user inhibit write operations device, including chip erase. This useful protecting memory from inadvertent write cycles that occur during periods instability (uncontrolled conditions when excessive noise detected, when
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M28010
Figure Software Chip Erase Algorithm
Write Address 5555h
Figure Status Assignment
PLTS
Write Address 2AAAh
Page Write Timing
Write Address 5555h
PLTS
Data Polling Toggle Page Load Timer Status undefined Page Write Abort Software Data Protection
AI02486B
Write Address 5555h
Write Address 2AAAh
Figure Software Data Protection Status Read Algorithm
Write Address 5555h
Write Address 5555h Page Write Timing
Time (tWLQ5H)
Write Address 2AAAh
Wait write completion (tQ5HQ5X) Whole Array been Write Address 5555h
AI02236C
Read
power supply levels outside their specified values). default, device shipped "unprotected" state: memory contents freely changed user. Once Software Data Protection Mode enabled, write commands ignored, have effect memory contents. device remains this mode until valid Software Data Protection disable sequence received. device reverts "unprotected" state. status Software Data Protection (enabled disabled) represented non-volatile latch, remembered across periods power being off. Software Data Protection Enable command consists writing three specific data bytes three specific memory locations (each location being different page), shown Figure Similarly, disable Software Data Protection, user write specific data bytes into different locations, shown Figure This complex series operations protects against
Write Address xxxxh
Normal User Mode
AI02237B
chance inadvertent enabling disabling Software Data Protection mechanism. When enabled, memory array still have data written sequence more complex (and hence better protected from inadvertent use). sequence shown Figure This consists unlock key, enable write action, which continues enabled. This allows enabled, data written, within single Write cycle (tWC). Software Chip Erase device erased (with bytes FFh) using six-byte software command code. This operation initiated only user loads, with Page Write addressing mode,
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M28010
specific data bytes specific locations shown Figure complexity sequence been designed guard against inadvertent command. Status Bits devices provide five status bits (DQ7, DQ6, DQ5, DQ0) during write operations. These allow application write time latency device getting with other work. These signals available port bits DQ7, DQ6, DQ5, (but only during internal write cycle, tQ5HQ5X). Data Polling (DQ7). internally timed write cycle starts soon tWLQ5H (defined Table Table elapsed since previous byte latched memory. value this last byte, used signal throughout this write operation: inverted while internal write operation underway, inverted back original value once operation complete. Toggle (DQ6). device offers another determining when internal write cycle running. During internal write cycle, toggles from (the first read value being '0') subsequent attempts read byte memory. When internal write cycle complete, toggling stopped, values read DQ7-DQ0 those addressed memory byte. This indicates that device again available Read Write operations. Page Load Timer Status (DQ5). internal timer used measure period between successive Write operations, tWLQ5H (defined Table Table 9C). line held show when this timer running (hence showing that device received write operation, waiting next). line held high when counter overflowed (hence showing that device starting internal write memory array). Page Write Abort (DQ1). During page write operation, signals should kept constant. They should change while successive data bytes being transferred internal latches memory device. change occurs pins, during page write operation (that before falling edge which ever occurs later), internal write cycle started, internal circuitry completely reset. abort signal observed pin, using normal read operation. This performed time during byte load cycle, tWLQ5H, while input being held high between load cycles. default value initially changes internal circuitry detected change address pins This checked regardless whether Software Data Protection enabled disabled. Software Data Protection (DQ0). Reading (DQ0) allows user determine whether Software Data Protection mode been enabled (SDP=1) disabled (SDP=0). (DQ0) read using dedicated algorithm shown Figure combined
Table Read Mode Characteristics M28010 range)
Symbol Parameter Input Leakage Current Output Leakage Current Test Condition VOUT VIL, VIL, Supply Current (CMOS inputs) VIL, VIL, VIL, ICC1 Supply Current (Stand-by) CMOS Input Voltage Input High Voltage Output Voltage Output High Voltage -400 -0.3 Min. Max. Unit
Note: inputs outputs open circuit.
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M28010
Table Read Mode Characteristics M28010-W range)
Symbol Parameter Input Leakage Current Output Leakage Current Test Condition VOUT VIL, VIL, Supply Current (CMOS inputs) VIL, VIL, VIL, ICC1 Supply Current (Stand-by) CMOS Input Voltage Input High Voltage Output Voltage Output High Voltage -100 -0.3 Min. Max. 0.45 Unit
Note: inputs outputs open circuit.
Table Read Mode Characteristics M28010-R range)
Symbol ICC1 Parameter Input Leakage Current Output Leakage Current Supply Current (CMOS inputs) VIL, VIL, MHz, Supply Current (Stand-by) CMOS Input Voltage Input High Voltage Output Voltage Output High Voltage -100 0.15 0.15 Test Conditio VOUT VIL, MHz, Min. Max. Unit
Note: inputs outputs open circuit.
with reading (DQ7), (DQ6) PLTS (DQ5).
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M28010
Table Input Output Parameters1 MHz)
Symbol Parameter Input Capacitance Output Capacitance Test Condition VOUT Min. Max. Unit
Note: Sampled only, 100% tested.
Table Measurement Conditions
Input Rise Fall Times Input Pulse Voltages Input Output Timing Ref. Voltages VCC/2
Figure Testing Equivalent Load Circuit
Figure Testing Input Output Waveforms
DEVICE UNDER TEST
VCC/2
AI02228
30pF
includes capacitance
AI02578
Table Read Mode Characteristics M28010 range)
Symbol Alt. Parameter Test Condi VIL, VIL, M28010 Unit
tAVQV tELQV tGLQV tEHQZ1 tGHQZ1 tAXQX
tACC
Address Valid Output Valid Chip Enable Output Valid Output Enable Output Valid Chip Enable High Output Hi-Z Output Enable High Output Hi-Z Address Transition Output Transition
Note: Output Hi-Z defined point which data longer driven.
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M28010
Table Read Mode Characteristics M28010-W range)
Symbol Alt. Parameter Test Condi VIL, VIL, M28010-W Unit
tAVQV tELQV tGLQV tEHQZ1 tGHQZ1 tAXQX
tACC
Address Valid Output Valid Chip Enable Output Valid Output Enable Output Valid Chip Enable High Output Hi-Z Output Enable High Output Hi-Z Address Transition Output Transition
Note: Output Hi-Z defined point which data longer driven.
Table Read Mode Characteristics M28010-R range)
Symbol Alt. Parameter Test Condi VIL, VIL, M28010-R Unit
tAVQV tELQV tGLQV tEHQZ1 tGHQZ1 tAXQX
tACC
Address Valid Output Valid Chip Enable Output Valid Output Enable Output Valid Chip Enable High Output Hi-Z Output Enable High Output Hi-Z Address Transition Output Transition
Note: Output Hi-Z defined point which data longer driven.
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M28010
Figure Read Mode Waveforms (with Write Enable, high)
A0-A16 tAVQV tGLQV tELQV DQ0-DQ7
VALID tAXQX
tEHQZ
tGHQZ DATA Hi-Z
AI02229
Note: Write Enable
Table Write Mode Characteristics M28010 range)
M28010 Symbol tAVWL tAVEL tELWL tGHWL tGHEL tWLEL tWLAX tELAX tELEH tWHEH tWHGL tEHWH tWHDX tEHDX tWHWL tWLWH tWLQ5H tQ5HQ5X tDVWH tDVEH Alt. tCES tOES tOES tWES tCEH tOEH tWEH tWPH tBLC Parameter Address Valid Write Enable Address Valid Chip Enable Chip Enable Write Enable Output Enable High Write Enable Output Enable High Chip Enable Write Enable Chip Enable Write Enable Address Transition Chip Enable Address Transition Chip Enable Chip Enable High Write Enable High Chip Enable High Write Enable High Output Enable Chip Enable High Write Enable High Write Enable High Input Transition Chip Enable High Input Transition Write Enable High Write Enable Write Enable Write Enable High Time-out after last byte write Byte Write Cycle time Page Write Cycle time bytes) Data Valid before Write Enable High Data Valid before Chip Enable High Test Condit VIL, VIH, Unit
12/22
M28010
Table Write Mode Characteristics M28010-W range)
M28010-W Symbol tAVWL tAVEL tELWL tGHWL tGHEL tWLEL tWLAX tELAX tELEH tWHEH tWHGL tEHWH tWHDX tEHDX tWHWL tWLWH tWLQ5H tQ5HQ5X tDVWH tDVEH Alt. tCES tOES tOES tWES tCEH tOEH tWEH tWPH tBLC Parameter Address Valid Write Enable Address Valid Chip Enable Chip Enable Write Enable Output Enable High Write Enable Output Enable High Chip Enable Write Enable Chip Enable Write Enable Address Transition Chip Enable Address Transition Chip Enable Chip Enable High Write Enable High Chip Enable High Write Enable High Output Enable Chip Enable High Write Enable High Write Enable High Input Transition Chip Enable High Input Transition Write Enable High Write Enable Write Enable Write Enable High Time-out after last byte write Byte Write Cycle time Page Write Cycle time bytes) Data Valid before Write Enable High Data Valid before Chip Enable High Test Condit VIL, VIH, Unit
13/22
M28010
Table Write Mode Characteristics M28010-R range)
M28010-R Symbol tAVWL tAVEL tELWL tGHWL tGHEL tWLEL tWLAX tELAX tELEH tWHEH tWHGL tEHWH tWHDX tEHDX tWHWL tWLWH tWLQ5H tWHRH tDVWH tDVEH Alt. tCES tOES tOES tWES tCEH tOEH tWEH tWPH tBLC Parameter Address Valid Write Enable Address Valid Chip Enable Chip Enable Write Enable Output Enable High Write Enable Output Enable High Chip Enable Write Enable Chip Enable Write Enable Address Transition Chip Enable Address Transition Chip Enable Chip Enable High Write Enable High Chip Enable High Write Enable High Output Enable Chip Enable High Write Enable High Write Enable High Input Transition Chip Enable High Input Transition Write Enable High Write Enable Write Enable Write Enable High Time-out after last byte write Byte Write Cycle time Page Write Cycle time bytes) Data Valid before Write Enable High Data Valid before Chip Enable High Test Condit VIL, VIH, Unit
14/22
M28010
Figure Write Mode Waveforms (Write Enable, controlled)
A0-A16 tAVWL tELWL tGHWL
VALID tWLAX
tWHEH
tWLWH
tWHGL
tWHWL DQ0-DQ7 DATA tDVWH tWHDX
AI02230
Figure Write Mode Waveforms (Chip Enable, controlled)
A0-A16 tAVEL tGHEL tWLEL tEHWH DQ0-DQ7 DATA tDVEH tEHDX
AI02231
VALID tELAX
tELEH
tEHGL
15/22
M28010
Figure Page Write Mode Waveforms (Write Enable, controlled)
A0-A12 Addr Addr Addr Addr
tWHWL tWLWH DQ0-DQ7 (in) Byte Byte Byte Byte
(out) tWLQ5H tQ5HQ5X
AI02829
Figure Software Protected Write Cycle Waveforms
A0-A6 5555h A7-A16 2AAAh 5555h Page Byte Byte
tWHWL tWLWH DQ0-DQ7 tDVWH tWHDX Byte Byte
AI02233B
Note: must specify same page address during each high-to-low transition must high only when both low.
16/22
M28010
Figure Data Polling Sequence Waveforms
A0-A16 Address last byte Page Write instruction
tWHGL
LAST BYTE LOADED
INTERNAL WRITE SEQUENCE TIME BETWEEN CONSECUTIVE BYTES LOADING
READY AFTER INTERNAL WRITE SEQUENCE
AI02234
Figure Toggle Sequence Waveforms
A0-A16 Address last byte Page Write instruction
LAST BYTE LOADED
TOGGLE INTERNAL WRITE SEQUENCE TIME BETWEEN CONSECUTIVE BYTES LOADING
READY AFTER INTERNAL WRITE SEQUENCE
AI02235
Note: Toggle first `0'.
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M28010
Table Ordering Information Scheme
Example: M28010
Option Tape Reel Packing
Speed Temperature Range
Operating Voltage blank
Package PDIP32 PLCC32 TSOP32: 20mm
Note: This temperature range request only.
ORDERING INFORMATION Devices shipped from factory with memory content `1's (FFh). notation used device number shown Table list available options (speed, package, etc.) further information aspect this device, please contact Sales Office nearest you.
18/22
M28010
Table PDIP32 lead Plastic DIP, mils width, Package Mechanical Data
Symbol 2.54 15.24 38.10 15.24 1.52 Typ. Min. 0.38 3.56 0.38 0.20 41.78 13.59 15.24 3.18 1.78 Max. 5.08 4.06 0.51 0.30 42.04 13.84 17.78 3.43 2.03 0.100 0.600 1.500 0.600 0.060 Typ. inches Min. 0.015 0.140 0.015 0.008 1.645 0.535 0.600 0.125 0.070 Max. 0.200 0.160 0.020 0.012 1.655 0.545 0.700 0.135 0.080
Figure PDIP32 (BA)
PDIP
Note: Drawing scale.
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M28010
Table PLCC32 lead Plastic Leaded Chip Carrier, rectangular
Symbol 0.89 1.27 Typ. Min. 2.54 1.52 0.33 0.66 12.32 11.35 9.91 14.86 13.89 12.45 0.00 0.10 Max. 3.56 2.41 0.38 0.53 0.81 12.57 11.56 10.92 15.11 14.10 13.46 0.25 0.035 0.050 Typ. inches Min. 0.100 0.060 0.013 0.026 0.485 0.447 0.390 0.585 0.547 0.490 0.000 0.004 Max. 0.140 0.095 0.015 0.021 0.032 0.495 0.455 0.430 0.595 0.555 0.530 0.010
Figure PLCC32 (KA)
0.51 (.020)
D2/E2
1.14 (.045)
PLCC
Note: Drawing scale.
20/22
M28010
Table TSOP32 lead Plastic Thin Small Outline, 20mm, Package Mechanical Data
Symbol Typ. 0.50 0.05 0.95 0.15 0.10 19.80 18.30 7.90 0.50 0.10 Min. Max. 1.20 0.17 1.05 0.27 0.21 20.20 18.50 8.10 0.70 0.020 0.002 0.037 0.006 0.004 0.780 0.720 0.311 0.020 0.004 Typ. Min. Max. 0.047 0.006 0.041 0.011 0.008 0.795 0.728 0.319 0.028 inches
Figure TSOP32 (NS)
TSOP-a
Note: Drawing scale.
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M28010
Information furnished believed accurate reliable. However, STMicroelectronics assumes responsibility consequences such information infringement patents other rights third parties which result from use. license granted implication otherwise under patent patent rights STMicroelectronics. Specifications mentioned this publication subject change without notice. This publication supersedes replaces information previously supplied. STMicroelectronics products authorized critical components life support devices systems without express writt approval STMicroelectronics. 1999 STMicroelectronics Rights Reserved logo registered trademark STMicroelectronics. other names property their respective owners. STMicroelectronics GROUP COMPANIES Australia Brazil China France Germany Italy Japan Korea Malaysia Malta Mexico Morocco Netherlands Singapore Spain Sweden Switzerland Taiwan Thailand United Kingdom U.S.A. http:// www.st.com
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Mbit (128K Parallel EEPROM With Software Data Protection Fast Acc

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