AK2048D Transceiver FEATURES 2.048Mbps Interface CLOCK DATA

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AK2048D Transceiver FEATURES 2.048Mbps Interface CLOCK DATA

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[AK2048]
AK2048D
Transceiver
FEATURES 2.048Mbps Interface CLOCK DATA Recovery function Loss Lock Detection Loss Signal Detection Transmitter Pulse Shape Single 5.0V±5% Operation Power Consumption: 400mW (TYP) Package: 44pin BLOCK DIAGRAM
TDATA
DRIVER
ENCODER
TCLK TCRV
CLOCK RECOVER
DECODER
RDATA RCRV RCLK
RESET
VREF
CALIB
LOCK
LOCK
REF25
RVDD
RVSS
TVDD
TVSS
Transceiver Block Diagram
MS0073-E-02
2002/05
[AK2048]
GENERAL DESCRIPTIONS AK2048D 2.048Mbps interface CMOS interface card. includes Clock Data Recovery, Line Driver, Detector, etc. Build clock recovery circuit eliminates correlation frequency deviation uneven quality devices secular change.
ASSIGNMENTS
44pin
RVDD
RVSS
RDATA RCLK RCVR TDATA TCLK TCRV
REF25 TVDD TVSS
(TOP VIEW)
TEST1
TEST2
LOCK
MS0073-E-02
2002/05
[AK2048]
ASSIGNMENTS
Name RDATA RCLK RCRV TDATA TCLK TCRV TEST1 TEST2 LOCK TVSS TVDD REF25 RVDD
Type
Load (MAX) 15pF 15pF 15pF
Load (MIN)
Comment
Analog 15pF 15pF 15pF
Analog Analog Analog Analog
15pF 1µF(typ)
Pulled internal register (50Kmin)
RVSS
other pins pins. pins recommended connect avoid noise problem. TXA, drive connected between these pins. Must open.
MS0073-E-02
2002/05
[AK2048]
DESCRIPTIONS
Name RDATA RCLK RCRV
Function
Receive Data output recovered from incoming data. Delay time from incoming data RDATA about 1.25bit. Output rising edge RCLK. Receive Clock Output recovered from incoming data. (Code Rule Violation) output pin. When AK2048D detects codes from coming data, RCRV goes "high" synchronized with violation data. detected both data data. Refer Fig.6,
TDATA TCLK TCRV
Transmit Data Input pin. Input falling edge TCLK. Transmit Clock Input pin. this input "high", AK2048D generates transmit data. generated both "0"data "1"data. "High" input TCRV accepted until clocks duration. duration "High" input longer than clocks, TCRV input after clock ignored. Refer Fig.4,
TEST1 TEST2 LOCK
Test pin. Should floated. Test pin. Should floated. LOCK indicates status whether LOCK status UNLOCK status. LOCK status LOCK becomes "Low" when sampled RCLK "Low" during consecutive RXA-RXB sample clock duration. LOCK status LOCK becomes "High" when following both conditions satisfied.
sampled RCLK "High" more than clocks frame consecutive
RXA-RXB clock duration.
above happens consecutive frames.
another condition, LOCK keeps current output status without change. output timing this signal asynchronous with RCLK. When "Low", LOCK fixed "High".
MS0073-E-02
2002/05
[AK2048]
Name TVSS TVDD REF25 RVDD
Function
goes High within 12usec after AK2048D detects that amplitude input signal lower than 135mVpp(typ). Output rising edge RCLK. Transmit signal output. CMI+, corresponds CMI-. Delay time from TDATA about 1bit. Negative power supply Positive power supply Transmit signal output. CMI+, corresponds CMI-. Delay time from TDATA about 1bit. Receive signal input. CMI+, corresponds CMI-. Output reference voltage (about 2.5V) order decide middle point input signal (RXA-RXB). Connected middle point external equalizer. Receive signal input. CMI+, corresponds CMI-. Positive power supply. "Low" input reset calibration circuit forces LOCK output "High" TXA-TXB output "High-Z". When this input rise, calibration restarts. Please open connect when using.
RVSS
Negative power supply
MS0073-E-02
2002/05
[AK2048]
ABSOLUTE MAXIMUM RATINGS Parameter Supply Input Voltage Input Current Input Current (TXA, TXB, RXA, RXB) Storage Temperature Tstg Symbol DVDD TVDD RVSS-0.3 RVDD+0.3 -0.3 Units Conditions
Except TXA, TXB, RXA,
RECOMMENDED OPERATING CONDITIONS
Parameter Supply Ambient Operating Temperature Power Consumption PD1(RVDD) PD2(TVDD) LOAD Symbol RVDD TVDD 4.75 5.25 Unit Conditions TVDD<RVDD+0.3V
ELECTRICAL CHARACTERISTICS CHARACTERISTICS
Condition: VDD=5.0V±5%, VSS=0V,Ta=0~80°C Parameter Digital High-level input voltage Digital Low-level input voltage Digital High-Level output voltage Digital Low-level output voltage Input leak current Input leak current When CMOS load connected, output CMOS logic level. Symbol Unit IOUT=-40µA IOUT=1.6mA Without RST, TEST1 RST, TEST1 Conditions
MS0073-E-02
2002/05
ASAHI KASEI TRANSMITTER
Parameter Symbol Output signal level VpeakH VpeakL Rise/Fall Time Pulse duty transmit output 2.55 2.55 3.90 4.05 Vp-p Unit
[AK2048]
Comments Refer Fig.1,
Refer Fig.1, *1), Refer Fig.3 *3)Refer Fig.4
Delay time from TDATA TXA,TXB duty cycle TCLK 50%±4%. Duty cycle Tpwh (Tpwh Tpwl) 100% Signal output delay (1bit logical delay) (internal propagation delay)
Transmit output amplitude specified this point. (Va, VpeakH, VpeakL)
Fig.1 Measurement circuit
VpeakH
VpeakL
0.8Va
Tr,Tf
Fig.2 Rise fall times
MS0073-E-02
2002/05
[AK2048]
Tpwh
Tpwl
Fig.3 Transmit output pulse duty
TCLK TCRV TDATA TXA-TXB
shaded portion
Fig.4 Data input signal output delay time
MS0073-E-02
2002/05
[AK2048]
RECEIVER
Parameter REF25 output Signal loss threshold level Signal loss detection time Sensitivity Input jitter tolerance PSRR (Line Length 400m) tolerance Line Length 400m Signal input Data output delay time RCLK Output Jitter nsp-p Reference output fixed equalizer. amplitude input data 3.0±0.75Vp-p data pattern 215-1. Data output delay (1.25bit logical delay) (internal propagation delay) Data pattern "all space" with every 8kHz cycle.
135mVp-p TALM REF25
Symbol VREF TALM
0.15
Unit mVp-p usec Vp-p UIp-p mVp-p
Comments Iout<IuA terminal Fig.5
Jitter frequency 20KHz~100KHz frequency 1.9MHz Fig.6
1.25
Fig.5 output signal
RCLK RCRV RDATA
shaded portion
Fig.6 Delay time from RXA,RXB RDATA
MS0073-E-02
2002/05
[AK2048]
CHARACTERISTICS
Parameter Input Clock Frequency Duty Cycle Delay time from TCLK rising TDATA, TCRV. Output Clock Frequency Output Clock Duty Delay time from RCLK rising RDATA, RCRV. Name TCLK TCLK TDATA TCRV Symbol 2.048 Unit Refer Fig.7 Conditions Conditions
Refer Fig.8 rate received signal 2.048Mbps Refer Fig.7 Refer Fig.8
RCLK RCLK RDATA RCRV LOCK
fout
2.048
Refer Fig.9
Rise/Fall Time
RDATA RCLK RCRV
Delay time from RCLK rising
Refer Fig.8
Duty: Tpwh/(Tpwh+Tpwl) 100%
MS0073-E-02
2002/05
[AK2048]
Tpwh
Tpwl
Fig.7 Clock timing
TCLK, RCLK TDATA, RDATA TCRV, RCRV
Fig.8 Transmitter Timing
OUTPUT Measurement point
Fig.9 Rise fall times condition measurement.
MS0073-E-02
2002/05
[AK2048]
FUNCTIONAL DESCRIPTION
calibration function calibration caused case following 3cases. Power rising LOCK rising Power After power calibration complete LOCK goes "Low" less than 63ms from whichever later happens, input signal (RXA-RXB) rising edge RST. rising calibration complete LOCK goes "Low" less than 38ms from whichever later happens, input signal (RXA-RXB) rising edge RST. LOCK rising When device falls into unlock some reasons LOCK goes "high", calibration restarts. calibration complete LOCK goes "Low" less than 38ms from rising edge LOCK. pull time after loss signal When goes "high" loss signal after calibration, pull restarts signal input. device pull without calibration, pull-in completes less than 200us. other case, LOCK goes "high" calibration restarts less than 2ms. signal goes "high", when amplitude less than 135mVpp(typ) during bits (about 8us). signal goes "Low", when amplitude more than 135mVpp(typ). When signal lost during calibration, signal goes "high" calibration circuit reset. calibration restarts after signal goes "Low".
MS0073-E-02
2002/05
[AK2048]
(Code Rule Violation) code with violation called (Modified Dipulse) code. refer Fig.10. Generally speaking, (Code Rule Violation) generated code "1". AK2048D generates violation only code "1", also code "0". Violation code refer Fig.11.
CLOCK
violation
MARK(1) SPACE(0)
Fig.10 code
CODE
Violation CODE
Fig.11 Violation CODE
MS0073-E-02
2002/05
[AK2048]
RECOMMENDED EXTERNAL CIRCUITS
RXA(33)
input
1:1CT
EQL.
REF25(31) RXB(29)
AK2048D
RVDD(40) TVDD(25) TXA(23) RVSS(42) TVSS(24) TXA(26)
output
1:1CT
Transmit output amplitude specified this point. (Described page Va,VpeakH,VpeakL)
Fig.12 example external circuits
recommended that Shott diode connected protection latch-up.
MS0073-E-02
2002/05
[AK2048]
PACKAGE
18.2±0.4
14TYP
0.5MAX
18.2±0.4
14TYP
XXXXYZZ AK2048D JAPAN
0-15
1±0.16
0.4±0.1
2.9MAX 0.96TYP 0.15±0.05
1±0.4
MS0073-E-02
2002/05
[AK2048]
IMPORTANT NOTICE These products their specifications subject change without notice. Before considering
application, consult Asahi Kasei Microsystems Co., Ltd. (AKM) sales office authorized distributor concerning their current status. assumes liability infringement patent, intellectual property, other right application information contained herein. export these products, devices systems containing them, require export license other official approval under regulations country export pertaining customs tariffs, currency exchange, strategic materials. products neither intended authorized critical components safety, life support, other hazard related device system, assumes responsibility relating such use, except with express written consent Representative Director AKM. here: hazard related device system designed intended life support maintenance safety applications medicine, aerospace, nuclear energy, other fields, which failure function perform reasonably expected result loss life significant injury damage person property. critical component whose failure function perform reasonably expected result, whether directly indirectly, loss safety effectiveness device system containing which must therefore meet very high standards performance reliability. responsibility buyer distributor product distributes, disposes otherwise places product with third party notify that party advance above content conditions, buyer distributor agrees assume responsibility liability hold harmless from claims arising from said product absence such notification. used
MS0073-E-02
2002/05

AK2048D Transceiver FEATURES 2.048Mbps Interface CLOCK DATA

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