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SST39SF512 SST39SF010 Data Sheet FEATURES: Organized 128K Single


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Kbit Mbit (x8) Multi-Purpose Flash
SST39SF512 SST39SF010
Data Sheet FEATURES: Organized 128K Single 5.0V Read Write Operations Superior Reliability Endurance: 100,000 Cycles (typical) Greater than years Data Retention Power Consumption: Active Current: (typical) Standby Current: (typical) Sector-Erase Capability Uniform KByte sectors Fast Read Access Time: Latched Address Data Fast Erase Byte-Program: Sector-Erase Time: (typical) Chip-Erase Time: (typical) Byte-Program Time: (typical) Chip Rewrite Time: seconds (typical) SST39SF512 seconds (typical) SST39SF010 Automatic Write Timing Internal Generation End-of-Write Detection Toggle Data# Polling Compatibility JEDEC Standard Flash EEPROM Pinouts command sets Packages Available 32-Pin PDIP 32-Pin PLCC 32-Pin TSOP (8mm 14mm)
PRODUCT DESCRIPTION SST39SF512/010 CMOS Multi-Purpose Flash (MPF) manufactured with SST's proprietary, high performance CMOS SuperFlash technology. split-gate cell design thick oxide tunneling injector attain better reliability manufacturability compared with alternate approaches. SST39SF512/010 devices write (Program Erase) with 5.0V-only power supply. SST39SF512/010 device conforms JEDEC standard pinouts memories. Featuring high performance Byte-Program, SST39SF512/010 devices provide maximum ByteProgram time µsec. These devices Toggle Data# Polling indicate completion Program operation. protect against inadvertent write, they have on-chip hardware Software Data Protection schemes. Designed, manufactured, tested wide spectrum applications, these devices offered with guaranteed endurance 10,000 cycles. Data retention rated greater than years. SST39SF512/010 devices suited applications that require convenient economical updating program, configuration, data memory. system applications, they significantly improve performance reliability, while lowering power consumption. They inherently less energy during erase program than alternative flash technologies. total energy consumed function
2001 Silicon Storage Technology, Inc. 394-2 1/01 S71149
applied voltage, current, time application. Since given voltage range, SuperFlash technology uses less current program shorter erase time, total energy consumed during Erase Program operation less than alternative flash technologies. These devices also improve flexibility while lowering cost program, data, configuration storage applications. SuperFlash technology provides fixed Erase Program times, independent number Erase/ Program cycles that have occurred. Therefore system software hardware does have modified de-rated necessary with alternative flash technologies, whose Erase Program times increase with accumulated Erase/Program cycles. meet high density, surface mount requirements, SST39SF512/010 offered 32-pin TSOP 32-pin PLCC packages. mil, 32-pin PDIP also available. Figures pinouts. Device Operation Commands used initiate memory operation functions device. Commands written device using standard microprocessor write sequences. command written asserting while keeping low. address latched falling edge CE#, whichever occurs last. data latched rising edge CE#, whichever occurs first.
logo SuperFlash registered trademarks Silicon Storage Technology, Inc. trademark Silicon storage Technology, Inc. These specifications subject change without notice.
Kbit Mbit Multi-Purpose Flash SST39SF512 SST39SF010
Data Sheet Read Read operation SST39SF512/010 controlled OE#, both have system obtain data from outputs. used device selection. When high, chip deselected only standby power consumed. output control used gate data from output pins. data high impedance state when either high. Refer Read cycle timing diagram further details (Figure Byte-Program Operation SST39SF512/010 programmed byte-by-byte basis. Program operation consists three steps. first step three-byte-load sequence Software Data Protection. second step load byte address byte data. During Byte-Program operation, addresses latched falling edge either WE#, whichever occurs last. data latched rising edge either WE#, whichever occurs first. third step internal Program operation which initiated after rising edge fourth CE#, whichever occurs first. Program operation, once initiated, will completed, within Figures controlled Program operation timing diagrams Figure flowcharts. During Program operation, only valid reads Data# Polling Toggle Bit. During internal Program operation, host free perform additional tasks. commands written during internal Program operation will ignored. Sector-Erase Operation Sector-Erase operation allows system erase device sector-by-sector basis. sector architecture based uniform sector size KByte. Sector-Erase operation initiated executing six-byte-command load sequence Software Data Protection with Sector-Erase command (30H) sector address (SA) last cycle. sector address latched falling edge sixth pulse while command (30H) latched rising edge sixth pulse. internal Erase operation begins after sixth pulse. Erase determined using either Data# Polling Toggle methods. Figure timing waveforms. commands written during Sector-Erase operation will ignored. Chip-Erase Operation SST39SF512/010 provide Chip-Erase operation, which allows user erase entire memory array "1's" state. This useful when entire device must quickly erased.
2001 Silicon Storage Technology, Inc.
Chip-Erase operation initiated executing sixbyte Software Data Protection command sequence with Chip-Erase command (10H) with address 5555H last byte sequence. Erase operation begins with rising edge sixth CE#, whichever occurs first. During Erase operation, only valid read Toggle Data# Polling. Table command sequence, Figure timing diagram, Figure flowchart. commands written during ChipErase operation will ignored. Write Operation Status Detection SST39SF512/010 provide software means detect completion Write (Program Erase) cycle, order optimize system Write cycle time. software detection includes status bits: Data# Polling (DQ7) Toggle (DQ6). End-of-Write detection mode enabled after rising edge WE#, which initiates program erase cycle. actual completion nonvolatile write asynchronous with system; therefore, either Data# Polling Toggle read simultaneous with completion Write cycle. this occurs, system possibly erroneous result, i.e., valid data appear conflict with either DQ6. order prevent spurious rejection, erroneous result occurs, software routine should include loop read accessed location additional times. both reads valid, then device completed Write cycle, otherwise rejection valid. Data# Polling (DQ7) When SST39SF512/010 internal Program operation, attempt read will produce complement true data. Once Program operation completed, will produce true data. device then ready next operation. During internal Erase operation, attempt read will produce `0'. Once internal Erase operation completed, will produce `1'. Data# Polling valid after rising edge fourth CE#) pulse Program Operation. sector Chip-Erase, Data# Polling valid after rising edge sixth CE#) pulse. Figure Data# Polling timing diagram Figure flowchart. Toggle (DQ6) During internal Program Erase operation, consecutive attempts read will produce alternating 1's, i.e., toggling between Toggle will begin with "1". When internal Program Erase operation completed, toggling will stop. device then ready next operation. Toggle valid after rising
S71149 394-2 1/01
Kbit Mbit Multi-Purpose Flash SST39SF512 SST39SF010
Data Sheet edge fourth CE#) pulse Program operation. Sector Chip-Erase, Toggle valid after rising edge sixth CE#) pulse. Figure Toggle timing diagram Figure flowchart. Data Protection SST39SF512/010 provide both hardware software features protect nonvolatile data from inadvertent writes. Hardware Data Protection Noise/Glitch Protection: pulse less than will initiate Write cycle. Power Up/Down Detection: write operation inhibited when less than 2.5V. Write Inhibit Mode: Forcing low, high, high will inhibit Write operation. This prevents inadvertent writes during power-up power-down. Software Data Protection (SDP) SST39SF512/010 provide JEDEC approved Software Data Protection scheme data alteration operations, i.e., Program Erase. Program operation requires inclusion series three byte sequence. three byte-load sequence used initiate Program operation, providing optimal protection from inadvertent write operations, e.g., during system power-up power-down. Erase operation requires inclusion byte load sequence. SST39SF512 device shipped with Software Data Protection permanently enabled. Table specific software command codes. During command sequence, invalid commands will abort device read mode, within TRC. Product Identification product identification mode identifies device SST39SF512 SST39SF010 manufacturer SST. This mode accessed hardware software operations. hardware operation typically used programmer identify correct algorithm SST39SF512/010. Users wish software product identification operation identify part (i.e., using device code) when using multiple manufacturers same socket. details, Table hardware operation Table software operation, Figure software entry read timing diagram Figure entry command sequence flowchart. TABLE PRODUCT IDENTIFICATION Address Manufacturer's Device SST39SF512 SST39SF010 0001H 0001H
T1.1
Data
0000H
Product Identification Mode Exit/Reset order return standard read mode, Software Product Identification mode must exited. Exit accomplished issuing Exit command sequence, which returns device Read operation. Please note that software reset command ignored during internal Program Erase operation. Table software command codes, Figure timing waveform Figure flowchart.
FUNCTIONAL BLOCK DIAGRAM
SuperFlash Memory
X-Decoder
Memory Address
Address Buffers Latches Y-Decoder
B1.1
Control Logic
Buffers Data Latches
2001 Silicon Storage Technology, Inc.
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Kbit Mbit Multi-Purpose Flash SST39SF512 SST39SF010
Data Sheet
SST39SF010 SST39SF512 SST39SF512 SST39SF010
Standard Pinout View
F01.2
FIGURE ASSIGNMENTS 32-PIN TSOP (8mm 14mm)
SST39SF010 SST39SF512
SST39SF512 SST39SF010
32-Pin PDIP View
F02a.2
FIGURE ASSIGNMENTS 32-PIN PDIP
2001 Silicon Storage Technology, Inc.
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Kbit Mbit Multi-Purpose Flash SST39SF512 SST39SF010
Data Sheet
SST39SF512 SST39SF010
SST39SF010 SST39SF512
SST39SF512 SST39SF010
SST39SF010 SST39SF512
32-Pin PLCC View
F02b.3
FIGURE ASSIGNMENTS 32-PIN PLCC
2001 Silicon Storage Technology, Inc.
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Kbit Mbit Multi-Purpose Flash SST39SF512 SST39SF010
Data Sheet TABLE DESCRIPTION Symbol AMS-A0 lines DQ7-DQ0 Name Address Inputs Data Input/output Functions provide memory addresses. During Sector-Erase AMS-A12 address will select sector. output data during Read cycles receive input data during Write cycles. Data internally latched during Write cycle. outputs tri-state when high. activate device when low. gate data output buffers. control Write operations. provide 5-volt supply 10%) Unconnected pins.
T2.2
Chip Enable Output Enable Write Enable Power Supply Ground Connection
Note: Most significant address SST39SF512 SST39SF010
TABLE OPERATION MODES SELECTION Mode Read Program Erase Standby Write Inhibit Product Identification Hardware Mode Software Mode
DOUT High High Z/DOUT High Z/DOUT Manufacturer's (BFH) Device Code
Address Sector address, Chip-Erase AMS(2) VIL, AMS(2) VIL, Table
T3.1
Note: Device SST39SF512 SST39SF010 Most significant address SST39SF512 SST39SF010
2001 Silicon Storage Technology, Inc.
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Kbit Mbit Multi-Purpose Flash SST39SF512 SST39SF010
Data Sheet TABLE SOFTWARE COMMAND SEQUENCE
Command Sequence Write Cycle Addr(1) Data Byte-Program 5555H Sector-Erase 5555H Chip-Erase 5555H Software Entry 5555H Software Exit Software Exit 5555H Write Cycle Addr(1) Data 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH Write Cycle Addr(1) Data 5555H 5555H 5555H 5555H 5555H
T4.1
Write Cycle Addr(1) Data BA(3) Data 5555H 5555H
Write Cycle Addr(1) Data 2AAAH 2AAAH
Write Cycle Addr(1) Data SAx(2) 5555H
Notes:
Address format A14-A0 (Hex), Address "Don't Care" Command sequence SST39SF512. Address "Don't Care" Command sequence SST39SF010. Sector-Erase; uses AMS-A12 address lines Most significant address SST39SF512 SST39SF010 Program Byte address Both Software Exit operations equivalent With Manufacturer's BFH, read with SST39SF512 Device read with SST39SF010 Device read with device does remain Software Product Mode powered down.
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" cause permanent damage device. This stress rating only functional operation device these conditions conditions greater than those defined operational sections this data sheet implied. Exposure absolute maximum stress rating conditions affect device reliability.) Temperature Under Bias -55°C +125°C Storage Temperature -65°C +150°C Voltage Ground Potential -0.5V VDD+ 0.5V Transient Voltage (<20 Ground Potential -1.0V VDD+ 1.0V Voltage Ground Potential -0.5V 14.0V Package Power Dissipation Capability 25°C) 1.0W Through Hole Lead Soldering Temperature Seconds) 300°C Surface Mount Lead Soldering Temperature Seconds) 240°C Output Short Circuit Current(1)
Note:
Outputs shorted more than second. more than output shorted time.
OPERATING RANGE Range Ambient Temp Commercial Industrial
CONDITIONS TEST 5V±10% 5V±10% Input Rise/Fall Time Output Load Output Load Figures
2001 Silicon Storage Technology, Inc.
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Kbit Mbit Multi-Purpose Flash SST39SF512 SST39SF010
Data Sheet TABLE OPERATING CHARACTERISTICS 5V±10% Limits Symbol Parameter Power Supply Current Read Write Standby Current (TTL input) Standby Current (CMOS input) Input Leakage Current Output Leakage Current Input Voltage Input High Voltage Output Voltage Output High Voltage Supervoltage Supervoltage Current 11.4 12.6
Units
Test Conditions Address input VIL/VIH, f=1/TRC Min., VDD=VDD Max. CE#=OE#=VIL,WE#=VIH I/Os open CE#=WE#=VIL, OE#=VIH CE#=VIH, =VDD Max. CE#=VDD -0.3V. Max. =GND VDD, Max. VOUT =GND VDD, Max. Min. Max. Min. -400µA, Min. =VIL, VIL, VIH, Max.
T5.1
TABLE RECOMMENDED SYSTEM POWER-UP TIMINGS Symbol TPU-READ(1) TPU-WRITE(1) Parameter Power-up Read Operation Power-up Write Operation Minimum Units
T6.0
TABLE CAPACITANCE Mhz, other pins open) Parameter Description Test Condition CI/O CIN(1)
Maximum
T7.0
Capacitance Input Capacitance
VI/O
Note: (1)This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE RELIABILITY CHARACTERISTICS Symbol Parameter NEND(1) TDR(1) VZAP_HBM(1) VZAP_MM(1) ILTH(1)
Note:
(1)This
Minimum Specification 10,000 2000
Units Cycles Years Volts Volts
Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard A114 JEDEC Standard A115 JEDEC Standard
T8.0
Endurance Data Retention Susceptibility Human Body Model Susceptibility Machine Model Latch
parameter measured only initial qualification after design process change that could affect this parameter.
2001 Silicon Storage Technology, Inc.
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Kbit Mbit Multi-Purpose Flash SST39SF512 SST39SF010
Data Sheet CHARACTERISTICS TABLE READ CYCLE TIMING PARAMETERS 4.5-5.5V Symbol TCLZ(1) TOLZ(1) TCHZ(1) TOHZ(1) TOH(1) Parameter Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time Active Output Active Output High High-Z Output High High-Z Output Output Hold from Address Change SST39SF512/010-70 SST39SF512/010-90 Units
T9.1
Units
T10.0
Note:
TABLE PROGRAM/ERASE CYCLE TIMING PARAMETERS Symbol Parameter Byte-Program Time Address Setup Time Address Hold Time Setup Time Hold Time TOES High Setup Time TOEH High Hold Time Pulse Width Pulse Width TWPH Pulse Width High TCPH Pulse Width High Data Setup Time Data Hold Time TIDA Software Access Exit Time Sector-Erase TSCE Chip-Erase
Note:
(1)This
parameter measured only initial qualification after design process change that could affect this parameter.
2001 Silicon Storage Technology, Inc.
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Kbit Mbit Multi-Purpose Flash SST39SF512 SST39SF010
Data Sheet
ADDRESS AMS-0
TOLZ
TOHZ TCHZ HIGH-Z DATA VALID
DQ7-0
HIGH-Z
TCLZ
DATA VALID
Note: Most significant address SST39SF512 SST39SF010
F03.1
FIGURE READ CYCLE TIMING DIAGRAM
INTERNAL PROGRAM OPERATION STARTS ADDRESS AMS-0 5555 DQ7-0 DATA BYTE (ADDR/DATA) TWPH 2AAA 5555 ADDR
F04.1
Note: Most significant address SST39SF512 SST39SF010
FIGURE CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
2001 Silicon Storage Technology, Inc.
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Kbit Mbit Multi-Purpose Flash SST39SF512 SST39SF010
Data Sheet
INTERNAL PROGRAM OPERATION STARTS ADDRESS AMS-0 5555 DQ7-0 DATA BYTE (ADDR/DATA) TCPH 2AAA 5555 ADDR
F05.1
Note: Most significant address SST39SF512 SST39SF010
FIGURE CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
ADDRESS AMS-0 TOEH TOES
F06.1
Note: Most significant address SST39SF512 SST39SF010
FIGURE DATA# POLLING TIMING DIAGRAM
2001 Silicon Storage Technology, Inc.
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Kbit Mbit Multi-Purpose Flash SST39SF512 SST39SF010
Data Sheet
ADDRESS AMS-0 TOEH TOES
Note
Note: Toggle output always high first. Most significant address SST39SF512 SST39SF010
READ CYCLES WITH SAME OUTPUTS F07.1
FIGURE TOGGLE TIMING DIAGRAM
SIX-BYTE CODE SECTOR-ERASE ADDRESS AMS-0 5555 2AAA 5555 5555 2AAA
DQ7-0
F08.2
Note: This device also supports controlled Sector-Erase operation. signals interchageable long minimum timings met. (See Table Sector Address Most significant address SST39SF512 SST39SF010
FIGURE CONTROLLED SECTOR-ERASE TIMING DIAGRAM
2001 Silicon Storage Technology, Inc.
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Kbit Mbit Multi-Purpose Flash SST39SF512 SST39SF010
Data Sheet
TSCE 5555
SIX-BYTE CODE CHIP-ERASE ADDRESS AMS-0 5555 2AAA 5555 5555 2AAA
DQ7-0
F17.1
Note: This device also supports controlled Chip-Erase operation. signals interchageable long minimum timings met. (See Table Sector Address Most significant address SST39SF512 SST39SF010
FIGURE CONTROLLED CHIP-ERASE TIMING DIAGRAM
Three-byte sequence Software Entry ADDRESS A14-0 5555 2AAA 5555 0000 0001
TWPH DQ7-0 Device TIDA
F09.2
Device SST39SF010 SST39SF020
FIGURE SOFTWARE ENTRY READ
2001 Silicon Storage Technology, Inc.
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Kbit Mbit Multi-Purpose Flash SST39SF512 SST39SF010
Data Sheet
THREE-BYTE SEQUENCE SOFTWARE EXIT RESET
ADDRESS A14-0
5555
2AAA
5555
DQ7-0
TIDA
F10.0
FIGURE SOFTWARE EXIT RESET
2001 Silicon Storage Technology, Inc.
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Kbit Mbit Multi-Purpose Flash SST39SF512 SST39SF010
Data Sheet
VIHT
INPUT REFERENCE POINTS
OUTPUT
VILT
F11.0
test inputs driven VIHT (2.4 logic VILT (0.4 logic "0". Measurement reference points inputs outputs (2.0 (0.8 Inputs rise fall times (10% 90%)
Note: VHT-VHIGH Test VLT-VLOW Test VIHT-VINPUT HIGH Test VILT-VINPUT Test
FIGURE INPUT/OUTPUT REFERENCE WAVEFORMS
TEST LOAD EXAMPLE TESTER HIGH
F12.1
FIGURE TEST LOAD EXAMPLE
2001 Silicon Storage Technology, Inc.
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Kbit Mbit Multi-Purpose Flash SST39SF512 SST39SF010
Data Sheet
Start
Load data: Address: 5555H
Load data: Address: 2AAAH
Load data: Address: 5555H
Byte Address/Byte Data
Wait Program (TBP' Data# Polling Toggle operation) Program Completed
F13.1
FIGURE BYTE-PROGRAM ALGORITHM
2001 Silicon Storage Technology, Inc.
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Kbit Mbit Multi-Purpose Flash SST39SF512 SST39SF010
Data Sheet
Internal Timer Program/Erase Initiated Toggle Byte-Program/ Sector Erase Initiated Data# Polling Byte-Program Initiated
Wait TBP, TSCE,
Read byte
Read
Program/Erase Completed
Read same byte
true data?
Does match?
Write Completed
Write Completed
F14.0
FIGURE WAIT OPTIONS
2001 Silicon Storage Technology, Inc.
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Kbit Mbit Multi-Purpose Flash SST39SF512 SST39SF010
Data Sheet
Software Product Entry Command Sequence
Software Product Exit Reset Command Sequence
Load data: Address: 5555H
Load data: Address: 5555H
Load data: Address:
Load data: Address: 2AAAH
Load data: Address: 2AAAH
Wait TIDA
Load data: Address: 5555H
Load data: Address: 5555H
Return normal operation
Wait TIDA
Wait TIDA
Read Software
Return normal operation
F15.1
FIGURE SOFTWARE PRODUCT COMMAND FLOWCHARTS
2001 Silicon Storage Technology, Inc.
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Kbit Mbit Multi-Purpose Flash SST39SF512 SST39SF010
Data Sheet
Chip-Erase Command Sequence Load data: Address: 5555H
Sector-Erase Command Sequence Load data: Address: 5555H
Load data: Address: 2AAAH
Load data: Address: 2AAAH
Load data: Address: 5555H
Load data: Address: 5555H
Load data: Address: 5555H
Load data: Address: 5555H
Load data: Address: 2AAAH
Load data: Address: 2AAAH
Load data: Address: 5555H Load data: Address:
Wait TSCE
Wait
Chip-Erase
Sector-Erase
F16.1
FIGURE ERASE COMMAND SEQUENCE
2001 Silicon Storage Technology, Inc.
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Kbit Mbit Multi-Purpose Flash SST39SF512 SST39SF010
Data Sheet Device SST39SFxxx Speed Suffix1 Suffix2 Package Modifier leads Numeric modifier Package Type PDIP PLCC TSOP (die (8mm 14mm) Unencapsulated Temperature Range Commercial 70°C Industrial -40° 85°C Minimum Endurance 10,000 cycles Read Access Speed Device Density Kilobit Megabit
SST39SF512 Valid combinations SST39SF512-70-4C-WH SST39SF512-70-4C-NH SST39SF512-90-4C-WH SST39SF512-90-4C-NH SST39SF512-90-4C-U3 SST39SF512-70-4I-WH SST39SF512-70-4I-NH SST39SF512-90-4I-WH SST39SF512-90-4I-NH SST39SF010 Valid combinations SST39SF010-70-4C-WH SST39SF010-70-4C-NH SST39SF010-90-4C-WH SST39SF010-90-4C-NH SST39SF010-90-4C-U4 SST39SF010-70-4I-WH SST39SF010-90-4I-WH SST39SF010-70-4I-NH SST39SF010-90-4I-NH
SST39SF512-70-4C-PH SST39SF512-90-4C-PH
SST39SF010-70-4C-PH SST39SF010-90-4C-PH
Example Valid combinations those products mass production will mass production. Consult your sales representative confirm availability valid combinations determine availability combinations.
2001 Silicon Storage Technology, Inc.
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Kbit Mbit Multi-Purpose Flash SST39SF512 SST39SF010
Data Sheet PACKAGING DIAGRAMS
index
.600 .625 .530 .550 .065 .075 1.645 1.655 PLCS.
Base Plane Seating Plane
.015 .050 .120 .150
.170 .200
.008 .012 .600
.070 .080
.045 .065
.016 .022
.100
Note:
Complies with JEDEC publication MO-015 dimensions, although some dimensions more stringent. linear dimensions inches (min/max). Dimensions include mold flash. Maximum allowable mold flash .010 inches.
32.pdipPH-ILL.1
32-PIN PLASTIC DUAL-IN-LINE PACKAGE (PDIP) PACKAGE CODE:
VIEW
SIDE VIEW
BOTTOM VIEW
Optional Identifier .485 .495 .447 .453 .042 .048
.106 .112 .020 MAX. .023 .029 .030 .040
.042 .048 .585 .595 .547 .553 .026 .032
.013 .021 .400
.490 .530
.050 BSC. .015 Min. .050 BSC. .125 .140 .075 .095 .026 .032
32.PLCC.NH-ILL.1
Note:
Complies with JEDEC publication MS-016 dimensions, although some dimensions more stringent. linear dimensions inches (min/max). Dimensions include mold flash. Maximum allowable mold flash .008 inches.
32-PIN PLASTIC LEAD CHIP CARRIER (PLCC) PACKAGE CODE:
2001 Silicon Storage Technology, Inc.
S71149
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Kbit Mbit Multi-Purpose Flash SST39SF512 SST39SF010
Data Sheet
1.05 0.95
IDENTIFIER
8.10 7.90
.270 .170
12.50 12.30
0.15 0.05
0.70 0.50
14.20 13.80
Note:
Complies with JEDEC publication MO-142 dimensions, although some dimensions more stringent. linear dimensions millimeters (min/max). Coplanarity: (±.05)
32.TSOP-WH-ILL.3
32-PIN THIN SMALL OUTLINE PACKAGE (TSOP) PACKAGE CODE:
Silicon Storage Technology, Inc. 1171 Sonora Court Sunnyvale, 94086 Telephone 408-735-9110 408-735-9036 www.SuperFlash.com www.ssti.com
2001 Silicon Storage Technology, Inc.
S71149
394-2 1/01

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