AK2546 channel Transceiver FEATURE short haul transceiver Jitter

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AK2546 channel Transceiver FEATURE short haul transceiver Jitter

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[AK2546]
AK2546 channel Transceiver
FEATURE short haul transceiver Jitter Tolerance: Compliant with GR-499 Category Transmitter Pulse Shape: Compliant with GR-499 Loss Signal Detection Selectable Signal Polarity Local/Remote Loopback Parallel Microprocessor Interface Single 3.3V±5% Operation Power Consumption (105mW/ch: Typ) Pin-to-pin compatible with AK2548 channel transceiver) Small Plastic Package 144pin LQFP
BLOCK DIAGRAM
MCLK CLKSEL CLKSEL RESET TEST1TEST1- (WR) AD7AD7-
CLKGEN CONTROL
AS(ALE) DS(RD) LOS1
TRANSCEIVER
RTIP1
Remote Loopback
Local Loopback
RECOVER
RRING1 TTIP1 TRING1
RCLK1 RPOS1 RNEG1 TCLK1 TPOS1 TNEG1
SHAPER
RTIP2RTIP2- RRING2RRING2 TTIP2TTIP2- TRING2-7 TRING2-
TRANSCEIVER
LOS2LOS2- RCLK2RCLK2- RPOS2RPOS2- RNEG2RNEG2- TCLK2TCLK2- TPOS2-7 TPOS2TNEG2-7 TNEG2-
Channel Transceiver Block Diagram
<C0019-E-02>
2002/5
[AK2546]
GENERAL DESCRIPTION AK2546 channel short haul transceiver SONET MUX, MUX, etc. includes seven independent transmitters, clock data recovery, detector, control circuit LQFP-144 package which saves space, power consumption board design time. Internally generated transmit pulse provides appropriate pulse shape line length ranging from feet from DSX-1 cross connect.
ASSIGNMENTS
AVSS8 TTIP7 TVSS7 TVDD7 TRING7 AVSS7 TTIP6 TVSS6 TVDD6 TRING6 AVSS6 TTIP5 TVSS5 TVDD5 TRING5 AVSS5 TTIP4 TVSS4 TVDD4 TRING4 AVSS4 TTIP3 TVSS3 TVDD3 TRING3 AVSS3 TTIP2 TVSS2 TVDD2 TRING2 AVSS2 TTIP1 TVSS1 TVDD1 TRING1 AVSS1 TCLK7 TPOS7 TNEG7 RCLK7 RPOS7 RNEG7 TCLK6 TPOS6 TNEG6 RCLK6 RPOS6 RNEG6 IOVDD2 IOVSS2 TAVDD2 TAVSS2 TCLK5 TPOS5 TNEG5 RCLK5 RPOS5 RNEG5 DAVSS2 DVSS2 DVDD2 LOS7 LOS6 LOS5
(TOP VIEW)
TCLK1 TPOS1 TNEG1 RCLK1 RPOS1 RNEG1 TCLK2 TPOS2 TNEG2 RCLK2 RPOS2 RNEG2 IOVDD1 IOVSS1 TAVDD1 TAVSS1 TCLK3 TPOS3 TNEG3 RCLK3 RPOS3 RNEG3 DAVSS1 DVSS1 DVDD1 TCLK4 TPOS4 TNEG4 RCLK4 RPOS4 RNEG4 LOS1 LOS2 LOS3 LOS4 RAVDD1
<C0019-E-02>
R/W(WR) AS(ALE) DS(RD) PVDD MCLK PVSS RAVSS2 RAVDD2 RESET RRING7 RTIP7 RRING6 RTIP6 TEST5 RRING5 RTIP5 TEST4 BVSS BGREF BVDD TEST3 RRING4 RTIP4 TEST2 RRING3 RTIP3 CLKSEL RRING2 RTIP2 TEST1 RRING1 RTIP1 RAVSS1
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[AK2546]
CONDITION
Name TCLK7 TPOS7 TNEG7 RCLK7 RPOS7 RNEG7 TCLK6 TPOS6 TNEG6 RCLK6 RPOS6 RNEG6 IOVDD2 IOVSS2 TAVDD2 TAVSS2 TCLK5 TPOS5 TNEG5 RCLK5 RPOS5 RNEG5 DAVSS2 DVSS2 DVDD2 LOS7 LOS6 LOS5
Type CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS Power Power Power Power CMOS CMOS CMOS CMOS CMOS CMOS Power Power Power CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
Load
Load
Comments
15pF 15pF 15pF
15pF 15pF 15pF
15pF 15pF 15pF
15pF 15pF 15pF 50pF 50pF 50pF 50pF 50pF 50pF 50pF 50pF
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[AK2546]
Name R/W(WR) AS(ALE) DS(RD) PVDD MCLK PVSS RAVSS2 RAVDD2 RESET RRING7 RTIP7 RRING6 RTIP6 TEST5 RRING5 RTIP5 TEST4 BVSS BGREF BVDD TEST3 RRING4 RTIP4 TEST2 RRING3 RTIP3 CLKSEL RRING2 RTIP2 TEST1 RRING1 RTIP1 RAVSS1
Type CMOS CMOS CMOS CMOS Open drain Power CMOS Power Power Power CMOS Analog Analog CMOS Analog Analog CMOS Analog Analog CMOS Power Analog Power CMOS Analog Analog CMOS Analog Analog CMOS Analog Analog CMOS Analog Analog Power
Load
Load
Comments
PMOS Open drain
Note1)
Note1) accuracy Note1)
Note2)
Note1)
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[AK2546]
Name RAVDD1 LOS4 LOS3 LOS2 LOS1 RNEG4 RPOS4 RCLK4 TNEG4 TPOS4 TCLK4 DVDD1 DVSS1 DAVSS1 RNEG3 RPOS3 RCLK3 TNEG3 TPOS3 TCLK3 TAVSS1 TAVDD1 IOVSS1 IOVDD1 RNEG2 RPOS2 RCLK2 TNEG2 TPOS2 TCLK2 RNEG1 RPOS1 RCLK1 TNEG1 TPOS1 TCLK1
Type Power CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS Power Power Power CMOS CMOS CMOS CMOS CMOS CMOS Power Power Power Power CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
Load 15pF 15pF 15pF 15pF 15pF 15pF 15pF
Load
Comments
15pF 15pF 15pF
15pF 15pF 15pF
15pF 15pF 15pF
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[AK2546]
Name AVSS1 TRING1 TVDD1 TVSS1 TTIP1 AVSS2 TRING2 TVDD2 TVSS2 TTIP2 AVSS3 TRING3 TVDD3 TVSS3 TTIP3 AVSS4 TRING4 TVDD4 TVSS4 TTIP4 AVSS5 TRING5 TVDD5 TVSS5 TTIP5 AVSS6 TRING6 TVDD6 TVSS6 TTIP6 AVSS7 TRING7 TVDD7 TVSS7 TTIP7 AVSS8
Type Power Analog Power Power Analog Power Analog Power Power Analog Power Analog Power Power Analog Power Analog Power Power Analog Power Analog Power Power Analog Power Analog Power Power Analog Power Analog Power Power Analog Power
Load
Load
Comments driver output
driver output driver output
driver output driver output
driver output driver output
driver output driver output
driver output driver output
driver output driver output
driver output
Note1 Should connected externally. Note2 Should connected externally
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ASAHI KASEI DESCRIPTIONS
Name TTIP1-7 TRING1-7 TPOS1-7 TNEG1-7 TCLK1-7 RTIP1-7 RRING1-7 RPOS1-7 RNEG1-7 RCLK1-7 LOS1-7 Transmit Tip/Ring Output Bipolar output over transmit transformer Transmit Positive/Negative Data Input Input falling edge TCLK Transmit Clock Input Receive Tip/Ring Input Bipolar Input over receive transformer Receive Positive/Negative Data Output Output falling edge RCLK Receive Clock Output recovered from receive data input Loss signal output Output "high" when detect loss signal LOSx output masked MLOSx register. TVDD1-7 TVSS1-7 AVSS1-8 Common Block MCLK AS(ALE) 1.544MHz 24.704MHz External Reference Clock Input Address Select(Address Latch Enable) Input Interrupt Output(PMOS open drain, should tied through resistor), Active High, output goes "high" when alarm reported LOSx, LOTCx LOMC registers. This masked MLOSx, MLOTCx MLOMC registers. DS(RD) (WR) Data Strobe(Read Enable) Input Read/Write(Write Enable) Input Chip Select Input Type Select Input BTS="H" Motorola Mode BTS="L" Intel Mode AD0-AD7 CLKSEL Address/Data Input/Output Used read/write internal registers. MCLK Select Input CLKSEL="H":1.544MHz CLKSEL="L":24.704MHz RESET Reset Input Active "Low" input pulse over 200ns initializes internal circuit forces RPOSx/RNEGx output "low" LOSx output "high". Positive Power Supply Transmit Driver Negative Power Supply Transmit Driver Analog ground Function
[AK2546]
Comment
Transceiver
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[AK2546]
Name TEST1,3-5 TEST2 TAVDD1,2 TAVSS1,2 RAVDD1,2 RAVSS1,2 DVDD1,2 DVSS1,2 DAVSS1,2 IOVDD1,2 IOVSS1,2 BVDD BVSS PVDD PVSS BGREF
Function Factory Use. Should connected externally. Factory Use. Should connected externally. Positive Power Supply analog circuitry transmitters Negative Power Supply analog circuitry transmitters Positive Power Supply digital circuitry transmitters Negative Power Supply digital circuitry transmitters Positive Power Supply Digital Negative Power Supply Digital Ground Digital Positive Power Supply Negative Power Supply Positive Power Supply Reference Circuit Negative Power Supply Reference Circuit Positive Power Supply Negative Power Supply Bandgap Reference Output. 12k±1% external register should connected across this VSS.
Comment
Common block
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[AK2546]
ABSOLUTE MAXIMUM RATINGS
Parameter Supply Input Voltage
Symbol VIN1 VIN2
-0.3 -0.3
VDD+0.3 VDD+0.3
Units
Condition
Apply except RTIPx, RRINGx Apply RTIPx, RRINGx
Input Current Storage Temperature
Tstg
Note) voltages with respect ground. negative voltage pins apply positive voltage pins.
RECOMMENDED OPERATING CONDITIONS
Parameter Supply Ambient Operating Temperature
Symbol
3.135
3.465
Units
Condition 3.3V±5%
Note) voltages with respect ground. negative voltage pins apply positive voltage pins.
ELECTORICAL CHARACTERISTICS
CHARACTERISTICS
Parameter Power Consumption(/ch) Digital High-Level Output Voltage Digital Low-Level Output Voltage Digital High-Level Input Voltage Digital Low-Level Input Voltage Input Leak Current Output Current Symbol 0.7VDD 0.3VDD 0.9VDD Units Note1 IOH=-40µA IOL=500µA Condition
Note1: mark, Room temp., 3.3V, line length 399feet, Load max: 100% mark, Temp./VDD range, line length 655feet, Load include other load (ex. External pull register) except lines.
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[AK2546]
RECEIVER
Receiver characteristics guaranteed conditions shown below. VDD=3.3V±5%, VSS, GND=0V, Ta=-40~85°C, MCLK frequency: 1.544MHz±100ppm, 24.704MHz±100ppm, Bipolar input frequency: 1.544MHz±130ppm(reference input level: 3V0p±20%) Parameter Sensitivity Loss Signal Threshold Allowable Consecutive Zero before tolerance Generated Jitter pulse density immunity Jitter Tolerance Symbol 0.35 Units bits Note3 nspp Note4 Note1 Note2 Condition
1/16 GR-499 Category I,II
Mark
Note1: Relative value reference level. Compare 772kHz with Mark Pattern. Note2: Level chip side transformer. Loss signal logical between analog loss Signal monitors input level digital loss signal check recovered data stream. Note3: PN20 Mark pattern input. Noise frequency 770kHz. Note4: PN20 pattern input.
JITTER TOLERANCE
Jitter Amplitude(UIpp) 0.01 1000 10000 100000 Jiiter Frequency(Hz)
GR-499 Category
GR-499 Category
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[AK2546]
TRANSMITTER
Transmitter characteristics guaranteed conditions shown below. VDD=3.3V±5%, VSS, GND=0V,Ta=-40~85°C, MCLK frequency: 1.544MHz±100ppm, 24.704MHz±100ppm Parameter Output Pulse Shape Output Pulse Amplitude Output Pulse Imbalance Output Jitter 10Hz-8kHz 10Hz-40kHz 8kHz-40kHz Broad Band Power Levels@772kHz Power Levels @1.544MHz Note1: Measured terminated with 100. Note2: Amplitude pulse center normalize unity. Turns Ratio recommended value. Note3: Measured 2kHz band width around specified frequency. Transmit mark pattern. Note4: Compare power 772kHz 12.6 0.02 0.025 0.025 0.05 17.9 Note3 Note3, Note4 UIpp Symbol Units Condition
GR-499,Note1
Note1, Note2
ISOLATED PULSE MASK (GR-499)
Normalized Amplitude -0.5 -0.5 Time, Unit Intervals
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[AK2546]
CHARACTERISTICS (Clock/Data)
Parameter Clock Frequency Clock Pulse Width Clock Pulse Width Duty Cycle Setup/Hold Time MCLK MCLK TCLK RCLK RCLK TCLK RCLK RPOS RNEG Setup/Hold Time TCLK TPOS TNEG Rise Time RCLK RPOS RNEG Fall Time TCLK TPOS TNEG Note1) Duty Cycle:(tpwho/( Note2) Drive 15pF Load Capacitance
Symbol tpwhi tpwli tpwho tpwlo
Units
Condition
1.543846 1.544000 1.544154 24.70153 24.70400 24.70647
±100ppm Refer Fig.2 Refer Fig.1 Note1 Refer Fig.1
tsu1 tsu2
Refer Fig.2
Refer Fig.3 Note2
Refer Fig.3 Note2
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[AK2546]
tpwho
tpwlo tsur
RCLK
RPOS/RNEG
Fig.1
Receiver Timing
tpwli
tpwhi
TCLK
tsut
TPOS/TNEG
Fig.2
Transmitter Timing
Fig.3
Rise Fall Times
(RCLK, RPOS, RNEG, TCLK, TPOS, TNEG)
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[AK2546]
CHARACTERISTICS (Parallel Port)
Parameter Read/Write Cycle Motorola Mode Symbol tcyc Units Condition
Address Setup Time Address Hold Time Delay Time Delay Time Read Data Delay Time Read Data Hold Time Setup Time Hold Time Setup Time Hold Time Write Data Setup Time Write Data Hold Time Pulse Width Pulse Width Address Invalid Delay Time Intel Mode Address Setup Time Address Hold Time Delay Time Delay Time Delay Time Read Data Delay Time Read Data Hold Time Setup Time Hold Time Write Data Setup Time Write Data Hold Time Pulse Width Pulse Width Pulse Width Address Invalid Delay Time
Notes) 50pF AD0-AD7. timing specified 50%VDD.
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[AK2546]
Motorola Mode(READ)
Data
AD7-0
Address
Motorola Mode(WRITE)
Data
AD7-0
Address
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[AK2546]
Intel Mode(READ)
AD7-0 Data
Address
Intel Mode(WRITE)
AD7-0 Data
Address
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[AK2546]
REGISTER DESCRIPTION
REGISTER
*A7-A4="0" Address
Bit7 <AD7> Bit6 <AD6> Bit5 <AD5>
Function
Bit4 <AD4> Bit3 <AD3> Bit2 <AD2> Bit1 <AD1> Bit0 <AD0>
Status Register (READ ONLY)
LOS7 LOTC7
LOS6 LOTC6
LOS5 LOTC5
LOS4 LOTC4
LOS3 LOTC3
LOS2 LOTC2
LOS1 LOTC1
LOMC
Mask Control Register (WRITE/READ)
MLOS7 MLOTC7
MLOS6 MLOTC6
MLOS5 MLOTC5
MLOS4 MLOTC4
MLOS3 MLOTC3
MLOS2 MLOTC2
MLOS1 MLOTC1
RDEN MLOMC
Channel Control Register (WRITE/READ)
LENG31 LENG32 LENG33 LENG34 LENG35 LENG36 LENG37
LENG21 LENG22 LENG23 LENG24 LENG25 LENG26 LENG27
LENG11 LENG12 LENG13 LENG14 LENG15 LENG16 LENG17
RLOOP1 RLOOP2 RLOOP3 RLOOP4 RLOOP5 RLOOP6 RLOOP7
LLOOP1 LLOOP2 LLOOP3 LLOOP4 LLOOP5 LLOOP6 LLOOP7
POLN1 POLN2 POLN3 POLN4 POLN5 POLN6 POLN7
MSK1 MSK2 MSK3 MSK4 MSK5 MSK6 MSK7
*Other address reserved.
Initial value *"<>" show name. Address A0-A3 should input AD0-AD3 pins.
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[AK2546]
STATUS REGISTER Symbol
LOSx (x=1 LOTCx (x=1 LOMC
Description
Loss signal alarm channel Read only register. When loss signal detected, LOSx High. Loss TCLK alarm channel Read only register. When loss TCLKx detected, LOTCx High. Loss MCLK alarm. Read only register. When loss MCLK detected, LOMC High.
MASK CONTROL Symbol
MLOSx (x=1
Description Mask loss signal alarm channel MLOSx active-high prevent LOSx from setting output "high". possible read LOSx register regardless status MLOSx. Initial value "high". Mask loss TCLK alarm channel MLOTCx active-high prevent LOTCx from setting output "high". possible read LOTCx register regardless status MLOTCx. Initial value "high". Mask loss MCLK alarm. MLOMC active-high prevent LOMC from setting output "high". possible read LOMC register regardless status MLOMC. Initial value "high". When loss MCLK detected, LOSx register LOSx pins "high" same time. Therefore MLOSx register must "high" prevent loss MCLK from setting output. this case, LOMC read.
MLOTCx (x=1
MLOMC
CHANNEL CONTROL REGISTER Symbol
LENGyx
Description
RLOOPx/ LLOOPx POLNx
MSKx RDEN
generated transmit pulse channel provides appropriate pulse shape line length from DSX-1 cross connect through setting this register shown below Table Loopback mode channel activated through setting these registers shown below Table This register shown Table controls TIPx/RINGx output polarity. Initial value "high". active-high corresponding transceiver power down mode. impedance between TTIP TRING 30k(typ). LOSx goes "high" power down mode. Initial value "high". MSKx active-high prevent LOSx LOTCx from setting output "high". Initial value "high". RDEN active-high prevent RCLK, RPOS, RNEG output from forcing "low" "high" detection Loss signal. Initial value "low".
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[AK2546]
Table Pulse Shape Control
LENG3x LENG2x LENG1x Line Length 0-133feet (Initial Value) 133-266feet 266-399feet 399-533feet 533-655feet
Table Loopback mode Select
RLOOPx LLOOPx Normal Local Loop back Remote Loop back Inhibited Function (Initial value)
Table TIPx/RINGx Polarity Control
POLNx POSx/NEGx TIPx/RINGx space mark mark space
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[AK2546]
OUTPUT CONTROL
don't care LOS: LOSx output LOSx register
Reset, Loss MCLK, Power down
RESET MCLK Loopback Local Remot loss loss clocked clocked 0(Note 0(Note 0(Note POLN RDEN TCLK Receive signal TTIP TRING RCLK RPOS RNEG
Normal Operation(RESET=1, MCLK: Clocked, PD=0)
Loopback Local Remote clocked POLN RDEN TCLK Receive signal TTIP TRING TPOS TNEG clocked loss TPOS TNEG loss RCLK RTIP RRING loss clocked loss loss TPOS TNEG loss loss RCLK RCLK RTIP RRING RTIP RRING clocked TPOS TNEG clocked loss TPOS TNEG loss RCLK RTIP RRING loss clocked loss loss TPOS TNEG loss loss RCLK RCLK RTIP RRING RTIP RRING RCLK RTIP RRING RCLK RCLK RPOS RNEG RTIP RRING
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[AK2546]
Remote Loopback(RESET=1, MCLK: Clocked, PD=0)
Loopback Local Remote POLN RDEN TCLK Receive signal RRING RTIP loss RRING RTIP loss RRING RTIP RRING RTIIP loss RRING RTIP loss RRING RCLK RRING RTIP RCLK RRING RCLK RRING RTIP RTIP TTIP TRING RTIP RCLK RRING RCLK RPOS RNEG RTIP
Local Loopback(RESET=1, MCLK: Clocked, PD=0)
Loopback Local Remote clocked POLN RDEN TCLK Receive signal TTIP TRING TPOS TNEG clocked loss TPOS TNEG loss loss clocked loss TPOS TNEG clocked loss TPOS TNEG loss loss loss TCLK (Note TCLK (Note TCLK (Note TCLK (Note RCLK RPOS RNEG TPOS TNEG TPOS TNEG TPOS TNEG TPOS TNEG
Note impedance between TTIP TRING 30k(typ). Note phase TCLK satisfies receive output timing.
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ASAHI KASEI THEORY OPERATION
[AK2546]
Loss signal Loss signal channel reported setting LOSx register "high". receiver will indicate loss signal upon receiving consecutive zeros detecting input level being below threshold (ALOS). LOSx returns "low" when received signal returns 12.5% ones density including consecutive zeros. (GR-820)
When Loss Signal detected channel LOSx register "high" LOSx becomes "high". When LOSx "high", interrupt will issued MLOSx "low". LOSx becomes high regardless MLOSx status. MLOSx active-high masks LOSx interrupt. LOSx registers LOSx pins represent current status received signal regardless MLOSx status.
Loss TCLK Loss TCLKx reported setting LOTCx "high". When LOTCx "high", output becomes "high" MLOTCx "low". MLOTCx active-high masks LOTCx interrupt. LOTCx represents current status TCLKx read regardless MLOTCx status. When Loss TCLKx detected, TTIPx/TRINGx will forced "0". Loss MCLK Loss MCLK reported setting LOMC "high". When LOMC "high", output becomes "high" MLOMC "low". MLOMC active-high masks LOMC interrupt. LOMC represents current status MCLK read regardless MLOMC status. When loss MCLK detected, LOSx register LOSx goes "high" same time. Therefore MLOSx register must "high" prevent loss MCLK from setting output output output becomes "high" when alarm reported LOSx, LOTCx LOMC registers. This masked MLOSx, MLOTCx MLOMC registers. Local Loopback Local Loopback mode, TPOSx, TNEGx, TCLKx signals looped back RPOSx, RNEGx, RCLKx output. RTIPx, RRINGx inputs ignored loss signal detection active. transmitter channel outputs TTIPx, TRINGx normally. Remote Loopback Remote Loopback mode, RTIPx/RRINGx signals looped back TTIPx/TRINGx output. receiver channel output RPOSx, RNEGx, RCLKx normally detect loss signal. TPOSx, TNEGx, TCLKx inputs ignored.
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[AK2546]
RECOMMENDED EXTERNAL CIRCUIT
Transmit Circuit
AK2546 TTIPx
TRINGx C1=0.47µF
Received Circuit
AK2546 RTIPx RRINGx 2CT:1
R1=R2=68 R3=R4=130
Recommended Transformer Specification Turns Primary Leakage Ratio Inductance Inductance (Typ) (Min) (Max)
1:2CT 720µH 720µH 0.3µH 0.3µH
Interwinding Capacitance (Max) 30pF 30pF
(Max)
Recommended Transformers Selection Turns Ratio Manufacturer Part Number 1:2CT* WBTT-0425 Pulse Engineering T1105, T1106 4101
Description Single, SMT,1.5kV Octal, SMT,1.5kV Single, SMT,1.5kV
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[AK2546]
Reference current circuit
determine input reference current, connect 12k±1% resistor. AK2546 BGREF
R1=12k±1%
Power Supply
attenuate power supply noise, connect capacitors between respectively. value capacitance AK2546 need depend condition power supply line. Please decide value capacitance after your evaluation.
AK2546
name RAVDD1-RAVSS1, RAVDD2-RAVSS2, BVDD-BVSS, TAVDD1-TAVSS1, TAVDD2-TAVSS2 TVDD1-TVSS1, TVDD2-TVSS2, TVDD3-TVSS3, TVDD4-TVSS4, TVDD5-TVSS5, IOVDD1-IOVSS1, TVDD6-TVSS6, IOVDD2-IOVSS2, TVDD7-TVSS7, DVDD1-DVSS1,
0.01µF
DVDD2-DVSS2, PVDD-PVSS
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[AK2546]
Recommended conditions board
performance noise heat, board design must taken care. Recommended conditions board shown below. Recommended conditions: Multilayerboard with more than layer Please design rest pattern
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[AK2546]
PACKAGE
144pin
LQFP
OUTPUT DIMENSIONS
22.0 20.0
AK2546 XXXXXXX JAPAN
20.0 0.17±0.040.07
1.70 1.40
0.50 0.20
0.10
22.0
0.10
0.10 0.50±0.1
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[AK2546]
IMPORTANT NOTICE These products their specifications subject change without notice. Before considering
application, consult Asahi Kasei Microsystems Co., Ltd. (AKM) sales office authorized distributor concerning their current status. assumes liability infringement patent, intellectual property, other right application information contained herein. export these products, devices systems containing them, require export license other official approval under regulations country export pertaining customs tariffs, currency exchange, strategic materials. products neither intended authorized critical components safety, life support, other hazard related device system, assumes responsibility relating such use, except with express written consent Representative Director AKM. used here: hazard related device system designed intended life support maintenance safety applications medicine, aerospace, nuclear energy, other fields, which failure function perform reasonably expected result loss life significant injury damage person property. critical component whose failure function perform reasonably expected result, whether directly indirectly, loss safety effectiveness device system containing which must therefore meet very high standards performance reliability. responsibility buyer distributor product distributes, disposes otherwise places product with third party notify that party advance above content conditions, buyer distributor agrees assume responsibility liability hold harmless from claims arising from said product absence such notification.
<C0019-E-02>
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AK2546 channel Transceiver FEATURE short haul transceiver Jitter

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