This article originally published 1994. REDUCE DRAM MEMORY COSTS

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This article originally published 1994. REDUCE DRAM MEMORY COSTS

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TN-04-32 REDUCE DRAM MEMORY COSTS WITH CACHE
This article originally published 1994.
REDUCE DRAM MEMORY COSTS WITH CACHE
DRAM SPEED
Prior employment cache memory, DRAM speed significant effect microprocessor's performance generally considered bottleneck system performance. Figure depicts historical performance increases obtained DRAM speed improved from 120ns 80ns. analysis assumes microprocessor cache), external cache 10ns buffer/trace delay. DRAM speed grade improvements generally provided significant microprocessor performance enhancements. This generated demand faster DRAMs warranted extra premium being charged them. With introduction primary (L1) secondary (L2) cache memory, number microprocessor accesses DRAM main memory been significantly reduced, seen Figure microprocessor with internal (L1) cache will generally require percent memory accesses microprocessor access either cache memory DRAM main memory. With addition cache memory, just four percent memory accesses required slower DRAM main memory.
INTRODUCTION
sold today (x486 above) have cache memory, usually both internal processor (L1) external processor (L2). intended purpose cache memory minimize number wait-states DRAMbased main memory imposes microprocessor. other words, cache memory improves speed microprocessor accesses because significantly faster than DRAM-based main memory. Today, performance DRAM-based main memory nearly important microprocessor accesses before cache memories-a side benefit incorporating cache that generally overlooked. Cache used during most microprocessor accesses percent accesses). When cache memory accessed, DRAM-based main memory accessed. This means DRAM-based main memory accessed microprocessor small percentage time. This dramatic shift from previous generations systems that incorporate cache memory. performance factors DRAM which dramatically improve when usage rate DRAM reduced speed soft error rates (SER).
Performance Improvement Over 120ns DRAM
Microprocessor Access Allocation
120ns 100n 80ns 120ns 100n
Cache Cache
Cache Memory
Cache Memory Main emory
80ns
120ns 100n
80ns
Figure HISTORICAL DRAM MEMORY PERFORMANCE
TN-04-32 DT32.p65 Rev. 2/99
Figure MICROPROCESSOR ACCESS ALLOCATION
Micron Technology, Inc., reserves right change products specifications without notice. ©1999, Micron Technology, Inc. Micron registered trademark Micron Technology, Inc.
TN-04-32 REDUCE DRAM MEMORY COSTS WITH CACHE
With only four percent memory accesses going DRAM main memory, microprocessor performance improvements obtained using today's faster DRAMs greatly minimized, seen Figure example, utilizing 50ns DRAMs 486-based with cache both caches obtaining percent rate, microprocessor's performance would improved less than percent over employment 70ns DRAMs. Excluding cache memory effects, more in-depth look into DRAM's speed performance reveals that perceived advantages faster DRAMs are, part, diminished nature data being clocked. faster DRAM speed does affect microprocessor's performance unless eliminate wait-state, demonstrated Figure should noted that faster tRAC (sufficiently fast enough eliminate wait state) only improves microprocessor's burst performance clock best; whereas sufficiently faster improves microprocessor's burst performance three clocks. Thus, impetus behind growing demand DRAMs (see technical note TN-04-29, "Maximizing Advantages System Level"). prudent system designer generally deliver best price/performance ratio using 70ns DRAMs rather than speed premiums 60ns DRAMs. With today's computing architectures, should assume faster DRAM equates noticeable microprocessor performance improvement.
MULTIPLE-CLOCKED MICROPROCESSORS
worth noting that previous analysis based non-multiple-clocked microprocessors. That microprocessors which data clocking same rate microprocessor. performance effects DRAM more pronounced multiple-clocked microprocessors. Although percentage DRAM main memory accesses remains same, amount time DRAM access slows microprocessor longer one-to-one ratio multiple microprocessor clocks. This ratio different because each wait-state external memory imposes microprocessor equates several clocks microprocessor (e.g., three clocks triple-clocked microprocessor). typical system with cache (assume each have percent rate) will retain percent memory accesses internal microprocessor (L1) direct remaining external memory. this, percent external memory accesses percent total memory accesses) secondary cache. remaining memory accesses percent total memory accesses) DRAM memory. multiple-clocked microprocessor-based system, cache DRAM memory accesses will require higher percentage execution time since each external clock translates multiple microprocessor's internal clocks.
Performance Improvement Over 70ns DRAM
Cache Cache
70ns 60ns 50ns 70ns 60ns 50ns 70ns 60ns 50ns
70ns 60ns 50ns
Figure DRAM MEMORY PERFORMANCE
TN-04-32 DT32.p65 Rev. 2/99
Micron Technology, Inc., reserves right change products specifications without notice. ©1999, Micron Technology, Inc.
TN-04-32 REDUCE DRAM MEMORY COSTS WITH CACHE
Burst Rate x-y-y-y
Number Clocks
RAS# Leadoff ('x') Burst Rate ('y')
70ns 60ns 50ns 70ns 60ns 50ns 70ns 60ns
50ns
70ns
60ns
50ns
Figure DRAM SPEED CLOCKS
difference between DX4-486 microprocessor external clock, internal clock) MHz, DX-486 when using 50ns 70ns DRAMs evaluated Table This analysis shows that clocked-multiplied microprocessors more demand external memories. example, 70ns DRAMs require percent memory accessing time with typical MHz, 486DX, clocktripled MHz, 486DX4 requires percent memory accessing time. Even with this additional demand DRAM memory performance, performance improvement obtained from using 50ns DRAM over 70ns negligible. 50ns DRAM only improves leadoff cycle (i.e., clock fails improve burst rate).
Table EFFECTS MULTIPLE-CLOCKED MICROPROCESSORS
Memory Type MHz-486DX Percent accesses Clocks burst Clocks seen Time allocation burst Time allocation burst MHz-486DX4 Percent accesses Clocks burst Clocks seen Time allocation burst Time allocation burst
TN-04-32 DT32.p65 Rev. 2/99
L1-Cache (2-1-1-1) 76.3% (2-1-1-1) 52.5%
L2-Cache (2-1-1-1) 15.3% 15.3% (2-1-1-1) 31.5%
70ns DRAMs (5-2-2-2) 8.4% (5-2-2-2)
50ns DRAMs (4-2-2-2) 7.7% (4-2-2-2)
Micron Technology, Inc., reserves right change products specifications without notice. ©1999, Micron Technology, Inc.
TN-04-32 REDUCE DRAM MEMORY COSTS WITH CACHE
PERIPHERAL COMPONENTS
Besides microprocessor accesses, DRAM memory accessed peripheral components. Non-cached peripheral components access DRAM main memory over either local bus. previously discussed, even without cache memory, faster DRAMs necessarily equate increased performance. Figure depicts leadoff page mode cycles today's faster DRAMs while being accessed peripheral components over either local bus. DRAM speed improves, burst rate does improve since speed improvement sufficient enough reduce number clocks required. speeds used, burst rate already clock. most cases leadoff cycle does change between speed versions either. only improvement DRAM memory accesses peripheral components obtained when using 50ns DRAMs over slower DRAMs MHz. Additionally, main memory accesses peripheral components typically long streams data (i.e., page mode) which minimizes improved leadoff time obtained from faster DRAMs. example, assume burst words. 50ns DRAM-based main memory would only percent faster than using 70ns DRAMs local bus. Such negligible performance increase makes difficult justify speed premiums associated with fast DRAMs. parity detail provides system designers with information needed answer this question. However, worth noting that when cache memory utilized, DRAM accessed only four percent time. This leaves DRAM main memory standby mode remainder time. mentioned same technical note, highly dependent DRAM cycle rate. DRAM less susceptible soft errors approximately factor 20x) when standby mode (only refresh cycles) than when being accessed fast cycle rate. Figure depicts typical 32-bit-wide, 4MB, DRAMbased main memory's mean time between failures (MTBF) over various utilization rates (READ/WRITE accesses 200ns). example, system with cache memories obtaining percent rate percent percent cache memory rates), designers expect DRAM soft error during years continuous use, because sees only four percent utilization rate. same DRAM memory would experience DRAM soft error every years only cache percent rate percent utilization rate) employed. other extreme, same DRAM memory non-cached cache memory) system would percent utilization rate. These conditions would result approximately DRAM soft error every years.
DRAM SOFT ERRORS
There been much discussion regarding DRAM soft error rate (SER), with common question being: need parity?" previous technical note, TN-04-28, "DRAM Soft Error Rate Calculations," (1Q94), discusses issue
SUMMARY
addition cache memory only achieves objective minimizing microprocessor wait states, also demands less DRAM main memory. With cache memory, need faster DRAMs parity memory eliminated most designs.
Number Clocks
RAS# Leadoff ('x')
Burst Rate ('y')
Years Fail
70ns 60ns 50ns 70ns 60ns 50ns 70ns
60ns 50ns
READ/WRITE
cess Time Alloc
ation
Figure DRAM SPEED LOCAL/ISA ACCESSES
TN-04-32 DT32.p65 Rev. 2/99
Figure DRAM MTBF SOFT ERRORS ACCESS RATE
Micron Technology, Inc., reserves right change products specifications without notice. ©1999, Micron Technology, Inc.

This article originally published 1994. REDUCE DRAM MEMORY COSTS

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