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HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM

PRELIMINARY IDT70V07S / L

HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM
Features
PRELIMINARY IDT70V07S / L
Description
The IDT70V07 is a high-speed 32K x 8 Dual-Port Static RAM. The IDT70V07 is designed to be used as a stand-alone 256K-bit Dual-Port RAM or as a combination MASTER / SLAVE Dual-Port RAM for 16-bitor-more word systems. Using the IDT MASTER / SLAVE Dual-Port RAM approach in 16-bit or wider memory system applications results in full-speed, error-free operation without the need for additional
Functional Block Diagram
I / O0L- I / O7L I / O Control BUSYL A14L A0L
I / O Control
I / O0R-I / O7R
BUSYR Address Decoder
MEMORY ARRAY
Address Decoder
A14R A0R
ARBITRATION INTERRUPT SEMAPHORE LOGIC
SEML (2) INTL
NOTES: 1. (MASTER): BUSY is output (SLAVE): BUSY is input. 2. BUSY and INT outputs are non-tri-stated push-pull.
SEMR INTR(2)
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JUNE 1999
DSC 2943 / 5
IDT70V07S / L High-Speed 32K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
discrete logic. This device provides two independent ports with separate control, address, and I / O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by CE permits the on-chip circuitry of each port
to enter a very low standby power mode. Fabricated using IDTs CMOS high-performance technology, these devices typically operate on only 300mW of power. The IDT70V07 is packaged in a ceramic 68-pin PGA and PLCC and a 80-pin thin quad flatpack (TQFP).
Pin Configurations(1, 2, 3)
I / O1L I / O0L N / C OEL R / WL SEML CEL A14L A13L VCC A12L A11L A10L A9L A8L A7L A6L
IDT70V07J J68-1(4) 68-Pin PLCC Top View(5)
A5L A4L A3L A2L A1L A0L INTL BUSYL GND M / S BUSYR INTR A0R A1R A2R A3R A4R
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I / O7R N / C OER R / WR SEMR CER A14R A13R GND A12R A11R A10R A9R A8R A7R A6R A5R
I / O7R N / C OER R / WR SEMR CER N / C A14R A13R GND A12R A11R A10R A9R A8R A7R A6R A5R N / C N / C
NOTES: 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground. 3. J68-1 package body is approximately .95 in x .95 in x .17 in. PN80-1 package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking.
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 1 60 2 59 3 58 57 4 56 5 55 6 54 7 70V07PF 53 8 (4) PN80-1 9 52 10 51 80-Pin TQFP 50 11 (5) Top View 49 12 48 13 14 47 15 46 16 45 44 17 43 18 19 42 41 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
I / O1L I / O0L N / C OEL R / WL SEML CEL N / C A14L A13L VCC A12L A11L A10L A9L A8L A7L A6L N / C N / C
N / C A5L A4L A3L A2L A1L A0L INTL BUSYL GND , M / S BUSYR INTR A0R A1R A2R A3R A4R N / C N / C
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IDT70V07S / L High-Speed 32K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
51 11 53 A7L 55 A9L A5L 52 A6L 54 A8L 50 A4L 49 A3L 48 A2L 47 A1L 46 44 42 A0L BUSYL M / S 40 38 INTR A1R 36 A3R 35 A4R 32 A7R 30 A9R 28 A11R 26 GND 34 A5R 33 A6R 31 A8R 29 A10R 27 A12R
45 43 41 39 37 INTL GND BUSYR A0R A2R
57 56 A11L A10L 59 58 VCC A12L 61 60 A13L
IDT70V07G G68-1(4) 68-Pin PGA Top View(5)
24 25 A14R A13R 22 23 SEMR CER 20 OER 21 R / WR
01 A INDEX
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NOTES: 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground. 3. Package body is approximately 1.18 in x 1.18 in x .16 in. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking.
Pin Names(1, 2)
Left Port CEL R / WL OEL A 0L - A14L I / O0L - I / O7L SEML INTL BUSYL CER R / WR OER A0R - A14R I / O0R - I / O7R SEMR INTR BUSYR M / S VCC GND Right Port Chip Enable Read / Write Enable Output Enable Address Data Input / Output Semaphore Enable Interrupt Flag Busy Flag Master or Slave Select Power Ground
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Names
IDT70V07S / L High-Speed 32K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table I: Non-Contention Read / Write Control
Inputs(1) CE H L L X R / W X L H X OE X X L H SEM H H H X Outputs I / O 0-7 High-Z DATAIN DATA OUT High-Z Deselected: Power-Down Write to Memory Read Memory Outputs Disabled
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NOTE: 1. A0L A14L A0R A14R
Truth Table II: Semaphore Read / Write Control
Inputs(1) CE H H L R / W H X OE L X X SEM L L L Outputs I / O 0-7 DATA OUT DATAIN
Mode Read Data in Semaphore Flag Write I / O0 into Semaphore Flag Not Allowed
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Absolute Maximum Ratings(1)
Symbol V TERM(2) Rating Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature DC Output Current Commercial & Industrial -0.5 to +4.6 Unit V
Maximum Operating Temperature and Supply Voltage(1, 2)
Grade Commercial Ambient Temperature 0OC to +70OC -40OC to +85OC GND 0V 0V Vcc 3.3V + 0.3 3.3V + 0.3
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TBIAS TSTG IOUT
-55 to +125 -55 to +125 50
Industrial
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NOTES: 1. This is the parameter TA. 2. Industrial temperature: for specific speeds, packages and powers contact your sales office.
Recommended DC Operating Conditions(2)
Symbol VCC GND VIH VIL Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min. 3.0 0 2.0 -0.3(1) Typ. 3.3 0
Max. 3.6 0 VCC+0.3(2) 0.8
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Capacitance(1)
Symbol CIN COUT Input Capacitance
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Output Capacitance
NOTES: 1. This parameter is determined by device characterization but is not production tested. 2. 3dV represents the interpolated capacitance when the input and output signals switch from 0V to 3V or from 3V to 0V.
IDT70V07S / L High-Speed 32K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
70V07L Min.
Max. 10 10 0.4
Max. 5 5 0.4
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Output Leakage Current Output Low Voltage Output High Voltage
Max. 170 140
Max. 140 120
Unit mA
Standby Current (Both Ports - TTL Level Inputs)
Standby Current (One Port - TTL Level Inputs)
Full Standby Current (Both Ports CMOS Level Inputs)
Full Standby Current (One Port CMOS Level Inputs)
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IDT70V07S / L High-Speed 32K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
3.3V 3.3V
AC Test Conditions
Input Pulse Levels Input Rise / Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 3ns 1.5V 1.5V Figures 1 and 2
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590 DATAOUT BUSY INT 435 30pF DATAOUT 435
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Figure 1. AC Output Test Load
Figure 2. Output Test Load (for tLZ , tHZ, tWZ, tOW) Including scope and jig.
AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(4, 5)
Parameter
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Output Enable Access Time Output Hold from Address Change Output Low-Z Time (1, 2) Output High-Z Time
Chip Enable to Power Up Time
Chip Disable to Power Down Time
Semaphore Flag Update Pulse (OE or SEM) Semaphore Address Access Time
Timing of Power-Up Power-Down
CE ICC ISB
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IDT70V07S / L High-Speed 32K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of Read Cycles(5)
tRC ADDR tAA (4) tACE tAOE OE
R / W tLZ DATAOUT
tOH VALID DATA
tHZ BUSYOUT
AC Electrical Characteristics Over the Operating Temperature and Supply Voltage(5, 6)
Parameter
Address Valid to End-of-Write Address Set-up Time Write Pulse Width Write Recovery Time Data Valid to End-of-Write Output High-Z Time (1, 2) Data Hold Time (4) Write Enable to Output in High-Z(1, 2) Output Active from End-of-Write SEM Flag Write to Read Time SEM Flag Contention Window
IDT70V07S / L High-Speed 32K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R / W Controlled Timing(1, 5, 8)
tWC ADDRESS tHZ OE tAW CE or SEM
tAS (6) R / W tWZ (7) DATAOUT
tDW DATAIN
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Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1, 5)
tWC ADDRESS tAW CE or SEM
tEW(2)
tWR(3)
tDW DATAIN
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IDT70V07S / L High-Speed 32K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
tSAA A0-A2 VALID ADDRESS tAW SEM tEW tDW DATA0 tAS R / W tSWRD OE
Write Cycle
VALID ADDRESS tACE
tSOP DATAOUT VALID(2)
DATAIN VALID tWP tDH
tAOE tSOP
Read Cycle
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Timing Waveform of Semaphore Write Contention(1, 3, 4)
A0"A"-A2"A" MATCH
SEM"A" tSPS A0"B"-A2"B" MATCH
SEM"B"
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IDT70V07S / L High-Speed 32K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(6, 7)
Parameter
BUSY TIMING (M / S - VIL) tWB tWH BUSY Input to Write (4) Write Hold After BUSY
PORT-TO-PORT DELAY TIMING tWDD tDDD Write Pulse to Data Delay (1) Write Data Valid to Read Data Delay (1)
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Timing Waveform of Write with Port-to-Port Read and BUSY(2, 4, 5)
tDH VALID
MATCH tBDA tBDD
VALID
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IDT70V07S / L High-Speed 32K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with BUSY
tWP R / W"A" tWB BUSY"B" tWH
NOTES: 1. tWH must be met for both BUSY input (SLAVE) and output (MASTER). 2. BUSY is asserted on Port "B" blocking R / W"B", until BUSY"B" goes HIGH.
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Waveform of BUSY Arbitration Controlled by CE Timing(1)
ADDR"A" and "B" ADDRESSES MATCH
CE"A" tAPS CE"B" tBAC BUSY"B"
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Waveform of BUSY Arbitration Cycle Controlled by Address Match Timing(1)
ADDR"A" tAPS ADDR"B"
ADDRESS "N"
MATCHING ADDRESS "N" tBAA tBDA
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BUSY"B"
NOTES: 1. All timing is the same for left and right ports. Port A may be either the left or right port. Port B is the port opposite from Port A. 2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or the other, but there is no guarantee on which side busy will be asserted.
IDT70V07S / L High-Speed 32K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1)
Parameter
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Waveform of Interrupt Timing(1)
tWC ADDR"A" tAS CE"A"
INTERRUPT SET ADDRESS
R / W"A" tINS (3) INT"B"
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tRC ADDR"B" INTERRUPT CLEAR ADDRESS tAS (3) CE"B"
OE"B" tINR (3) INT"B"
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NOTES: 1. All timing is the same for left and right ports. Port A may be either the left or right port. Port B is the port opposite from port A. 2. See Interrupt Truth Table III. 3. Timing depends on which enable signal (CE or R / W) is asserted last. 4. Timing depends on which enable signal (CE or R / W) is de-asserted first.
IDT70V07S / L High-Speed 32K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table III Interrupt Flag(1)
Right Port R / WR X X L X CER X L L X OER X L X X A14R-A0R X 7FFF 7FFE X INTR L
Function Set Right INTR Flag Reset Right INTR Flag Set Left INTL Flag Reset Left INTL Flag
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Truth Table IV Address BUSY Arbitration
Inputs CEL X H X L CER X X H L A0L-A14L A0R-A14R NO MATCH MATCH MATCH MATCH Outputs BUSYL(1) H H H (2) BUSYR(1) H H H (2) Function Normal Normal Normal Write Inhibit(3)
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Truth Table V Example of Semaphore Procurement Sequence(1, 2, 3)
Functions No Action Left Port Writes "0" to Semaphore Right Port Writes "0" to Semaphore Left Port Writes "1" to Semaphore Left Port Writes "0" to Semaphore Right Port Writes "1" to Semaphore Left Port Writes "1" to Semaphore Right Port Writes "0" to Semaphore Right Port Writes "1" to Semaphore Left Port Writes "0" to Semaphore Left Port Writes "1" to Semaphore D0 - D7 Left 1 0 0 1 1 0 1 1 1 0 1 D0 - D7 Right 1 1 1 0 0 1 1 0 1 1 1 Semaphore free Left port has semaphore token No change. Right side has no write access to semaphore Right port obtains semaphore token No change. Left port has no write access to semaphore Left port obtains semaphore token Semaphore free Right port has semaphore token Semaphore free Left port has semaphore token Semaphore free
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Status
IDT70V07S / L High-Speed 32K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
The IDT70V07 provides two ports with separate control, address and I / O pins that permit independent access for reads or writes to any location in memory. The IDT70V07 has an automatic power down feature controlled by CE. The CE controls on-chip power down circuitry that permits the respective port to go into a standby mode when not selected (CE HIGH). When a port is enabled, access to the entire memory array is permitted.
Functional Description
programmed by tying the BUSY pins HIGH. If desired, unintended write operations can be prevented to a port by tying the BUSY pin for that port LOW. The BUSY outputs on the IDT 70V07 RAM in master mode, are push-pull type outputs and do not require pull up resistors to operate. If these RAMs are being expanded in depth, then the BUSY indication for the resulting array requires the use of an external AND gate.
DECODER
Interrupts
MASTER Dual Port RAM BUSYL
CE BUSYR
SLAVE Dual Port RAM BUSYL
CE BUSYR
Width Expansion with BUSY Logic Master / Slave Arrays
BUSYL
MASTER Dual Port RAM BUSYL
CE BUSYR
SLAVE Dual Port RAM BUSYL
CE BUSYR BUSYR
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Figure 3. Busy and chip enable routing for both width and depth expansion with IDT70V07 RAMs.
Busy Logic provides a hardware indication that both ports of the SRAM have accessed the same location at the same time. It also allows one of the two accesses to proceed and signals the other side that the SRAM is busy. The busy pin can then be used to stall the access until the operation on the other side is completed. If a write operation has been attempted from the side that receives a BUSY indication, the write signal is gated internally to prevent the write from proceeding. The use of BUSY logic is not required or desirable for all applications. In some cases it may be useful to logically OR the BUSY outputs together and use any BUSY indication as an interrupt source to flag the event of an illegal or illogical operation. If the write inhibit function of BUSY logic is not desirable, the BUSY logic can be disabled by placing the part in slave mode with the M / S pin. Once in slave mode the BUSY pin operates solely as a write inhibit input pin. Normal operation can be
Busy Logic
The IDT70V07 is an extremely fast Dual-Port 32K x 8 CMOS Static RAM with an additional 8 address locations dedicated to binary semaphore flags. These flags allow either processor on the left or right side of the Dual-Port SRAM to claim a privilege over the other processor for functions defined by the system designers software. As an example, the semaphore can be used by one processor to inhibit the other from accessing a portion of the Dual-Port SRAM or any other shared resource. The Dual-Port SRAM features a fast access time, and both ports are completely independent of each other. This means that the activity on the left port in no way slows the access time of the right port. Both ports are identical in function to standard CMOS Static RAM and can be read from, or written to, at the same time with the only possible conflict arising from the simultaneous writing of, or a simultaneous READ / WRITE of, a non-semaphore location. Semaphores are protected against such ambiguous situations and may be used by the system program to avoid any conflicts in the non-semaphore portion of the Dual-Port SRAM. These devices have an automatic powerdown feature controlled by CE, the Dual-Port SRAM enable, and SEM, the semaphore enable. The CE and SEM pins control on-chip power down circuitry that permits the respective port to go into standby mode when not selected. This is the condition which is shown in Truth Table
Semaphores
IDT70V07S / L High-Speed 32K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
semaphore flags useful in interprocessor communications. (A thorough discussion on the use of this feature follows shortly.) A zero written into the same location from the other side will be stored in the
L PORT SEMAPHORE REQUEST FLIP FLOP D0 WRITE SEMAPHORE READ
Figure 4. IDT70V07 Semaphore Logic
R PORT SEMAPHORE REQUEST FLIP FLOP
D0 WRITE
SEMAPHORE READ
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The semaphore logic is a set of eight latches which are independent of the Dual-Port SRAM. These latches can be used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphores provide a hardware assist for a use assignment method called Token Passing Allocation. In this method, the state of a semaphore latch is used as a token indicating that shared resource is in use. If the left processor wants to use this resource, it requests the token by setting the latch. This processor then verifies its success in setting the latch by reading it. If it was successful, it proceeds to assume control over the shared resource. If it was not successful in setting the latch, it determines that the right side processor has set the latch first, has the token and is using the shared resource. The left processor can then either repeatedly request that semaphores status or remove its request for that semaphore to perform another task and occasionally attempt again to gain control of the token via the set and test sequence. Once the right side has relinquished the token, the left side should succeed in gaining control. The semaphore flags are active LOW. A token is requested by writing a zero into a semaphore latch and is released when the same side writes a one to that latch. The eight semaphore flags reside within the IDT70V07 in a separate memory space from the Dual-Port SRAM. This address space is accessed by placing a LOW input on the SEM pin (which acts as a chip select for the semaphore flags) and using the other control pins (Address, OE, and R / W) as they would be used in accessing a standard Static RAM. Each of the flags has a unique address which can be accessed by either side through address pins A0 A2. When accessing the semaphores, none of the other address pins has any effect. When writing to a semaphore, only data pin D0 is used. If a LOW level is written into an unused semaphore location, that flag will be set to a zero on that side and a one on the other side (see Truth Table V). That semaphore can now only be modified by the side showing the zero. When a one is written into the same location from the same side, the flag will be set to a one for both sides (unless a semaphore request from the other side is pending) and then can be written to by both sides. The fact that the side which is able to write a zero into a semaphore subsequently locks out writes from the other side is what makes
How the Semaphore Flags Work
IDT70V07S / L High-Speed 32K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
is written to a one. From this it is easy to understand that, if a semaphore is requested and the processor which requested it no longer needs the resource, the entire system can hang up until a one is written into that semaphore request latch. The critical case of semaphore timing is when both sides request a single token by attempting to write a zero into it at the same time. The semaphore logic is specially designed to resolve this problem. If simultaneous requests are made, the logic guarantees that only one side receives the token. If one side is earlier than the other in making the request, the first side to make the request will receive the token. If both requests arrive at the same time, the assignment will be arbitrarily made to one port or the other. One caution that should be noted when using semaphores is that semaphores alone do not guarantee that access to a resource is secure. As with any powerful programming technique, if semaphores are misused or misinterpreted, a software error can easily happen. Initialization of the semaphores is not automatic and must be handled via the initialization program at power-up. Since any semaphore request flag which contains a zero must be reset to a one, all semaphores on both sides should have a one written into them at initialization from both sides to assure that they will be free when needed.
Perhaps the simplest application of semaphores is their application as resource markers for the IDT70V07s Dual-Port SRAM. Say the 32K x 8 SRAM was to be divided into two 16K x 8 blocks which were to be dedicated at any one time to servicing either the left or right port. Semaphore 0 could be used to indicate the side which would control the lower section of memory, and Semaphore 1 could be defined as the indicator for the upper section of memory. To take a resource, in this example the lower 16K of Dual-Port SRAM, the processor on the left port could write and then read a zero in to Semaphore 0. If this task were successfully completed (a zero was read back rather than a one), the left processor would assume control of the lower 16K. Meanwhile the right processor was attempting to gain control of the resource after the left processor, it would read back a one in response to the zero it had attempted to write into Semaphore 0. At this point, the software could choose to try and gain control of the second 16K section by writing, then reading a zero into
Using SemaphoresSome Examples
Semaphore 1. If it succeeded in gaining control, it would lock out the left side. Once the left side was finished with its task, it would write a one to Semaphore 0 and may then try to gain access to Semaphore 1. If Semaphore 1 was still occupied by the right side, the left side could undo its semaphore request and perform other tasks until it was able to write, then read a zero into Semaphore 1. If the right processor performs a similar task with Semaphore 0, this protocol would allow the two processors to swap 16K blocks of Dual-Port SRAM with each other. The blocks do not have to be any particular size and can even be variable, depending upon the complexity of the software using the semaphore flags. All eight semaphores could be used to divide the Dual-Port SRAM or other shared resources into eight parts. Semaphores can even be assigned different meanings on different sides rather than being given a common meaning as was shown in the example above. Semaphores are a useful form of arbitration in systems like disk interfaces where the CPU must be locked out of a section of memory during a transfer and the I / O device cannot tolerate any wait states. With the use of semaphores, once the two devices has determined which memory area was off-limits to the CPU, both the CPU and the I / O devices could access their assigned portions of memory continuously without any wait states. Semaphores are also useful in applications where no memory WAIT state is available on one or both sides. Once a semaphore handshake has been performed, both processors can access their assigned SRAM segments at full speed. Another application is in the area of complex data structures. In this case, block arbitration is very important. For this application one processor may be responsible for building and updating a data structure. The other processor then reads and interprets that data structure. If the interpreting processor reads an incomplete data structure, a major error condition may exist. Therefore, some sort of arbitration must be used between the two different processors. The building processor arbitrates for the block, locks it and then is able to go in and update the data structure. When the update is completed, the data structure block is released. This allows the interpreting processor to come back and read the complete data structure, thereby guaranteeing a consistent data structure.
IDT70V07S / L High-Speed 32K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Ordering Information
IDT XXXXX Device Type A Power 999 Speed A Package A Process / Temperature Range Blank I(1) Commercial (0°C to +70°C) Industrial (-40°C to +85°C)
80-pin TQFP (PN80-1) 68-pin PGA (G68-1) 68-pin PLCC (J68-1)
Commercial Only Commercial Only Commercial Only
Speed in nanoseconds
Standard Power Low Power
70V07 256K (32K x 8) 3.3V Dual-Port RAM
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NOTE: 1. Industrial temperature range is available. For specific speeds, packages and powers contact your sales office.
Preliminary Datasheet:
Datasheet Document History:
3 / 24 / 99: Initiated datasheet document history Converted to new format Cosmetic and typographical corrections Page 2 and 3 Added additional notes to pin configurations Changed drawing format
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