PRELIMINARY IDT70V07S/L True Dual-Ported memory cells which allow

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PRELIMINARY IDT70V07S/L True Dual-Ported memory cells which allow

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HIGH-SPEED 3.3V DUAL-PORT STATIC
PRELIMINARY IDT70V07S/L
True Dual-Ported memory cells which allow simultaneous access same memory location High-speed access Commercial: 25/35/55ns (max.) Low-power operation IDT70V07S Active: 300mW (typ.) Standby: 3.3mW (typ.) IDT70V07L Active: 300mW (typ.) Standby: 660µW (typ.) IDT70V07 easily expands data width bits more using Master/Slave select when cascading more than device BUSY output flag Master BUSY input Slave
Interrupt Flag On-chip port arbitration logic Full on-chip hardware support semaphore signaling between ports Fully asynchronous operation from either port TTL-compatible, single 3.3V (±0.3V) power supply Available 68-pin PLCC, 80-pin TQFP
Description
IDT70V07 high-speed Dual-Port Static RAM. IDT70V07 designed used stand-alone 256K-bit Dual-Port combination MASTER/SLAVE Dual-Port 16-bitor-more word systems. Using MASTER/SLAVE Dual-Port approach 16-bit wider memory system applications results full-speed, error-free operation without need additional
Functional Block Diagram
R/WL R/WR
I/O0L- I/O7L Control BUSYL A14L
(1,2)
Control
I/O0R-I/O7R
BUSYR Address Decoder
(1,2)
MEMORY ARRAY
Address Decoder
A14R
R/WL
ARBITRATION INTERRUPT SEMAPHORE LOGIC
R/WR
SEML INTL
NOTES: (MASTER): BUSY output; (SLAVE): BUSY input. BUSY outputs non-tri-stated push-pull.
SEMR INTR(2)
2943
JUNE 1999
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©1998 Integrated Device Technology, Inc.
IDT70V07S/L High-Speed Dual-Port Static
Industrial Commercial Temperature Ranges
discrete logic. This device provides independent ports with separate control, address, pins that permit independent, asynchronous access reads writes location memory. automatic power down feature controlled permits on-chip circuitry each port
enter very standby power mode. Fabricated using IDTs CMOS high-performance technology, these devices typically operate only 300mW power. IDT70V07 packaged ceramic 68-pin PLCC 80-pin thin quad flatpack (TQFP).
Configurations(1,2,3)
INDEX I/O2L I/O3L I/O4L I/O5L I/O6L I/O7L I/O0R I/O1R I/O2R I/O3R I/O4R I/O5R I/O6R
I/O1L I/O0L R/WL SEML A14L A13L A12L A11L A10L
IDT70V07J J68-1(4) 68-Pin PLCC View(5)
INTL BUSYL BUSYR INTR
2943
I/O7R R/WR SEMR A14R A13R A12R A11R A10R
INDEX I/O2L I/O3L I/O4L I/O5L I/O6L I/O7L I/O0R I/O1R I/O2R I/O3R I/O4R I/O5R I/O6R
I/O7R R/WR SEMR A14R A13R A12R A11R A10R
NOTES: pins must connected power supply. pins must connected ground. J68-1 package body approximately PN80-1 package body approximately 14mm 14mm 1.4mm. This package code used reference package diagram. This text does indicate orientation actual part-marking.
70V07PF PN80-1 80-Pin TQFP View
I/O1L I/O0L R/WL SEML A14L A13L A12L A11L A10L
INTL BUSYL BUSYR INTR
2943
IDT70V07S/L High-Speed Dual-Port Static
Industrial Commercial Temperature Ranges
Configurations(1,2,3) (con't.)
BUSYL INTR A11R A10R A12R
INTL BUSYR
A11L A10L A12L A13L
IDT70V07G G68-1(4) 68-Pin View(5)
A14L
SEML R/WL I/O0L I/O1L I/O2L I/O4L I/O3L I/O5L
A14R A13R SEMR R/WR
I/O7L I/O1R I/O4R I/O6L I/O0R I/O2R I/O3R I/O5R
I/O7R I/O6R
INDEX
2943
NOTES: pins must connected power supply. pins must connected ground. Package body approximately 1.18 1.18 This package code used reference package diagram. This text does indicate orientation actual part-marking.
Names(1,2)
Left Port R/WL A14L I/O0L I/O7L SEML INTL BUSYL R/WR A14R I/O0R I/O7R SEMR INTR BUSYR Right Port Chip Enable Read/Write Enable Output Enable Address Data Input/Output Semaphore Enable Interrupt Flag Busy Flag Master Slave Select Power Ground
2943
Names
IDT70V07S/L High-Speed Dual-Port Static
Industrial Commercial Temperature Ranges
Truth Table Non-Contention Read/Write Control
Inputs(1) Outputs High-Z DATAIN DATA High-Z Deselected: Power-Down Write Memory Read Memory Outputs Disabled
2943
Mode
NOTE: A14L A14R
Truth Table Semaphore Read/Write Control
Inputs(1) Outputs DATA DATAIN
Mode Read Data Semaphore Flag Write I/O0 into Semaphore Flag Allowed
2943
NOTE: There eight semaphore flags written I/O0 read from I/O's (I/O0-I/O7). These eight semaphores addressed A0-A2
Absolute Maximum Ratings(1)
Symbol TERM(2) Rating Terminal Voltage with Respect Temperature Under Bias Storage Temperature Output Current Commercial Industrial -0.5 +4.6 Unit
Maximum Operating Temperature Supply Voltage(1,2)
Grade Commercial Ambient Temperature +70OC -40OC +85OC 3.3V 3.3V
2943
TBIAS TSTG IOUT
+125 +125
Industrial
2943
NOTES: This parameter Industrial temperature: specific speeds, packages powers contact your sales office.
NOTES: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. VTERM must exceed 0.3V more than cycle time 10ns maximum, limited 20mA period VTERM 0.3V.
Recommended Operating Conditions(2)
Symbol Parameter Supply Voltage Ground Input High Voltage Input Voltage Min. -0.3(1) Typ.
Max. VCC+0.3(2)
Unit
2943
Capacitance(1)
Symbol COUT Input Capacitance
+25°C, 1.0MHz) TQFP Only
Parameter Conditions Max. Unit
2943
Output Capacitance
NOTES: -1.5V pulse width less than 10ns. VTERM must exceed 0.3V.
NOTES: This parameter determined device characterization production tested. represents interpolated capacitance when input output signals switch from from
IDT70V07S/L High-Speed Dual-Port Static
Industrial Commercial Temperature Ranges
Electrical Characteristics Over Operating Temperature Supply Voltage Range (VCC 3.3V 0.3V)
70V07S Symbol |ILI| |ILO| Parameter Input Leakage Current
70V07L Min.
Test Conditions 3.6V, VIH, VOUT +4mA -4mA
Min.
Max.
Max.
Unit
2943
Output Leakage Current Output Voltage Output High Voltage
NOTE: 2.0V, input leakages undefined.
Electrical Characteristics Over Operating Temperature Supply Voltage Range(1,6) (VCC 3.3V 0.3V)
70V07X25 Com'l Only Symbol Parameter Dynamic Operating Current (Both Ports Active) Test Condition VIL, Outputs Open fMAX(3) Version COM'L COM'L COM'L COM'L COM'L Typ.
70V07X35 Com'l Only Typ.
70V07X55 Com'l Only Typ.(2)
Max.
Max.
Max.
Unit
ISB1
Standby Current (Both Ports Level Inputs)
SEMR SEML fMAX(3)
ISB2
Standby Current (One Port Level Inputs)
CE"A" CE"B" VIH(5) Active Port Outputs Open, f=fMAX(3) SEMR SEML Both Ports 0.2V, 0.2V 0.2V, 0(4) SEMR SEML 0.2V CE"A" 0.2V CE"B" 0.2V(5) SEMR SEML 0.2V 0.2V 0.2V Active Port Outputs Open, fMAX(3)
ISB3
Full Standby Current (Both Ports CMOS Level Inputs)
ISB4
Full Standby Current (One Port CMOS Level Inputs)
NOTES: part number indicates power rating 3.3V, +25°C, production tested. ICCDC 80mA (Typ.) fMAX, address control lines (except Output Enable) cycling maximum frequency read cycle tRC, using Test Conditions" input levels means address control lines change. Port either left right port. Port opposite from port "A". Industrial temperature: specific speeds, packages powers contact your sales office.
2943
IDT70V07S/L High-Speed Dual-Port Static
Industrial Commercial Temperature Ranges
3.3V 3.3V
Test Conditions
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load 3.0V 1.5V 1.5V Figures
2943
DATAOUT BUSY 30pF DATAOUT
5pF*
2943
2943
Figure Output Test Load
Figure Output Test Load (for tHZ, tWZ, tOW) Including scope jig.
Electrical Characteristics Over Operating Temperature Supply Voltage Range(4,5)
70V07X25 Com'l Only Symbol READ CYCLE tACE tAOE tSOP tSAA Read Cycle Time Address Access Time Chip Enable Access Time
70V07X35 Com'l Only Min. Max.
70V07X55 Com'l Only Min. Max. Unit
Parameter
Min.
Max.
2943
Output Enable Access Time Output Hold from Address Change Output Low-Z Time (1,2) Output High-Z Time
(1,2)
Chip Enable Power Time
Chip Disable Power Down Time
Semaphore Flag Update Pulse SEM) Semaphore Address Access Time
NOTES: Transition measured ±200mV from Low- High-impedance voltage with Output Test Load (Figure This parameter guaranteed device characterization, production tested. access RAM, VIH. access semaphore, VIL. part number indicates power rating Industrial temperature: specific speeds, packages powers contact your sales office.
Timing Power-Up Power-Down
2943
IDT70V07S/L High-Speed Dual-Port Static
Industrial Commercial Temperature Ranges
Waveform Read Cycles(5)
ADDR tACE tAOE
DATAOUT
VALID DATA
BUSYOUT
(3,4)
2943 tBDD NOTES: Timing depends which signal asserted last, Timing depends which signal de-asserted first, tBDD delay required only cases where opposite port completing write operation same address location. simultaneous read operations BUSY relation valid output data. Start valid data depends which timing becomes effective last tAOE, tACE tBDD VIH.
Electrical Characteristics Over Operating Temperature Supply Voltage(5,6)
70V07X25 Com'l Only Symbol WRITE CYCLE tSWRD tSPS Write Cycle Time Chip Enable End-of-Write
70V07X35 Com'l Only Min. Max.
70V07X55 Com'l Only Min. Max. Unit
Parameter
Min.
Max.
Address Valid End-of-Write Address Set-up Time Write Pulse Width Write Recovery Time Data Valid End-of-Write Output High-Z Time (1,2) Data Hold Time Write Enable Output High-Z(1,2) Output Active from End-of-Write Flag Write Read Time Flag Contention Window
(1,2,4)
2943 NOTES: Transition measured ±200mV from High impedance voltage with Output Test Load (Figure This parameter guaranteed device characterization, production tested. access RAM, VIH. access semaphore, VIL. Either condition must valid entire time. specification must device supplying write data SRAM under operating conditions. Although values will vary over voltage temperature, actual will always smaller than actual tOW. part number indicates power rating Industrial temperature: specific speeds, packages powers contact your sales office.
IDT70V07S/L High-Speed Dual-Port Static
Industrial Commercial Temperature Ranges
Timing Waveform Write Cycle Controlled Timing(1,5,8)
ADDRESS
DATAOUT
DATAIN
2943
Timing Waveform Write Cycle Controlled Timing(1,5)
ADDRESS
tEW(2)
tWR(3)
DATAIN
2943
NOTES: must HIGH during address transitions. write occurs during overlap (tEW tWP) memory array writing cycle. measured from earlier R/W) going HIGH write cycle. During this period, pins output state input signals must applied. transition occurs simultaneously with after transition, outputs remain High-impedance state. Timing depends which enable signal asserted last, R/W. This parameter guaranteed device characterization, production tested. Transition measured ±200mV from steady state with Output Test Load (Figure during controlled write cycle, write pulse width must larger (tWZ allow drivers turn data placed required HIGH during controlled write cycle, this requirement does apply write pulse short specified access SRAM, VIH. access semaphore, VIL. must either condition.
IDT70V07S/L High-Speed Dual-Port Static
Industrial Commercial Temperature Ranges
Timing Waveform Semaphore Read after Write Timing, Either Side(1)
tSAA A0-A2 VALID ADDRESS DATA0 tSWRD
Write Cycle
VALID ADDRESS tACE
tSOP DATAOUT VALID(2)
DATAIN VALID
tAOE tSOP
Read Cycle
2943
NOTES: duration above timing (both write read cycle). DATAOUT VALID represents I/O's (I/O0-I/O7) equal semaphore value.
Timing Waveform Semaphore Write Contention(1,3,4)
A0"A"-A2"A" MATCH
SIDE
R/W"A"
SEM"A" tSPS A0"B"-A2"B" MATCH
SIDE
R/W"B"
SEM"B"
2943
NOTES: VIL, VIH. timing same left right ports. Port either left right port. opposite from port "A". This parameter measured from R/W"A" SEM"A" going HIGH R/WB going HIGH. tSPS satisfied, semaphore will fall positively side other, there guarantee which side will obtain flag.
IDT70V07S/L High-Speed Dual-Port Static
Industrial Commercial Temperature Ranges
Electrical Characteristics Over Operating Temperature Supply Voltage Range(6,7)
70V07X25 Com'l Only Symbol BUSY TIMING (M/S VIH) tBAA tBDA tBAC tBDC tAPS tBDD BUSY Access Time from Address BUSY Disable Time from Address BUSY Access Time from Chip Enable BUSY Disable Time from Chip Enable Arbitration Priority Set-up Time BUSY Disable Valid Data
70V07X35 Com'l Only Min. Max.
70V07X55 Com'l Only Min. Max. Unit
Parameter
Min.
Max.
BUSY TIMING (M/S VIL) BUSY Input Write Write Hold After BUSY
PORT-TO-PORT DELAY TIMING tWDD tDDD Write Pulse Data Delay Write Data Valid Read Data Delay
2943
NOTES: Port-to-port delay through cells from writing port reading port, refer "Timing Waveform Write with Port-to-Port Read BUSY". ensure that earlier ports wins. tBDD calculated parameter greater tWDD (actual) tDDD (actual). ensure that write cycle inhibited port during contention port "A". ensure that write cycle completed port after contention port "A". part numbers indicates power rating Industrial temperature: specific speeds, packages powers contact yuor sales office.
Timing Waveform Write with Port-to-Port Read BUSY(2,4,5)
ADDR"A" MATCH R/W"A" DATAIN tAPS ADDR"B" tBAA BUSY"B" tWDD DATAOUT tDDD NOTES: ensure that earlier ports wins. tAPS ignored (SLAVE). reading port. (SLAVE), then BUSY input (BUSY"A" BUSY"B" "don't care", this example). timing same left right ports. Port either left right port. Port port opposite from port "A".
VALID
MATCH tBDA tBDD
VALID
2943
IDT70V07S/L High-Speed Dual-Port Static
Industrial Commercial Temperature Ranges
Timing Waveform Write with BUSY
R/W"A" BUSY"B"
R/W"B"
NOTES: must both BUSY input (SLAVE) output (MASTER). BUSY asserted Port blocking R/W"B", until BUSY"B" goes HIGH.
2943
Waveform BUSY Arbitration Controlled Timing(1)
ADDR"A" ADDRESSES MATCH
CE"A" tAPS CE"B" tBAC BUSY"B"
2943
tBDC
Waveform BUSY Arbitration Cycle Controlled Address Match Timing(1)
ADDR"A" tAPS ADDR"B"
ADDRESS
MATCHING ADDRESS tBAA tBDA
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BUSY"B"
NOTES: timing same left right ports. Port either left right port. Port port opposite from Port tAPS satisfied, BUSY signal will asserted side other, there guarantee which side busy will asserted.
IDT70V07S/L High-Speed Dual-Port Static
Industrial Commercial Temperature Ranges
Electrical Characteristics Over Operating Temperature Supply Voltage Range(1)
70V07X25 Com'l Only Symbol INTERRUPT TIMING tINS tINR Address Set-up Time Write Recovery Time Interrupt Time Interrupt Reset Time
70V07X35 Com'l Only Min. Max.
70V07X55 Com'l Only Min. Max. Unit
Parameter
Min.
Max.
2043
NOTE: part number indicates power rating
Waveform Interrupt Timing(1)
ADDR"A" CE"A"
INTERRUPT ADDRESS
R/W"A" tINS INT"B"
2943
ADDR"B" INTERRUPT CLEAR ADDRESS CE"B"
OE"B" tINR INT"B"
2943
NOTES: timing same left right ports. Port either left right port. Port port opposite from port Interrupt Truth Table III. Timing depends which enable signal R/W) asserted last. Timing depends which enable signal R/W) de-asserted first.
IDT70V07S/L High-Speed Dual-Port Static
Industrial Commercial Temperature Ranges
Truth Table Interrupt Flag(1)
Left Port R/WL A14L-A0L 7FFF 7FFE INTL
Right Port R/WR A14R-A0R 7FFF 7FFE INTR
Function Right INTR Flag Reset Right INTR Flag Left INTL Flag Reset Left INTL Flag
2943
NOTES: Assumes BUSYL BUSYR =VIH. BUSYL VIL, then change. BUSYR VIL, then change.
Truth Table Address BUSY Arbitration
Inputs A0L-A14L A0R-A14R MATCH MATCH MATCH MATCH Outputs BUSYL(1) BUSYR(1) Function Normal Normal Normal Write Inhibit(3)
2943
NOTES: Pins BUSYL BUSYR both outputs when part configured master. Both inputs when configured slave. BUSY outputs IDT70V07 pushpull, open drain outputs. slaves BUSY input internally inhibits writes. inputs opposite port were stable prior address enable inputs this port. inputs opposite port became stable after address enable inputs this port. tAPS met, either BUSY BUSYR will result. BUSYL BUSYR outputs simultaneously. Writes left port internally ignored when BUSYL outputs driving regardless actual logic level pin. Writes right port internally ignored when BUSYR outputs driving regardless actual logic level pin.
Truth Table Example Semaphore Procurement Sequence(1,2,3)
Functions Action Left Port Writes Semaphore Right Port Writes Semaphore Left Port Writes Semaphore Left Port Writes Semaphore Right Port Writes Semaphore Left Port Writes Semaphore Right Port Writes Semaphore Right Port Writes Semaphore Left Port Writes Semaphore Left Port Writes Semaphore Left Right Semaphore free Left port semaphore token change. Right side write access semaphore Right port obtains semaphore token change. Left port write access semaphore Left port obtains semaphore token Semaphore free Right port semaphore token Semaphore free Left port semaphore token Semaphore free
2943
Status
NOTES: This table denotes sequence events only eight semaphores IDT70V07. There eight semaphore flags written I/O0 read from I/O's (I/O0 I/O7). These eight semaphores addressed -A2. VIH, access semaphores. Refer Semaphore Read/Write Control Truth Table.
IDT70V07S/L High-Speed Dual-Port Static
Industrial Commercial Temperature Ranges
IDT70V07 provides ports with separate control, address pins that permit independent access reads writes location memory. IDT70V07 automatic power down feature controlled controls on-chip power down circuitry that permits respective port into standby mode when selected HIGH). When port enabled, access entire memory array permitted.
Functional Description
programmed tying BUSY pins HIGH. desired, unintended write operations prevented port tying BUSY that port LOW. BUSY outputs 70V07 master mode, push-pull type outputs require pull resistors operate. these RAMs being expanded depth, then BUSY indication resulting array requires external gate.
user chooses interrupt function, memory location (mail message center) assigned each port. left port interrupt flag (INTL) asserted when right port writes memory location 7FFE (HEX), where write defined R/WR Truth Table III. left port clears interrupt through access address location 7FFE when VIL, "don't care". Likewise, right port interrupt flag (INTR) asserted when left port writes memory location 7FFF (HEX) clear interrupt flag (INTR), right port must read memory 7FFF location 7FFF. message bits) 7FFE 7FFF user-defined since addressable SRAM location. interrupt function used, address locations 7FFE 7FFF used mail boxes, part random access memory. Refer Truth Table interrupt operation.
DECODER
Interrupts
MASTER Dual Port BUSYL
BUSYR
SLAVE Dual Port BUSYL
BUSYR
When expanding IDT70V07 array width while using BUSY logic, master part used decide which side array will receive BUSY indication, output that indication. number slaves addressed same address range master, BUSY signal write inhibit signal. Thus IDT70V07 BUSY output part used master (M/S VIH), BUSY input part used slave (M/S VIL) shown Figure more master parts were used when expanding width, split decision could result with master indicating BUSY side array another master indicating BUSY other side array. This would inhibit write operations from port part word inhibit write operations from other port other part word. BUSY arbitration, master, based chip enable address signals only. ignores whether access read write. master/slave array, both address chip enable must valid long enough BUSY flag output from master before actual write pulse initiated with signal. Failure observe this timing result glitched internal write inhibit signal corrupted data slave.
Width Expansion with BUSY Logic Master/Slave Arrays
BUSYL
MASTER Dual Port BUSYL
BUSYR
SLAVE Dual Port BUSYL
BUSYR BUSYR
2943
Figure Busy chip enable routing both width depth expansion with IDT70V07 RAMs.
Busy Logic provides hardware indication that both ports SRAM have accessed same location same time. also allows accesses proceed signals other side that SRAM busy. busy then used stall access until operation other side completed. write operation been attempted from side that receives BUSY indication, write signal gated internally prevent write from proceeding. BUSY logic required desirable applications. some cases useful logically BUSY outputs together BUSY indication interrupt source flag event illegal illogical operation. write inhibit function BUSY logic desirable, BUSY logic disabled placing part slave mode with pin. Once slave mode BUSY operates solely write inhibit input pin. Normal operation
Busy Logic
IDT70V07 extremely fast Dual-Port CMOS Static with additional address locations dedicated binary semaphore flags. These flags allow either processor left right side Dual-Port SRAM claim privilege over other processor functions defined system designers software. example, semaphore used processor inhibit other from accessing portion Dual-Port SRAM other shared resource. Dual-Port SRAM features fast access time, both ports completely independent each other. This means that activity left port slows access time right port. Both ports identical function standard CMOS Static read from, written same time with only possible conflict arising from simultaneous writing simultaneous READ/WRITE non-semaphore location. Semaphores protected against such ambiguous situations used system program avoid conflicts non-semaphore portion Dual-Port SRAM. These devices have automatic powerdown feature controlled Dual-Port SRAM enable, SEM, semaphore enable. pins control on-chip power down circuitry that permits respective port into standby mode when selected. This condition which shown Truth Table
Semaphores
IDT70V07S/L High-Speed Dual-Port Static
Industrial Commercial Temperature Ranges
where both HIGH. Systems which best IDT70V07 contain multiple processors controllers typically very high-speed systems which software controlled software intensive. These systems benefit from performance increase offered IDT70V07's hardware semaphores, which provide lockout mechanism without requiring complex programming. Software handshaking between processors offers maximum system flexibility permitting shared resources allocated varying configurations. IDT70V07 does semaphore flags control resources through hardware, thus allowing system designer total flexibility system architecture. advantage using semaphores rather than more common methods hardware arbitration that wait states never incurred either processor. This prove major advantage very high-speed systems.
semaphore flags useful interprocessor communications. thorough discussion this feature follows shortly.) zero written into same location from other side will stored
PORT SEMAPHORE REQUEST FLIP FLOP WRITE SEMAPHORE READ
Figure IDT70V07 Semaphore Logic
PORT SEMAPHORE REQUEST FLIP FLOP
WRITE
SEMAPHORE READ
2943
semaphore logic eight latches which independent Dual-Port SRAM. These latches used pass flag, token, from port other indicate that shared resource use. semaphores provide hardware assist assignment method called Token Passing Allocation. this method, state semaphore latch used token indicating that shared resource use. left processor wants this resource, requests token setting latch. This processor then verifies success setting latch reading successful, proceeds assume control over shared resource. successful setting latch, determines that right side processor latch first, token using shared resource. left processor then either repeatedly request that semaphores status remove request that semaphore perform another task occasionally attempt again gain control token test sequence. Once right side relinquished token, left side should succeed gaining control. semaphore flags active LOW. token requested writing zero into semaphore latch released when same side writes that latch. eight semaphore flags reside within IDT70V07 separate memory space from Dual-Port SRAM. This address space accessed placing input (which acts chip select semaphore flags) using other control pins (Address, R/W) they would used accessing standard Static RAM. Each flags unique address which accessed either side through address pins When accessing semaphores, none other address pins effect. When writing semaphore, only data used. level written into unused semaphore location, that flag will zero that side other side (see Truth Table That semaphore only modified side showing zero. When written into same location from same side, flag will both sides (unless semaphore request from other side pending) then written both sides. fact that side which able write zero into semaphore subsequently locks writes from other side what makes
Semaphore Flags Work
semaphore request latch that side until semaphore freed first side. When semaphore flag read, value spread into data bits that flag that reads data bits flag containing zero reads zeros. read value latched into sides output register when that side's semaphore select (SEM) output enable (OE) signals active. This serves disallow semaphore from changing state middle read cycle write cycle from other side. Because this latch, repeated read semaphore test loop must cause either signal (SEM inactive output will never change. sequence WRITE/READ must used semaphore order guarantee that system level contention will occur. processor requests access shared resources attempting write zero into semaphore location. semaphore already use, semaphore request latch will contain zero, semaphore flag will appear one, fact which processor will verify subsequent read (see Truth Table example, assume processor writes zero left port free semaphore location. subsequent read, processor will verify that written successfully that location will assume control over resource question. Meanwhile, processor right side attempts write zero same semaphore flag will fail, will verified fact that will read from that semaphore right side during subsequent read. sequence READ/WRITE been used instead, system contention problems could have occurred during between read write cycles. important note that failed semaphore request must followed either repeated reads writing into same location. reason this easily understood looking simple logic diagram semaphore flag Figure semaphore request latches feed into semaphore flag. Whichever latch first present zero semaphore flag will force side semaphore flag other side HIGH. This condition will continue until written same semaphore request latch. Should other sides semaphore request latch have been written zero meantime, semaphore flag will flip over other side soon written into first sides request latch. second sides flag will stay until semaphore request latch
IDT70V07S/L High-Speed Dual-Port Static
Industrial Commercial Temperature Ranges
written one. From this easy understand that, semaphore requested processor which requested longer needs resource, entire system hang until written into that semaphore request latch. critical case semaphore timing when both sides request single token attempting write zero into same time. semaphore logic specially designed resolve this problem. simultaneous requests made, logic guarantees that only side receives token. side earlier than other making request, first side make request will receive token. both requests arrive same time, assignment will arbitrarily made port other. caution that should noted when using semaphores that semaphores alone guarantee that access resource secure. with powerful programming technique, semaphores misused misinterpreted, software error easily happen. Initialization semaphores automatic must handled initialization program power-up. Since semaphore request flag which contains zero must reset one, semaphores both sides should have written into them initialization from both sides assure that they will free when needed.
Perhaps simplest application semaphores their application resource markers IDT70V07s Dual-Port SRAM. SRAM divided into blocks which were dedicated time servicing either left right port. Semaphore could used indicate side which would control lower section memory, Semaphore could defined indicator upper section memory. take resource, this example lower Dual-Port SRAM, processor left port could write then read zero Semaphore this task were successfully completed zero read back rather than one), left processor would assume control lower 16K. Meanwhile right processor attempting gain control resource after left processor, would read back response zero attempted write into Semaphore this point, software could choose gain control second section writing, then reading zero into
Using SemaphoresSome Examples
Semaphore succeeded gaining control, would lock left side. Once left side finished with task, would write Semaphore then gain access Semaphore Semaphore still occupied right side, left side could undo semaphore request perform other tasks until able write, then read zero into Semaphore right processor performs similar task with Semaphore this protocol would allow processors swap blocks Dual-Port SRAM with each other. blocks have particular size even variable, depending upon complexity software using semaphore flags. eight semaphores could used divide Dual-Port SRAM other shared resources into eight parts. Semaphores even assigned different meanings different sides rather than being given common meaning shown example above. Semaphores useful form arbitration systems like disk interfaces where must locked section memory during transfer device cannot tolerate wait states. With semaphores, once devices determined which memory area off-limits CPU, both devices could access their assigned portions memory continuously without wait states. Semaphores also useful applications where memory WAIT state available both sides. Once semaphore handshake been performed, both processors access their assigned SRAM segments full speed. Another application area complex data structures. this case, block arbitration very important. this application processor responsible building updating data structure. other processor then reads interprets that data structure. interpreting processor reads incomplete data structure, major error condition exist. Therefore, some sort arbitration must used between different processors. building processor arbitrates block, locks then able update data structure. When update completed, data structure block released. This allows interpreting processor come back read complete data structure, thereby guaranteeing consistent data structure.
IDT70V07S/L High-Speed Dual-Port Static
Industrial Commercial Temperature Ranges
Ordering Information
XXXXX Device Type Power Speed Package Process/ Temperature Range Blank I(1) Commercial (0°C +70°C) Industrial (-40°C +85°C)
80-pin TQFP (PN80-1) 68-pin (G68-1) 68-pin PLCC (J68-1)
Commercial Only Commercial Only Commercial Only
Speed nanoseconds
Standard Power Power
70V07 256K (32K 3.3V Dual-Port
2943
NOTE: Industrial temperature range available. specific speeds, packages powers contact your sales office.
Preliminary Datasheet:
"PRELIMINARY' datasheets contain descriptions products that early release.
Datasheet Document History:
3/24/99: Initiated datasheet document history Converted format Cosmetic typographical corrections Page Added additional notes configurations Changed drawing format
6/9/99:
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PRELIMINARY IDT70V07S/L True Dual-Ported memory cells which allow

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