PCIO PCIO chip high integration, high performance single chip sub

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PCIO PCIO chip high integration, high performance single chip sub

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STP2003QFP
PCIO
PCIO chip high integration, high performance single chip subsystem connected local bus. Using single load integrates high speed Ethernet EBus2. EBus2 generic slave (pseudo-ISA bus) which off-the-shelf peripherals connected implement rest core system. PCIO built around internal (the Channel Engine Interface). This structure PCIOs modularity. Above Channel Engine Interface, Adapter connects bus. identical ports Channel Engine Interface used each PCIO's functional units: Ethernet EBus2. Each these control status registers, data buffers core logic function.
Controller
Features
Local master/slave interface, compliant with Local Specification, Revision [1]. 10baseT (802.3) 100baseT (802.30) Ethernet, using derivative Media Access Control (MAC), with fully buffered transmit receive channels; media-independent interface (MII). Expansion interface (EBus2), supporting eight external devices four buffered slave channels. Oscillator SCSI clock, free running real-time clock. IEEE 1149.1 JTAG compliant test architecture.
following functions implemented with off-the-shelf devices, connecting directly EBus2:
PC87303 Super integrating 82077-compatible floppy controller with DMA, parallel port, P1284-compliant, with with 16C550 serial controllers with 16-byte FIFOs keyboard mouse. high performance sync/async serial ports, using Siemens SAB82532, 460.8 KBaud async, KBaud sync. compatible NVRAM, MK48T59, with alarm clock interrupt power management. EPROM flash EPROM, 8-bit wide, Mbyte, POST code. CS4231 Audio CODEC. Access control port. Auxiliary ports, power supply control, temperature sensor, frequency calibration other miscellaneous functions.
Product Summary
PCIO uses Symbios' 500, CMOS 3-layer metal technology. 0.75 micron drawn, micron effective gate length, operates volts. device packaged PQFP. signals VSS/VDD pads. PCIO cell gates bits RAM. operating frequency bus, EBus2 channel engine engine Ethernet channel 33.3 MHz. core, Media Access Control (MAC), operates MHz. Maximum power consumption PCIO watts.
Although designed specification, PCIO controller compatible with specification well. However, certain recommended features, such pseudo-split reads tighter interpretation initial latency rule implemented.
STP2003QFP
PCIO Controller
BLOCK DIAGRAM
Local
Adapter v2.1 compliant, double 64-byte write buffers 100+ Mbytes/sec peak transfer rate
Configuration Space (multi-function)
Scan Control
Ethernet Channel Engine
EBus2 Channel Engine
Ethernet Channels 2048 byte FIFO channel
EBus2 Channels byte FIFO p/channel
Media Access Control 10/100
EBus2 Interface Prog. timing Prog. priority
JTAG Figure PCIO Block Diagram EBus2
PCIO Controller
STP2003QFP
Adapter
Adapter provides bus-independent layer between channel engines bus. interface 32-bit MHz, fully compliant with Local Specification, Revision 2.0. master, capable 64-byte word) bursts. writes buffered Adapter support back back transactions. Adapter also contains Configuration Space. PCIO presents itself multi-function device: EBus2 bridge) Ethernet. Each function area configuration space.
Channel Engine Interface
Adapter contains identical Channel Engine Interface ports, each channel engine. Channel Engine Interface independent interface, resulting high level modularity design test level.
EBus2 Channel Engine
EBus2 Channel Engine interfaces standard off-the-shelf devices PCIO. eight single multi-function Intel-style 8-bit devices accommodated with minimum glue logic. Four internal engines attached these devices, buffering data streams 128-byte FIFOs each channel. standard devices PC87303 SuperIO (integrates 82077 floppy controller, dual 16C550 serial controllers keyboard mouse ECP/EPP P1284 parallel port), SAB82532 serial communications controller, CS4231 audio CODEC, MK48T59 NVRAM with alarm clock, boot PROM USC/DSC control port. EBus2 Channel Engine provides access several general purpose lines (a.k.a. AUXIO), used control miscellaneous system functions.
Ethernet Channel Engine
Ethernet Channel Engine provides buffered full duplex engine Media Access Control function based MAC. descriptor-based engine contains independent transmit receive channels, each with 2048 bytes on-chip buffering. provides Mbps CSMA/CD protocol based network interface conforming IEEE 802.3, proposed IEEE 802.30 Ethernet specifications.
Scan Control Block
Scan Control contains controller.
TYPICAL SYSTEM APPLICATION
following diagram shows possible configuration PCIO based Ultra SPARC system. connects System Controller chip other ports address, control data buses. system both EPCI slots, well board device (PCIO). Interrupt information provided chip, JTAG port provided board testing well in-circuit testing debugging U2P.
STP2003QFP
PCIO Controller
Memory Data (256+32ECC) Memory SIMMs Memory Address UPA_D0(127:0+ECC) UPA_A1(63:0+ECC) Memory Control
UPA_A0(35:0) UPA/S
Graphics
UPA_A1(35:0)
System Controller
(15:0) (24+3+P)
UPA_Ctrl
Ultra SPARC-1
SF3a Interface
DA(18+16BE) (128+16P) 512KB
Interface Interface
Adaptor Ethernet
Figure Typical System Application
PINOUT DESCRIPTION
naming conventions
names lower case, except power (VDD) ground (VSS). Active signals denoted underscore letter -"_l"- following name. Direction input (I), output (O), tri-state output (T), bidirectional (B), open drain (D). TABLE describes prefixes used name signals.
EBus2
PCIO
PCIO Controller
STP2003QFP
TABLE Signal Name Prefixes
Functional Block Ethernet EBus2 JTAG Port pci_ enet_ jtag_ Prefix
Summary
TABLE Count Summary
Section Interface Clock Oscillator Ethernet Interface EBus2 Interface Miscellaneous Test Signal Total Power/Ground Total Pins Includes analog power oscillator What Includes Full v2.0; 1BR/BG lines; interrupt lines SCSI clock oscillator interface, including transceiver management serial/nibble selection address lines, chip selects Mode pin, more interrupts, auxio JTAG port diagnostics
STP2003QFP
PCIO Controller
Pinout Function
TABLE Pinout Function
Name Interface: pins pci_ad[0] pci_ad[1] pci_ad[2] pci_ad[3] pci_ad[4] pci_ad[5] pci_ad[6] pci_ad[7] pci_ad[8] pci_ad[9] pci_ad[10] pci_ad[11] pci_ad[12] pci_ad[13] pci_ad[14] pci_ad[15] pci_ad[16] pci_ad[17] pci_ad[18] pci_ad[19] pci_ad[20] pci_ad[21] pci_ad[22] pci_ad[23] pci_ad[24] pci_ad[25] pci_ad[26] pci_ad[27] pci_ad[28] pci_ad[29] pci_ad[30] pci_ad[31] pci_c_be_l[0] pci_c_be_l[1] BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB Address/Data (LSB) Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data (MSB) Command/Byte Enable Command/Byte Enable Type Description
PCIO Controller
STP2003QFP
TABLE Pinout Function (Continued)
Name pci_c_be_l[2] pci_c_be_l[3] pci_clk pci_frame_l pci_devsel_l pci_idsel pci_irdy_l pci_trdy_l pci_stop_l pci_par pci_perr_l pci_serr_l pci_gnt_l pci_req_l pci_rst_l pci_inta_l pci_intb_l pci_intc_l pci_intd_l BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir Type PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB Description Command/Byte Enable Command/Byte Enable Clock (33.3 MHz) Frame Device Select Device Select Configuration cycle Initiator Ready Target Ready Transaction Terminator Data Parity Parity Error System Error Grant Request Reset Interrupt Request Interrupt Request Interrupt Request Interrupt Request
EBus2 Interface: pins eb_a[0] eb_a[1] eb_a[2] eb_a[3] eb_a[4] eb_a[5] eb_a[6] eb_a[7] eb_clken eb_cs_l[0] eb_cs_l[1] eb_cs_l[2] eb_cs_l[3] eb_cs_l[4] eb_cs_l[5] eb_cs_l[6] EBus2 Address (LSB) EBus2 Address EBus2 Address EBus2 Address EBus2 Address EBus2 Address EBus2 Address EBus2 Address (MSB) EBus2 Address Latch Enable (bits 23:8) EPROM Chip Select Chip Select General Purpose Chip Select Audio Codec Chip Select SuperIO Chip Select 85C30 Chip Select UltraSPARC System Controller Chip Select
STP2003QFP
PCIO Controller
TABLE Pinout Function (Continued)
Name eb_cs_l[7] eb_d[0] eb_d[1] eb_d[2] eb_d[3] eb_d[4] eb_d[5] eb_d[6] eb_d[7] eb_dack_l[0] eb_dack_l[1] eb_dack_l[2] eb_dack_l[3] eb_dreq[0] eb_dreq[1] eb_dreq[2] eb_dreq[3] eb_irq1 eb_irq2 eb_irq3 eb_irq4 eb_rd_l eb_wr_l eb_rdy eb_tcs BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir Type Description General Purpose Chip Select EBus2 Data (LSB) EBus2 Data EBus2 Data EBus2 Data EBus2 Data EBus2 Data EBus2 Data EBus2 Data (MSB) EBus2 Acknowledge (Parallel Port) EBus2 Acknowledge (Floppy) EBus2 Acknowledge (AudioIn) EBus2 Acknowledge (AudioOut) EBus2 Request (Parallel Port) EBus2 Request (Floppy) EBus2 Request (Audio EBus2 Request (Audio Out) EBus2 Interrupt (Parallel Port) EBus2 Interrupt (Floppy) EBus2 Interrupt (Audio Playback) EBus2 Interrupt (Audio Capture) EBus2 Read EBus2 Write EBus2 Ready Input pull-up) EBus2 Terminal Count
Ethernet Interface: pins enet_exvr_en enet_mgt_clk enet_mgt_d0 enet_mgt_d1 enet_rx_clk enet_rx_dv enet_rx_er enet_rxd[0] enet_rxd[1] enet_rxd[2] BiDir BiDir External Transceiver Enable Transceiver Management Clock Transceiver Management Data Transceiver Management Data 100baseT Receive Clock 100baseT Receive Frame Delimit 100baseT Receive Error 100baseT Receive Data 100baseT Receive Data 100baseT Receive Data
PCIO Controller
STP2003QFP
TABLE Pinout Function (Continued)
Name enet_rxd[3] enet_tx_clki enet_tx_clko enet_tx_col enet_tx_crs enet_tx_en enet_txd[0] enet_txd[1] enet_txd[2] enet_txd[3] Type Description 100baseT Receive Data 10baseT Transmit Clock 100baseT Transmit Clock 100baseT Colision Detect 100baseT Carrier Sense 100baseT Transmit Enable 100baseT Transmit Data 100baseT Transmit Data 100baseT Transmit Data 100baseT Transmit Data
Miscellaneous AuxIO: pins au_cap_irq_l au_pb_irq_l aux_ps_off boot[0] boot[1] cod_pdwn_l fpy_dsel fpy_dsens freq0 freq1 freq2 mode pci_s0_prsnt1 pci_s0_prsnt2 pci_s1_prsnt1 pci_s1_prsnt2 pci_s2_prsnt1 pci_s2_prsnt2 pci_s3_prsnt1 pci_s3_prsnt2 sys_ps_off system_led tsens_clk tsens_cs_l tsens_d BiDir Audio Capture (Motherboard Mode) Audio Playback (Motherboard Mode) Power Output Courtesy Outlet Boot PROM Reset Address Boot PROM Reset Address Audio CODEC Powerdown Output Floppy Density Select Output Floppy Density Sense Input Frequency Margining Frequency Margining Frequency Margining PCIO Mode Add-in PCIO Mode Motherboard Slot Preset Slot Preset Slot Preset Slot Preset Slot Preset Slot Preset Slot Preset Slot Preset Power Output Power Supply System Output Temp Sensor Clock Temp Sensor Chip Select Temp Sensor Data
STP2003QFP
PCIO Controller
TABLE Pinout Function (Continued)
Name Type Description
SCSI Clock Oscillator: pins osc_rst_l scsi_clk scsi_oscen scsi_x1 scsi_x2 clk_10m clk_5m Oscillator Reset 40/80 SCSI Clock Output SCSI Oscillator Enable 40/80 SCSI Crystal 40/80 SCSI Crystal Real Time Clock Time Base Real Time Clock Time Base
JTAG Port Diagnostics: pins clock_stop diag[0] diag[1] diag[2] diag[3] diag[4] jtag_clk jtag_tdi jtag_tdo jtag_tms jtag_trst_l Stop Clock Input Function Function Function Function Function JTAG Clock JTAG Test Data Input(100mA pull-up) JTAG Test Data Output JTAG Test Mode Select (100 pull-up) JTAG Reset (100 pull-up)
Power Ground: pins BSINVSSIO BSVSSIO BSVSSIO_1 Ring Ring
PCIO Controller
STP2003QFP
TABLE Pinout Function (Continued)
Name BSVSSIO_1 PCIVDDIO VDDIO VSSCORE VDDCORE Logic Core Logic Core Ring Ring Socket Compliant Type Ring Description
STP2003QFP
PCIO Controller
Pinout Number
TABLE Pinout Number
Name osc_rst_l diag[4] diag[3] diag[2] diag[1] BSVSSIO_1 diag[0] enet_tx_clko enet_tx_en enet_tx_clki enet_tx_crs BSVSSIO_1 VSSCORE enet_tx_col VDDIO enet_rxd[3] enet_rxd[2] enet_rxd[1] enet_rxd[0] BSVSSIO_1 enet_rx_clk enet_rx_dv enet_rx_er enet_txd[3] VDDCORE enet_txd[2] BSVSSIO_1 enet_txd[1] VDDIO enet_txd[0] enet_exvr_en enet_mgt_clk enet_mgt_d1 enet_mgt_d0 mode BiDir BiDir 100baseT Transmit Data External Transceiver Enable Transceiver Management Clock Transceiver Management Data Transceiver Management Data PCIO Mode: Add-in/Motherboard 100baseT Transmit Data 100baseT Transmit Data 100baseT Receive Clock 100baseT Receive Frame Delimit 100baseT Receive Error 100baseT Transmit Data 100baseT Receive Data 100baseT Receive Data 100baseT Receive Data 100baseT Receive Data 100baseT Colision Detect Function 100baseT Transmit Clock 100baseT Transmit Enable 10baseT Transmit Clock 100baseT Carrier Sense Type Oscillator Reset Function Function Function Function Description
PCIO Controller
STP2003QFP
TABLE Pinout Number (Continued)
Name jtag_tdo BSINVSSIO jtag_tdi VSSCORE jtag_clk VDDIO jtag_tms jtag_trst_l clock_stop cod_pdwn_l BSVSSIO_1 tsens_cs_l tsens_d tsens_clk BSVSSIO_1 sys_ps_off aux_ps_off fpy_dsel fpy_dsens system_led BSVSSIO_1 pci_s3_prsnt2 pci_s3_prsnt1 pci_s2_prsnt2 pci_s2_prsnt1 pci_s1_prsnt2 pci_s1_prsnt1 pci_s0_prsnt2 VDDCORE pci_s0_prsnt1 BSVSSIO_1 freq2 VDDIO freq1 freq0 au_pb_irq_l Frequency Margining Frequency Margining Audio Playback (Motherboard Mode) Frequency Margining Slot Preset Slot Preset Slot Preset Slot Preset Slot Preset Slot Preset Slot Preset Slot Preset Power Output Power Supply Power Output Courtesy Outlet Floppy Density Select Output Floppy Density Sense Input System Output BiDir Temp Sensor Chip Select Temp Sensor Data Temp Sensor Clock JTAG Test Mode Select (100 pull-up) JTAG Reset (100 pull-up) Stop Clock Input Audio CODEC Powerdown Output JTAG Clock JTAG Test Data Input(100mA pull-up) Type Description JTAG Test Data Output
STP2003QFP
PCIO Controller
TABLE Pinout Number (Continued)
Name au_cap_irq_l eb_irq4 eb_irq3 eb_irq2 eb_irq1 eb_rdy BSVSSIO clk_5m VSSCORE clk_10m scsi_oscen scsi_clk BSVSSIO_1 scsi_x1 scsi_x2 VDDIO VDDCORE boot[1] boot[0] PCIVDDIO pci_intd_l pci_intc_l pci_intb_l pci_inta_l BSVSSIO pci_rst_l BSVSSIO_1 pci_clk BSVSSIO_1 pci_gnt_l pci_req_l pci_ad[31] pci_ad[30] pci_ad[29] pci_ad[28] pci_ad[27] BiDir BiDir BiDir BiDir BiDir BiDir BiDir PCIB PCIB PCIB PCIB PCIB PCIB PCIB Grant Request Address/Data (MSB) Address/Data Address/Data Address/Data Address/Data Clock MHz) BiDir PCIB Reset BiDir BiDir BiDir BiDir PCIB PCIB PCIB PCIB Interrupt Request Interrupt Request Interrupt Request Interrupt Request Boot PROM Reset Address Boot PROM Reset Address 40/80 SCSI Crystal 40/80 SCSI Crystal Real Time Clock Time Base SCSI Oscillator Enable 40/80 SCSI Clock Output Real Time Clock Time Base Type Description Audio Capture (Motherboard Mode) EBus2 Interrupt (Audio Capture) EBus2 Interrupt (Audio Playback) EBus2 Interrupt (Floppy) EBus2 Interrupt (Parallel Port) EBus2 Ready Input pull-up)
PCIO Controller
STP2003QFP
TABLE Pinout Number (Continued)
Name pci_ad[26] BSVSSIO_1 pci_ad[25] pci_ad[24] pci_c_be_l[3] pci_idsel pci_ad[23] pci_ad[22] BSVSSIO_1 VSSCORE pci_ad[21] PCIVDDIO pci_ad[20] pci_ad[19] pci_ad[18] pci_ad[17] BSVSSIO_1 pci_ad[16] pci_c_be_l[2] pci_frame_l pci_trdy_l VDDCORE pci_irdy_l BSVSSIO pci_devsel_l pci_stop_l pci_perr_l pci_serr_l pci_par BSVSSIO_1 pci_c_be_l[1] pci_ad[15] pci_ad[14] VSSCORE pci_ad[13] PCIVDDIO BiDir PCIB Address/Data BiDir BiDir BiDir PCIB PCIB PCIB Command/Byte Enable Address/Data Address/Data BiDir BiDir BiDir BiDir BiDir PCIB PCIB PCIB PCIB PCIB Device Select Transaction Terminator Parity Error System Error Data Parity BiDir PCIB Initiator Ready BiDir BiDir BiDir BiDir PCIB PCIB PCIB PCIB Address/Data Command/Byte Enable Frame Target Ready BiDir BiDir BiDir BiDir PCIB PCIB PCIB PCIB Address/Data Address/Data Address/Data Address/Data BiDir PCIB Address/Data BiDir BiDir BiDir BiDir BiDir BiDir PCIB PCIB PCIB PCIB PCIB PCIB Address/Data Address/Data Command/Byte Enable Device Select Configuration cycle Address/Data Address/Data BiDir Type PCIB Description Address/Data
STP2003QFP
PCIO Controller
TABLE Pinout Number (Continued)
Name pci_ad[12] BSVSSIO_1 pci_ad[11] pci_ad[10] pci_ad[9] pci_ad[8] pci_c_be_l[0] BSVSSIO_1 pci_ad[7] pci_ad[6] pci_ad[5] pci_ad[4] pci_ad[3] pci_ad[2] pci_ad[1] PCIVDDIO pci_ad[0] BSVSSIO_1 eb_clken eb_rd_l eb_wr_l eb_tcs eb_dack_l[3] eb_dack_l[2] eb_dack_l[1] VDDCORE eb_dack_l[0] BSVSSIO_1 eb_cs_l[7] VDDIO eb_cs_l[6] eb_cs_l[5] eb_cs_l[4] eb_cs_l[3] BSVSSIO_1 eb_cs_l[2] General Purpose Chip Select UltraSPARC System Controller Chip Select 85C30 Chip Select SuperIO Chip Select Audio Codec Chip Select General Purpose Chip Select EBus2 Acknowledge (Parallel Port) EBus2 Address Latch Enable (bits 23:12) EBus2 Read EBus2 Write EBus2 Terminal Count EBus2 Acknowledge (AudioOut) EBus2 Acknowledge (Audio EBus2 Acknowledge (Floppy) BiDir PCIB Address/Data (LSB) BiDir BiDir BiDir BiDir BiDir BiDir BiDir PCIB PCIB PCIB PCIB PCIB PCIB PCIB Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data BiDir BiDir BiDir BiDir BiDir PCIB PCIB PCIB PCIB PCIB Address/Data Address/Data Address/Data Address/Data Command/Byte Enable BiDir Type PCIB Description Address/Data
PCIO Controller
STP2003QFP
TABLE Pinout Number (Continued)
Name eb_cs_l[1] eb_cs_l[0] VSSCORE BSVSSIO eb_d[7] eb_d[6] eb_d[5] eb_d[4] eb_d[3] BSVSSIO_1 eb_d[2] VDDIO eb_d[1] eb_d[0] eb_a[7] VDDCORE eb_a[6] eb_a[5] eb_a[4] BSVSSIO_1 eb_a[3] eb_a[2] eb_a[1] eb_a[0] eb_dreq[3] eb_dreq[2] eb_dreq[1] eb_dreq[0] BSVSSIO_1 EBus2 Address EBus2 Address EBus2 Address EBus2 Address (LSB) EBus2 Request (Audio Out) EBus2 Request (Audio EBus2 Request (Floppy) EBus2 Request (Parallel Port) EBus2 Address EBus2 Address EBus2 Address BiDir BiDir EBus2 Data EBus2 Data (LSB) EBus2 Address (MSB) BiDir EBus2 Data BiDir BiDir BiDir BiDir BiDir EBus2 Data (MSB) EBus2 Data EBus2 Data EBus2 Data EBus2 Data Type Chip Select EPROM Chip Select Description
STP2003QFP
PCIO Controller
Pinout Name
TABLE Pinout Name
Name BSINVSSIO BSVSSIO BSVSSIO_1 PCIVDDIO VDDCORE Logic Core Ring Ring Type Ring Ring Description
PCIO Controller
STP2003QFP
TABLE Pinout Name (Continued)
Name VDDIO VSSCORE au_cap_irq_l au_pb_irq_l aux_ps_off boot[0] boot[1] clk_10m clk_5m clock_stop cod_pdwn_l diag[0] diag[1] diag[2] diag[3] diag[4] eb_a[0] eb_a[1] eb_a[2] eb_a[3] eb_a[4] eb_a[5] eb_a[6] eb_a[7] eb_clken eb_cs_l[0] eb_cs_l[1] Audio Capture (Motherboard Mode) Audio Playback (Motherboard Mode) Power Output Courtesy Outlet Boot PROM Reset Address Boot PROM Reset Address Real Time Clock Time Base Real Time Clock Time Base Stop Clock Input Audio CODEC Powerdown Output Function Function Function Function Function EBus2 Address (LSB) EBus2 Address EBus2 Address EBus2 Address EBus2 Address EBus2 Address EBus2 Address EBus2 Address (MSB) EBus2 Address Latch Enable (bits 23:12) EPROM Chip Select Chip Select Logic Core Type Ring Description
STP2003QFP
PCIO Controller
TABLE Pinout Name (Continued)
Name eb_cs_l[2] eb_cs_l[3] eb_cs_l[4] eb_cs_l[5] eb_cs_l[6] eb_cs_l[7] eb_d[0] eb_d[1] eb_d[2] eb_d[3] eb_d[4] eb_d[5] eb_d[6] eb_d[7] eb_dack_l[0] eb_dack_l[1] eb_dack_l[2] eb_dack_l[3] eb_dreq[0] eb_dreq[1] eb_dreq[2] eb_dreq[3] eb_irq1 eb_irq2 eb_irq3 eb_irq4 eb_rd_l eb_rdy eb_tcs eb_wr_l enet_exvr_en enet_mgt_clk enet_mgt_d0 enet_mgt_d1 enet_rx_clk enet_rx_dv BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir Type Description General Purpose Chip Select Audio Codec Chip Select SuperIO Chip Select 85C30 Chip Select UltraSPARC System Controller Chip Select General Purpose Chip Select EBus2 Data (LSB) EBus2 Data EBus2 Data EBus2 Data EBus2 Data EBus2 Data EBus2 Data EBus2 Data (MSB) EBus2 Acknowledge (Parallel Port) EBus2 Acknowledge (Floppy) EBus2 Acknowledge (Audio EBus2 Acknowledge (AudioOut) EBus2 Request (Parallel Port) EBus2 Request (Floppy) EBus2 Request (Audio EBus2 Request (Audio Out) EBus2 Interrupt (Parallel Port) EBus2 Interrupt (Floppy) EBus2 Interrupt (Audio Playback) EBus2 Interrupt (Audio Capture) EBus2 Read EBus2 Ready Input pull-up) EBus2 Terminal Count EBus2 Write External Transceiver Enable Transceiver Management Clock Transceiver Management Data Transceiver Management Data 100baseT Receive Clock 100baseT Receive Frame Delimit
PCIO Controller
STP2003QFP
TABLE Pinout Name (Continued)
Name enet_rx_er enet_rxd[0] enet_rxd[1] enet_rxd[2] enet_rxd[3] enet_tx_clki enet_tx_clko enet_tx_col enet_tx_crs enet_tx_en enet_txd[0] enet_txd[1] enet_txd[2] enet_txd[3] fpy_dsel fpy_dsens freq0 freq1 freq2 jtag_clk jtag_tdi jtag_tdo jtag_tms jtag_trst_l mode osc_rst_l pci_ad[0] pci_ad[1] pci_ad[2] pci_ad[3] pci_ad[4] pci_ad[5] pci_ad[6] pci_ad[7] pci_ad[8] pci_ad[9] BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB Type Description 100baseT Receive Error 100baseT Receive Data 100baseT Receive Data 100baseT Receive Data 100baseT Receive Data 10baseT Transmit Clock 100baseT Transmit Clock 100baseT Colision Detect 100baseT Carrier Sense 100baseT Transmit Enable 100baseT Transmit Data 100baseT Transmit Data 100baseT Transmit Data 100baseT Transmit Data Floppy Density Select Output Floppy Density Sense Input Frequency Margining Frequency Margining Frequency Margining JTAG Clock JTAG Test Data Input(100mA pull-up) JTAG Test Data Output JTAG Test Mode Select (100 pull-up) JTAG Reset (100 pull-up) PCIO Mode: Add-in/Motherboard Oscillator Reset Address/Data (LSB) Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data
STP2003QFP
PCIO Controller
TABLE Pinout Name (Continued)
Name pci_ad[10] pci_ad[11] pci_ad[12] pci_ad[13] pci_ad[14] pci_ad[15] pci_ad[16] pci_ad[17] pci_ad[18] pci_ad[19] pci_ad[20] pci_ad[21] pci_ad[22] pci_ad[23] pci_ad[24] pci_ad[25] pci_ad[26] pci_ad[27] pci_ad[28] pci_ad[29] pci_ad[30] pci_ad[31] pci_c_be_l[0] pci_c_be_l[1] pci_c_be_l[2] pci_c_be_l[3] pci_clk pci_devsel_l pci_frame_l pci_gnt_l pci_idsel pci_inta_l pci_intb_l pci_intc_l pci_intd_l pci_irdy_l BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir Type PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB PCIB Description Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data Address/Data (MSB) Command/Byte Enable Command/Byte Enable Command/Byte Enable Command/Byte Enable Clock MHz) Device Select Frame Grant Device Select Configuration cycle Interrupt Request Interrupt Request Interrupt Request Interrupt Request Initiator Ready
PCIO Controller
STP2003QFP
TABLE Pinout Name (Continued)
Name pci_par pci_perr_l pci_req_l pci_rst_l pci_s0_prsnt1 pci_s0_prsnt2 pci_s1_prsnt1 pci_s1_prsnt2 pci_s2_prsnt1 pci_s2_prsnt2 pci_s3_prsnt1 pci_s3_prsnt2 pci_serr_l pci_stop_l pci_trdy_l scsi_clk scsi_oscen scsi_x1 scsi_x2 sys_ps_off system_led tsens_clk tsens_cs_l tsens_d BiDir BiDir BiDir BiDir BiDir BiDir BiDir BiDir Type PCIB PCIB PCIB PCIB PCIB PCIB PCIB Data Parity Parity Error Request Reset Slot Preset Slot Preset Slot Preset Slot Preset Slot Preset Slot Preset Slot Preset Slot Preset System Error Transaction Terminator Target Ready 40/80 SCSI Clock Output SCSI Oscillator Enable 40/80 SCSI Crystal 40/80 SCSI Crystal Power Output Power Supply System Output Temp Sensor Clock Temp Sensor Chip Select Temp Sensor Data Description
STP2003QFP
PCIO Controller
ELECTRICAL SPECIFICATIONS
TABLE Absolute Maximum Ratings
Symbol Vin, Vout Tstg Parameter Power Supply Voltage Input, Output Voltage Current Drain pair Storage Temperature Maximum Case Temperature Power dissipation -0.5 -0.5 Limit Watts Unit
Note: Stresses beyond those listed above table cause physical damage device should avoided.
TABLE Recommended Operating Conditions
Symbol Vin, Vout Parameter Power Supply Voltage Input, Output Voltage Operating Case Temperature 4.75 5.25 Limit Unit
PCIO Controller
STP2003QFP
TABLE Characteristics
Symbol Parameter Input Voltage CMOS Input High Voltage CMOS Output High Voltage CMOS (DC) Output Voltage CMOS (DC) Cclk Cidsel Input Leakage (non pins) Input High Leakage (PCI pins) InputLow Leakage (PCI pins) Input Capacitance (PCI) Capacitance (PCI) IDSEL Capacitance (PCI)
JTAG input levels Signals without pullup must have Iol. Signals requiring pullup must have Iol.
Conditions
Unit
VDD*0.3
VDD*0.7
-4,-8,-16 -4,-8,-16
-0.8
Vin=VDD Vin=2.7V Vin=0.5V
TABLE Environmental Electrical Protection
Minimum Latch Minimum
STP2003QFP
PCIO Controller
CHARACTERISTICS
Timing Characteristics have been obtained with operating conditions exceeding recommended limits. voltage variation, 4.5V 5.5V, factored into vendors BCCOM WCCOM timing libraries specified Table through Table
T_cyc T_low T_high clock T_su Input T_val Output T_on T_off Tri_Output T_hold
Figure General Timing Waveforms TABLE Timing Characteristics
Symbol T_cyc T_high T_low Inputs T_su T_su(ptp) T_hold Outputs T_val T_val(ptp) T_on T_off pci_clk Signal Valid Delay bused pci_clk Signal Valid Delay pci_req_l Float Active Delay Active Float Delay 50pF Load 50pF Load Input Setup Time pci_clk bused Input Setup Time pci_clk pci_gnt_l Input Hold Time from pci_clk Note Note pci_clk Cycle Time pci_clk High Time pci_clk Time Parameter Conditions Unit
Static Timing analysis indicates 350ps T_su requirement. Test vector extraction software required granularity. T_su specification currently being tested value. Static Timing analysis shows 250ps T_hold requirement. Test vector extraction software required granularity. T_hold specification currently being tested value
PCIO Controller
STP2003QFP
TABLE Ethernet Timing Characteristics
Symbol Clocks T_cyc rx/tx Cycle Time Duty Cycle Interface T_su(rx) T_hld(rx) T_su(tx) T_hld(tx) T_val Inputs Setup Time rx_clk Inputs Hold Time rx_clk Inputs Setup Time tx_clk Inputs Hold Time tx_clk Output Valid Time from tx_clk 30pF Load Parameter Conditions Unit
TABLE JTAG Timing Characteristics
Symbol JTAG clock T_cyc JTAG Inputs T_su(rx) T_hld(rx) T_val JTAG Inputs Setup Time jtag_clk JTAG Inputs Hold Time jtag_clk JTAG Output Valid Time from jtag_clk negative edge 30pF Load JTAG Cycle Time Parameter Conditions Unit
STP2003QFP
PCIO Controller
EBus2 Timing EBus2 asynchronous bus. timing self regulated handshaking, having fixed relationship PCIO clock. EBus2 timing programmable three timing control registers Ebus2 channel engine. timing control registers programming detailed PCIO User's Manual: Chapter "EBus2 Channel Engine," section 7.5.2, section section 7.7. three timing control registers enable following functions: SETUP TIME (Tsu) HOLD TIME (Thld) EB_CSx_ DACKx_ with respect EB_RD_ EB_WR_ strobes. Minimum deassertion time RECOVERY TIME (Thld) between consecutive EB_RD_ EB_WR_ strobes. WIDTH (Tstrb) EB_RD_ EB_WR_ strobes. Selection priority algorithm Figure illustrates timing parameters which controlled through timing control registers. Timing control registers programmable boot time. alter them after boot time. timing given timing control register tables terms number EBus2 clocks. Note that EBus2 clock same clock which duration 30ns.
EB_CSx_/DACKx_
Thld
EB_RD_/EB_WR_ Tstrb Trec
Figure Programmable Timing Paramaters
PCIO Controller
STP2003QFP
EBus2 Output Input Signals: Timing Characteristics Table specifies tming characteristics required EBus2 input output signals. TABLE EBus2 Timing Characteristics
Symbol Tcyc T_high T_low EBus2 Inputs EBus2 Outputs EB_CLK output valid delay load Input setup time EB_CLK Input hold time from EB_CLK Parameter EBus2 Clock Cycle Time EBus2 Clock High Time EBus2 Clock Time Condition
Minimum
Maximum
Units
EBus2 clock EBus2 channel engine internal clock used PCIO chips. EBus same clock which duration 30ns.
STP2003QFP
PCIO Controller
MECHANICAL INFORMATION
Package Information Drawings
PCIO packaged 208-pin, molded PQFP with copper fused lead frame heat spreader enhanced thermal dissipation. attach Mil. Package drawings mechanical data shown below.
Package Marking (Production Version) STP2003QFP 100-4183-05 609-0392059 DTXXXXX YYYY KOREA (Sun logo) (Sun Copy rights)
Part Number
DTXXXXX: trace number (e.g. DT06551) YYYY: Assembly date code (for example: 9542; only dates 96XX later)
TABLE Thermal Characteristics (extrapolated flow)
Package type fused lead frame heat spreader Theta_JA 20.0 Theta_JC Unit °C/W
PCIO Controller
STP2003QFP
208-Pin PQFP Package Dimensions
30.6 ±0.2 28.0 ±0.2 25.35 REF.
Index
0.50 Nom. Max. ±0.2
0.22 ±0.05
0.10 SEATING PLANE
0~7°
0.25 0.40 Dimensions millimeters.
0.50 0.75
STP2003QFP
PCIO Controller
ORDERING INFORMATION
Part Number STP2003PQFP Description PCIO Controller, 208-Pin Plastic Quad Flat Pack (PQFP)
Document Part Number: 802-7836-02

PCIO PCIO chip high integration, high performance single chip sub

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