Skew Output Buffer ICS9112-17 high performance, skew, jitter zero
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ICS9112-17
Skew Output Buffer
ICS9112-17 high performance, skew, jitter zero delay buffer. uses phase lock loop (PLL) technology align, both phase frequency, input with CLKOUT signal. designed distribute high speed clocks systems operating speeds from MHz. ICS9112-17 zero delay buffer that provides synchronization between input output. synchronization established CLKOUT feed back input PLL. Since skew between input output less than part acts zero delay buffer. ICS9112-17 banks four outputs controlled address lines. Depending selected address line, bank both banks tri-state mode. this mode, still running only output buffers high impedance mode. test mode shuts connects input directly output buffers (see table below functionality). ICS9112-17 comes sixteen SOIC SSOP package. absence input, will power down mode. this mode, turned output buffers pulled low. Power down mode provides lowest power consumption standby condition.
Features
Zero input output delay Frequency range (3.3V) High loop filter bandwidth ideal Spread Spectrum applications. Less than cycle cycle Jitter Skew controlled outputs Skew less than between outputs Available pin, SSOP SOIC package
Configuration
Block Diagram
SSOP SOIC
Functionality
CLKA Driven CLKB Tristate CLKOUT Driven Driven Bypass Mode Driven Output Source Shutdown Tristate Tristate Bypass Bypass Mode Mode Driven Driven
0051H-06/06/02
ICS9112-17
Descriptions
NUMBER NAME
TYPE
DESCRIPTION Input reference frequency. Buffered clock output, Bank Buffered clock output, Bank Power Supply (3.3V) Ground Buffered clock output. Bank Buffered clock output. Bank Select input, Select input, Buffered clock output. Bank Buffered clock output. Bank Buffered clock output, Bank Buffered clock output, Bank Buffered clock output, internal feedback this
CLKA1 CLKA2 CLKB1 CLKB2
CLKB3 CLKB4 CLKA3 CLKA4
CLKOUT3
Notes: Guaranteed design characterization. subject 100% test. Weak pull-down Weak pull-down outputs Weak pull-ups these inputs
0051H-06/06/02
ICS9112-17
Absolute Maximum Ratings
Supply Voltage Logic Inputs -0.5 +0.5 Ambient Operating Temperature +70°C Storage Temperature -65°C +150°C Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. These ratings stress specifications only functional operation device these other conditions above those listed operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect product reliability.
Electrical Characteristics Input Supply
70C; Supply Voltage +/-10% (unless otherwise stated) PARAMETER Input High Voltage Input Voltage Input High Current Input Current Operating current Input frequency Input Capacitance
SYMBOL CONDITIONS IDD1 CIN1 Outputs Loaded Logic Inputs
-0.5
UNITS +0.5
Guaranteed design, 100% tested production.
Electrical Characteristics Input Supply
70C; Supply Voltage +/-10% (unless otherwise stated) PARAMETER Input High Voltage Input Voltage Input High Current Input Current Operating current Input frequency Input Capacitance
SYMBOL CONDITIONS IDD1 CIN1 Outputs Loaded Logic Inputs
GND-0.3
UNITS DD+0.3
Guarenteed design, 100% tested production.
0051H-06/06/02
ICS9112-17
Electrical Characteristics OUTPUT
70C; +/-10%; (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Voltage Rise Time1 Fall Time
SYMBOL RDSP RDSN
CONDITIONS VDD*(0.5) VDD*(0.5)
0.25
UNITS
Lock Time1 Duty Cycle1 Cycle Cycle jitter1 Absolute Jitter1 Jitter; 1-Sigma1 Skew1 Device Device Skew1 Delay Input-Output1
Stable power supply, valid clock tLOCK presented 1.4V;Cl=30pF Tcyc-cyc 66MHz Loaded Outputs Tcyc-cyc >66MHz Loaded Outputs Tjabs 10000 cycles; Cl=30pF Tj1s 10000 cycles; Cl=30pF (Window) Output Output Measured VDD/2 CLKOUT Tdsk-Tdsk pins devices
-100
Guaranteed design, 100% tested production.
Electrical Characteristics OUTPUT
70C; +/-10%; (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Voltage Rise Time1 Fall Time1 SYMBOL RDSP RDSN CONDITIONS DD*(0.5) DD*(0.5) UNITS
0.25
Stable power supply, valid clock Lock Time1 tLOCK presented 1.4V;Cl=30pF Duty Cycle1 Vdd/2; Fout <66.6MHz Tcyc-cyc 66MHz Loaded Outputs Cycle Cycle jitter1 Tcyc-cyc >66MHz Loaded Outputs Tjabs 10000 cycles; Cl=30pF Absolute Jitter Jitter; 1-Sigma1 Tj1s 10000 cycles; Cl=30pF Skew1 (Window) Output Output Measured VDD/2 CLKOUT Device Device Skew1 Tdsk-Tdsk pins devices Delay Input-Output1
-100
Guaranteed design, 100% tested production.
0051H-06/06/02
ICS9112-17
Output Output Skew
skew between CLKOUT CLKA/B outputs dynamically adjusted PLL. Since CLKOUT inputs PLL, zero phase difference maintained from CLKOUT. outputs equally loaded, zero phase difference will maintained from outputs. applications requiring zero output-output skew, outputs must equally loaded. CLKA/B outputs less loaded than CLKOUT, CLKA/B outputs will lead CLKA/B more loaded than CLKOUT, CLKA/B will CLKOUT. Since CLKOUT CLKA/B outputs identical, they start same time, different loads cause them have different rise times different times crossing measurement thresholds.
input outputs loaded Equally
input CLKA/B outputs loaded equally, with CLKOUT loaded More.
input CLKA/B outputs loaded equally, with CLKOUT loaded Less.
0051H-06/06/02
Timing diagrams with different loading configurations
ICS9112-17
Application Suggestion:
ICS9112-17 mixed analog/digital product. analog portion very sensitive random noise generated charging discharging internal external capacitor power supply pins. This type noise will cause excess jitter outputs ICS9112-17. Below recommended alleviate addition noise. additional information layout, please refer AN07. capacitors should connected close possible power pins 13). Isolated power plane with capacitor ground will enhance power line stability.
CLKA1 CLKA2
CLKOUT CLKA4 CLKA3 CLKB4 CLKB3
0.1µF
CLKB1 CLKB2
0.1µF
0051H-06/06/02
ICS9112-17
SYMBOL VARIATIONS 10-0032 4.80 5.00
SSOP (QSOP) Millimeters Inches COMMON DIMENSIONS COMMON DIMENSIONS 1.35 1.75 .053 .069 0.10 0.25 .004 .010 -1.50 -.059 0.20 0.30 .008 .012 0.18 0.25 .007 .010 VARIATIONS VARIATIONS 5.80 6.20 .228 .244 3.80 4.00 .150 .157 0.635 BASIC 0.025 BASIC 0.40 1.27 .016 .050 VARIATIONS VARIATIONS VARIATIONS VARIATIONS
(Ref) 0.23
(inch) .189 .197
(Ref) .009
Reference Doc.: JEDEC Publication MO-137
Ordering Information
ICS9112yF-17-T
Example:
XXXX
Designation tape reel packaging Pattern Number digit number parts with code patterns) Package Type F=SSOP
Revision Designator (will correlate with datasheet revision)
Device Type (consists digit numbers) Prefix ICS, Standard Device
0051H-06/06/02
ICS9112-17
INDEX AREA
SEATING PLANE (.004)
(Narrow Body) SOIC Millimeters Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS 1.35 1.75 .0532 .0688 0.10 0.25 .0040 .0098 0.33 0.51 .013 .020 0.19 0.25 .0075 .0098 VARIATIONS VARIATIONS 3.80 4.00 .1497 .1574 0.050 BASIC 1.27 BASIC 5.80 6.20 .2284 .2440 0.25 0.50 .010 .020 0.40 1.27 .016 .050 VARIATIONS VARIATIONS VARIATIONS 9.80 10.00 (inch) .3859 .3937
Reference JEDEC ublicatio S-01 0-0030
Ordering Information
ICS9112yM-17-T
Example:
XXXX
Designation tape reel packaging Pattern Number digit number parts with code patterns) Package Type M=SOIC
Revision Designator (will correlate with datasheet revision)
Device Type (consists digit numbers) Prefix ICS, Standard Device
0051H-06/06/02
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