Operating voltage: program memory data memory HALT function wake-up fe

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Operating voltage: program memory data memory HALT function wake-up fe

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HT48RB8 8-Bit Type
Operating voltage: program memory data memory HALT function wake-up feature reduce power
fSYS=6M/12MHz: 4.0V~5.5V
voltage reset function bidirectional lines (max.) 8-bit programmable timer/event counter with over-
consumption
8-level subroutine nesting 0.33ms instruction cycle with 12MHz system
flow interrupt
16-bit programmable timer/event counter over-
flow interrupts
Crystal oscillator (6MHz 12MHz) Watchdog Timer channels 8-bit converter USB1.1 speed function endpoints supported (endpoint included)
clock VDD=5V
manipulation instruction 15-bit table read instruction powerful instructions instructions machine cycles 28-pin SOP, 48-pin SSOP package
General Description
This device 8-bit high performance RISC-like microcontroller designed product applications. particularly suitable products such mice, keyboards joystick. HALT feature included reduce power consumption.
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HT48RB8
Block Diagram
ifte
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HT48RB8
Assignment
Description
Name Code Option Description
PA0~PA5 PA6/TMR0 PA7/TMR1
Bidirectional 8-bit input/output port. Each configured wake-up input code option. input output mode controlled control register). Pull-high resistor options: PA0~PA7 Pull-low resistor options: PA0~PA5 Pull-low CMOS/NMOS/PMOS options: PA0~PA7 Pull-high Wake options: PA0~PA7 Wake-up CMOS/NMOS/PMOS pin-shared with TMR0 TMR1 input, respectively. PA0~PA5 used mouse input mouse hardware wake-up function PA6, used mouse button input mouse hardware wake-up function Bidirectional 8-bit input/output port. Software instructions determine CMOS output Schmitt trigger input with pull-high resistor (determined pull-high options). used analog input analog digital converter (determined options). PB6, used mouse button input mouse Hardware wake-up function Bidirectional lines. Software instructions determine CMOS output Schmitt trigger input with pull-high resistor (determined 1-bit pull-high option). used mouse button input mouse hardware wake-up function
PB0/AN0 PB1/AN1 PB2/AN2 PB3/AN3 PB4/AN4 PB5/AN5 PB6/VRL PB7/VRH
Pull-high Analog input
PD0~PD7
Pull-high
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Name Code Option Description Negative power supply, ground Bidirectional lines. Software instructions determine CMOS output Schmitt trigger input with pull-high resistor (determined pull-high options). used mouse IRPT control mouse hardware wake-up function Schmitt trigger reset input. Active Positive power supply 3.3V regulator output USBD+ line USBDOSC1, OSC2 connected 6MHz 12MHz Crystal/resonator (determined software instructions) internal system clock.
PC0~PC7
Pull-high
V33O USBD+ USBDOSC1 OSC2
Absolute Maximum Ratings
Supply Voltage .VSS-0.3V VSS+5.5V Input Voltage.VSS-0.3V VDD+0.3V Storage Temperature .-50°C 125°C Operating Temperature.-40°C 85°C
Note: These stress ratings only. Stresses exceeding range specified under Maximum cause substantial damage device. Functional operation this device other conditions beyond those listed specification implied prolonged exposure extreme conditions affect device reliability.
D.C. Characteristics
Symbol VDD1 VDD2 IDD1 IDD2 ISTB1 ISTB2 VIL1 VIH1 VIL2 VIH2 IOL1 IOL2 IOL3 IOL4 Parameter Operating Voltage Operating Voltage Operating Current (6MHz Crystal) Operating Current (12MHz Crystal) Standby Current (WDT Enabled) Standby Current (WDT Disabled) Input Voltage Ports Input High Voltage Ports Input Voltage (RES) Input High Voltage (RES) Port Sink Current PC1~PC7, Port Sink Current PC1~PC7, Port Sink Current Port Sink Current Test Conditions VOL=3.4V VOL=0.4V VOL=0.4V VOL=0.4V Conditions fSYS=6MHz fSYS=12MHz load, fSYS=6MHz load, fSYS=12MHz load, system HALT, suspend load, system HALT, suspend Min. 0.7VDD 0.9VDD Typ. Max. 0.3VDD 0.4VDD
Ta=25°C Unit
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Symbol IOH1 IOH2 VLVR VV33O EA/D Parameter Port Source Current Test Conditions Conditions VOH=3.4V VOH=3.4V IV33O=-5mA Total error Min. Typ. Max. Unit
Port Source Current PC1~PC7, Pull-high Resistance Pull-low Resistance PA1~PA5 Voltage Reset 3.3V Regulator Output Conversion Error
A.C. Characteristics
Symbol fSYS fTIMER Parameter System Clock (Crystal OSC) Timer Frequency (TMR0/TMR1) Test Conditions Conditions Without prescaler Without prescaler Wake-up from HALT Power-up, Watchdog Time-out from normal Min. Typ. Max. 1024 1024 1024
Ta=25°C Unit tSYS tSYS tWDTOSC tA/D
tWDTOSC Watchdog Oscillator tWDT1 tWDT2 tRES tSST1 tSST2 tINT tADC Note: tA/D= Watchdog Time-out Period (WDT OSC) Watchdog Time-out Period (System Clock) External Reset Pulse Width System Start-up Timer Period System Start-up Timer Period Interrupt Pulse Width Conversion Time
fA/D=A/D clock source frequencies (6MHz, 3MHz, 1.5MHz, 0.75MHz)
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Functional Description
Execution flow system clock microcontroller derived from either crystal oscillator. system clock internally divided into four non-overlapping clocks. instruction cycle consists four system clock cycles. Instruction fetching execution pipelined such that fetch takes instruction cycle while decoding execution takes next instruction cycle. However, pipelining scheme causes each instruction effectively execute cycle. instruction changes program counter, cycles required complete instruction. Program counter program counter (PC) controls sequence which instructions stored program executed contents specify full range program memory. After accessing program memory word fetch instruction code, contents program counter
incremented one. program counter then points memory word containing next instruction code. When executing jump instruction, conditional skip execution, loading register, subroutine call return from subroutine, initial reset, internal interrupt, external interrupt return from interrupts, manipulates program transfer loading address corresponding each instruction. conditional skip activated instructions. Once condition met, next instruction, fetched during current instruction execution, discarded dummy cycle replaces proper instruction. Otherwise proceed next instruction. lower byte program counter (PCL) readable writeable register (06H). Moving data into performs short jump. destination will within current program page. When control transfer takes place, additional dummy cycle required.
Execution flow
Mode Initial reset interrupt Timer/Event Counter overflow Timer/Event Counter overflow Skip Loading Jump, call branch Return from subroutine
Program Counter
PC+2
Program counter Note: *11~*0: Program counter bits #11~#0: Instruction code bits S11~S0: Stack register bits @7~@0: bits
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Program memory program memory used store program instructions which executed. also contains data, table, interrupt entries, organized into bits, addressed program counter table pointer. Certain locations program memory reserved special usage:
Location 000H Location 00CH
This location reserved Timer/Event Counter interrupt service program. timer interrupt results from Timer/Event Counter overflow, interrupt enabled stack full, program begins execution location 00CH.
Table location
This area reserved program initialization. After chip reset, program always begins execution location 000H.
Location 004H
This area reserved interrupt service program. interrupt activated, interrupt enabled stack full, program begins execution location 004H.
Location 008H
This area reserved Timer/Event Counter interrupt service program. timer interrupt results from Timer/Event Counter overflow, interrupt enabled stack full, program begins execution location 008H
itia
location program memory used look-up tables. instructions (the current page, page=256 words) (the last page) transfer contents lower-order byte specified data memory, higher-order byte TBLH (08H). Only destination lower-order byte table well-defined, other bits table word transferred lower portion TBLH, remaining 1-bit words read Table Higher-order byte register (TBLH) read only. table pointer (TBLP) read/write register (07H), which indicates table location. Before accessing table, location must placed TBLP. TBLH read only cannot restored. main routine (Interrupt Service Routine) both employ table read instruction, contents TBLH main routine likely changed table read instruction used ISR. Errors occur. other words, using table read instruction main routine simultaneously should avoided. However, table read instruction applied both main routine ISR, interrupt supposed disabled prior table read instruction. will enabled until TBLH been backed table related instructions require cycles complete operation. These areas function normal program memory depending upon requirements. Stack register STACK
Program memory
This special part memory which used save contents program counter (PC) only. stack organized into levels neither part data part program space, neither readable writeable. activated level indexed stack pointer (SP) neither readable writeable.
Instruction TABRDC TABRDL
Table Location
Table location Note: *11~*0: Table location bits @7~@0: Table pointer bits P11~P8: Current program counter bits
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subroutine call interrupt acknowledge signal, contents program counter pushed onto stack. subroutine interrupt routine, signaled return instruction (RET RETI), program counter restored previous value from stack. After chip reset, will point stack. stack full non-masked interrupt takes place, interrupt request flag will recorded acknowledge signal will inhibited. When stack pointer decremented RETI), interrupt will serviced. This feature prevents stack overflow allowing programmer structure more easily. similar case, stack full subsequently executed, stack overflow occurs first entry will lost (only most recent return addresses stored). Data memory Bank data memory designed with bits. data memory divided into functional groups: special function registers general purpose data memory Most read/write, some read only. special function registers include indirect addressing registers (R0;00H, R1;02H), Bank register (BP, 04H), Timer/Event Counter (;0DH), Timer/Event Counter control register (TMR0C;0EH), Timer/Event Counter higher order byte register (TMR1H;0FH), Timer/Event Counter lower order byte register (TMR1L;10H), Timer/Event Counter control register (TMR1C;11H), program counter lower-order byte register (PCL;06H), memory pointer registers (MP0;01H, MP1;03H), accumulator (ACC;05H), table pointer (TBLP;07H), table higher-order byte register (TBLH;08H), status register (STATUS;0AH), interrupt control register (INTC;0BH), Watchdog Timer option setting register (WDTS;09H), registers (PA;12H, PB;14H, PC;16H, PD;18H), control registers (PAC;13H, PBC;15H, PCC;17H, PDC;19H). USB/PS2 status control register (USC;1AH), endpoint interrupt status register (USR;1BH), system clock control register (SCC;1CH). converter status control register (ADSC;1DH) converter result register (ADR;1EH). remaining space before reserved future expanded usage reading these locations will general purpose data memory, addressed from BFH, used data control information under instruction commands.
Bank mapping data memory areas handle arithmetic, logic, increment, decrement rotate operations directly. Except some dedicated bits, each data memory reset They also indirectly accessible through memory pointer registers (MP0 MP1).
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Data memory Bank special function registers used interface located bank order access Bank1 register, only Indirect addressing pointer used Bank register should mapping bank shown.
Bank0 Bank1 data according value respectively. memory pointer registers (MP0 MP1) 8-bit registers. Accumulator accumulator closely related operations. also mapped location data memory carry immediate data operations. data movement between data memory locations must pass through accumulator. Arithmetic logic unit This circuit performs 8-bit arithmetic logic operations. provides following functions:
Arithmetic operations (ADD, ADC, SUB, SBC, DAA) Logic operations (AND, XOR, CPL) Rotation (RL, RLC, RRC) Increment Decrement (INC, DEC) Branch decision (SZ, SNZ, SIZ,
only saves results data operation also changes status register. bank Status register STATUS
Indirect addressing register Location indirect addressing registers that physically implemented. read/write operation [00H] ([02H]) will access data memory pointed (MP1). Reading location (02H) itself indirectly will return result 00H. Writing indirectly results operation. indirect addressing pointer (MP0) always point Bank0 addresses matter value Bank Register (BP). indirect addressing pointer (MP1) access Labels Bits
This 8-bit register (0AH) contains zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PD), watchdog time-out flag (TO). also records status information controls operation sequence. With exception flags, bits status register altered instructions like most other registers. data written into status register will change flag. addition operations related status register give different results from those intended. Function
operation results carry during addition operation borrow does take place during subtraction operation; otherwise cleared. also affected rotate through carry instruction. operation results carry nibbles addition borrow from high nibble into nibble subtraction; otherwise cleared. result arithmetic logic operation zero; otherwise cleared. operation results carry into highest-order carry highest-order bit, vice versa; otherwise cleared. cleared system power-up executing instruction. executing instruction. cleared system power-up executing instruction. time-out. Unused bit, read Unused bit, read Status register
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flag affected only system power-up, time-out executing instruction. flag affected only executing instruction during system power-up. flags generally reflect status latest operations. addition, entering interrupt sequence executing subroutine call, status register will pushed onto stack automatically. contents status important subroutine corrupt status register, precautions must taken save properly. Interrupt device provides external interrupt internal timer/event counter interrupts. Interrupt Control Register (INTC;0BH) contains interrupt control bits enable/disable interrupt request flags. Once interrupt subroutine serviced, other interrupts will blocked clearing bit). This scheme prevent further interrupt nesting. Other interrupt requests occur during this interval only interrupt request flag recorded. certain interrupt requires servicing within service routine, corresponding INTC allow interrupt nesting. stack full, interrupt request will acknowledged, even related interrupt enabled, until decremented. immediate service desired, stack must prevented from becoming full. these kinds interrupts have wake-up capability. interrupt serviced, control transfer occurs pushing program counter onto stack, followed branch subroutine specified location program memory. Only program counter pushed onto stack. contents register status register (STATUS) altered interrupt service program which corrupts desired control sequence, contents should saved advance. Register INTC (0BH) Label ET0I ET1I USBF interrupts triggered following events related interrupt request flag (USBF; INTC) will set.
access corresponding FIFO from suspend signal from resume signal from Reset signal
When interrupt enabled, stack full external interrupt active, subroutine call location will occur. interrupt request flag (USBF) bits will cleared disable other interrupts. When Host access FIFO HT48RB8, corresponding request set, interrupt triggered. user easy decide which FIFO accessed. When interrupt been served, corresponding should cleared firmware. When HT48RB8 receive Suspend signal from Host suspend line (bit0 USC) HT48RB8 interrupt also triggered. Also when HT48RB8 receive Resume signal from Host resume line (bit3 USC) HT48RB8 interrupt triggered. Whatever there reset signal detected, interrupt triggered. internal Timer/Event Counter interrupt initialized setting Timer/Event Counter interrupt request flag INTC), caused timer overflow. When interrupt enabled, stack full set, subroutine call location will occur. related interrupt request flag (T0F) will reset cleared disable further interrupts. internal timer/even counter interrupt initialized setting Timer/Event Counter interrupt request flag (;bit INTC), caused timer overflow. When interrupt enabled, stack full set, subroutine call location will occur. related interrupt request flag (T1F) will reset cleared disable further interrupts.
Function Controls master (global) interrupt enabled; disabled) Controls interrupt enabled; disabled) Controls Timer/Event Counter interrupt enabled; disabled) Controls Timer/Event Counter interrupt enabled; disabled) interrupt request flag active; inactive) Internal Timer/Event Counter request flag active; inactive) Internal Timer/Event Counter request flag active; inactive) Unused bit, read INTC register
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HT48RB8
During execution interrupt subroutine, other interrupt acknowledge signals held until instruction executed related interrupt control stack full). return from interrupt subroutine, invoked. RETI will enable interrupt service, will not. Interrupts, occurring interval between rising edges consecutive pulses, will serviced latter pulses, corresponding interrupts enabled. case simultaneous requests following table shows priority that applied. These masked resetting bit. Interrupt Source interrupt Timer/Event Counter overflow Timer/Event Counter overflow Priority Vector Oscillator configuration There oscillator circuits microcontroller.
illa
System oscillator This oscillator designed system clocks. HALT mode stops system oscillator ignores external signal conserve power. crystal across OSC1 OSC2 needed provide feedback phase shift required oscillator. other external components required. stead crystal, resonator also connected between OSC1 OSC2 frequency reference, external capacitors OSC1 OSC2 required. oscillator free running on-chip oscillator, external components required. Even system enters power down mode, system clock stopped, oscillator still works within period approximately 72ms. oscillator disabled code option conserve power. Watchdog Timer clock source implemented dedicated oscillator (WDT oscillator), instruction clock (system clock divided determines code option. This timer designed prevent software malfunction sequence from jumping unknown location with unpredictable results. Watchdog Timer disabled code option. Watchdog Timer disabled, executions related result operation.
Timer/Event Counter interrupt request flag (T0F/T1F), interrupt request flag (USBF), enable Timer/Event Counter interrupt (ET0I/ET1I), enable interrupt (EUI) enable master interrupt (EMI) constitute interrupt control register (INTC) which located data memory. EMI, EUI, ET0I ET1I used control enabling/disabling interrupts. These bits prevent requested interrupt from being serviced. Once interrupt request flags (T0F, T1F, USBF) set, they will remain INTC register until interrupts serviced cleared software instruction. recommended that program does within interrupt subroutine. Interrupts often occur unpredictable manner need serviced immediately some applications. only stack left enabling interrupt well controlled, original control sequence will damaged once operates interrupt subroutine.
Watchdog Timer
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HT48RB8
Once internal oscillator oscillator with period 72ms@5V normally) selected, first divided (8-stage) nominal time-out period 18.6ms@5V. This time-out period vary with temperatures, process variations. invoking prescaler, longer time-out periods realized. Writing data WS2, WS1, (bit 2,1,0 WDTS) give different time-out periods. WS2, WS1, equal division ratio 1:128, maximum time-out period 2.4s@5V seconds. oscillator disabled, clock still come from instruction clock operates same manner except that HALT state stop counting lose protecting purpose. this situation logic only restarted external logic. high nibble WDTS reserved defined flags, which only (WDTS.7~WDTS.3). device operates noisy environment, using on-chip oscillator (WDT OSC) 32kHz crystal oscillator (RTC OSC) strongly recommended, since HALT will stop system clock. WDTS register overflow under normal operation will initialize status HALT mode, overflow will initialize only reset zero. clear contents (including prescaler), three methods adopted; external reset level RES), software instruction instruction. software instruction include other these types instruction, only active depending code option times selection selected (i.e. CLRWDT times equal one), execution instruction will clear WDT. case that chosen (i.e. CLRWDT times equal two), these instructions must executed clear WDT; otherwise, reset chip result time-out. time-out periods defined WDTS used Mouse Hardware wake-up function. Please reference Mouse Hardware Wake-up function description. Rev. 1.00 Division Ratio 1:16 1:32 1:64 1:128 Power down operation HALT HALT mode initialized instruction results following.
system oscillator will turned
oscillator remains running oscillator selected). contents chip registers remain unchanged.
prescaler will cleared
counted again clock from oscillator).
ports maintain their original status. flag flag cleared.
system leave HALT mode means external reset, interrupt, external falling edge signal port overflow. external reset causes device initialization overflow performs After flags examined, reason chip reset determined. flag cleared system power-up executing instruction when executing instruction. flag time-out occurs, causes wake-up that only resets others remain their original status. port wake-up interrupt methods considered continuation normal execution. Each port independently selected wake device mask option. Awakening from port stimulus, program will resume execution next instruction. awakens from interrupt, sequence occur. related interrupt disabled interrupt enabled stack full, program will resume execution next instruction. interrupt enabled stack full, regular interrupt response takes place. interrupt request flag before entering HALT mode, wake-up function related interrupt will disabled. Once wake-up event occurs, takes 1024 tSYS (system clock period) resume normal operation. other words, dummy period will inserted after wake-up. wake-up results from interrupt acknowledge signal, actual interrupt subroutine execution will delayed more cycles. wake-up results next instruction execution, this will executed immediately after dummy period finished. minimize power consumption, pins should carefully managed before entering HALT status. Reset There three ways which reset occur:
reset during normal operation reset during HALT time-out reset during normal operation
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HT48RB8
time-out during HALT different from other chip reset conditions, since perform that resets only leaving other circuits their original state. Some registers remain unchanged during other reset conditions. Most registers reset when reset conditions met. examining flags, program distinguish between different RESET Conditions reset during power-up reset during normal operation wake-up HALT time-out during normal operation wake-up HALT
Reset circuit
Note: stands guarantee that system oscillator started stabilized, (System Start-up Timer) provides extra-delay 1024 system clock pulses when system reset (power-up, time-out reset) system awakes from HALT state. When system reset occurs, delay added during reset period. wake-up from HALT will enable delay.
Reset configuration functional unit chip reset status shown below. Interrupt Prescaler 000H Disable Clear Clear. After master reset, begins counting
Timer/event Counter Reset timing chart Input/output Ports Input mode Points stack
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states registers summarized table. Reset (Power xxxx xxxx 00-0 1000 xxxx xxxx xxxx xxxx 00-0 1-000H xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx -xxx xxxx xxxx -000 0000 1000 0111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 11xx 0000 0100 0000 0000 0000 1000 0000 xxxx xxxx Time-out (Normal Operation) uuuu uuuu 00-0 1000 uuuu uuuu uuuu uuuu 00-0 1-000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu -000 0000 1000 0111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu Reset (Normal Operation) uuuu uuuu 00-0 1000 uuuu uuuu uuuu uuuu 00-0 1-000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu -000 0000 1000 0111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 11xx 0000 0100 0000 0000 0000 1000 0000 xxxx xxxx Reset (HALT) uuuu uuuu 00-0 1000 uuuu uuuu uuuu uuuu 00-0 1-000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu -000 0000 1000 0111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 11xx 0000 0100 0000 0000 0000 1000 0000 xxxx xxxx Time-out (HALT)* uuuu uuuu uu-u uuuu uuuu uuuu uuuu uuuu uu-u u-000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu USB-reset (Normal) uuuu uuuu 00-0 1000 uuuu uuuu uuuu uuuu 00-0 1-000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu -000 0000 1000 0111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uu00 0u00 01uu 0000 0000 u000 1000 0000 xxxx xxxx USB-reset (HALT) uuuu uuuu 00-0 1000 uuuu uuuu uuuu uuuu 00-0 1-000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu -000 0000 1000 0111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uu00 0u00 01uu 0000 0000 u000 1000 0000 xxxx xxxx
Register
TMR0 TMR0C TMR1H TMR1L TMR1C Program Counter TBLP TBLH STATUS INTC WDTS PIPE STALL MISC FIFO0 FIFO1 FIFO2 FIFO3 ADSC Note:
stands stands stands
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HT48RB8
Timer/Event Counter timer/event counters (TMR0, TMR1) implemented microcontroller. Timer/Event Counter contains 8-bit programmable count-up counter clock comes from external source from fSYS/4. Timer/Event Counter contains 16-bit programmable count-up counter clock come from external source from system clock divided Label (TMR0C) Bits Unused bit, read define TMR0 active edge Timer/Event Counter (0=active high; 1=active high low) enable/disable timer counting (0=disabled; 1=enabled) Unused bit, read define operating mode 01=Event count mode (external clock) 10=Timer mode (internal clock) 11=Pulse width measurement mode 00=Unused TMR0C register Label (TMR1C) Bits Unused bit, read define TMR1 active edge Timer/Event Counter (0=active high; 1=active high low) enable/disable timer counting (0=disabled; 1=enabled) Unused bit, read define operating mode 01=Event count mode (external clock) 10=Timer mode (internal clock) 11=Pulse width measurement mode 00=Unused TMR1C register Function Using internal clock source, there only reference time-base Timer/Event Counter internal clock source coming from fSYS/4. external clock input allows user count external events, measure time intervals pulse widths. Using internal clock source, there only reference time-base Timer/Event Counter internal clock source coming from fSYS/4. external clock input allows user count external events, measure time intervals pulse widths. Function
Timer/Event Counter
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HT48RB8
Timer/Event Counter There registers related Timer/Event Counter TMR0 ([0DH]), TMR0C ([0EH]). physical registers mapped TMR0 location; writing TMR0 makes starting value placed Timer/Event Counter preload register reading TMR0 gets contents Timer/Event Counter TMR0C timer/event counter control register, which defines some options. There registers related Timer/Event Counter TMR1H (0FH), TMR1L (10H), TMR1C (11H). Writing TMR1L will only written data internal lower-order byte buffer bits) writing TMR1H will transfer specified data contents lower-order byte buffer TMR1H TMR1L preload registers, respectively. Timer/Event Counter preload register changed each writing TMR1H operations. Reading TMR1H will latch contents TMR1H TMR1L counters destination lower-order byte buffer, respectively. Reading TMR1L will read contents lower-order byte buffer. TMR1C Timer/Event Counter control register, which defines operating mode, counting enable disable active edge. TM0, bits define operating mode. event count mode used count external events, which means clock source comes from external (TMR0/TMR1) pin. timer mode functions normal timer with clock source coming from fSYS/4 (Timer0/Timer1). pulse width measurement mode used count high level duration external signal (TMR0/TMR1). counting based fSYS/4 (Timer0/Timer1). event count timer mode, once Timer/Event Counter starts counting, will count from current contents Timer/Event Counter FFFFH. Once overflow occurs, counter reloaded from Timer/Event Counter preload register generates interrupt request flag (T0F/T1F; INTC) same time. pulse width measurement mode with bits equal one, once TMR0/TMR1 received transient from high high bits will start counting until TMR0/TMR1 returns original level resets TON. measured result will remain Timer/Event Counter even activated transient occurs again. other words, only cycle measurement done. Until setting TON, cycle measurement will function again long receives further transient pulse. Note that, this operating mode, Timer/Event Counter starts counting according logic level according transient edges. case counter overflows, counter reloaded from Timer/Event Counter preload register issues interrupt request just like other modes. enable counting operation, timer (TON; TMR0C/TMR1C) should pulse width measurement mode, will cleared automatically after measurement cycle completed. other modes only reset instructions. overflow Timer/Event Counter wake-up sources. matter what operation mode writing ET0I/ET1I disable corresponding interrupt services. case Timer/Event Counter condition, writing data Timer/Event Counter preload register will also reload that data Timer/Event Counter 0/1. Timer/Event Counter turned data written will only kept Timer/Event Counter preload register. Timer/Event Counter will still operate until overflow occurs Timer/Event Counter reloading will occur same time). TMR0/TMR1) read, clock will blocked avoid errors. clock blocking results counting error, this must taken into consideration programmer.
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2002
HT48RB8
Input/output ports There bidirectional input/output lines microcontroller, labeled from which mapped data memory [12H], [14H], [16H] [18H] respectively. these ports used input output operations. input operation, these ports non-latching, that inputs must ready rising edge instruction (m=12H, 14H, 18H). output operation, data latched remains unchanged until output latch rewritten. Each line control register (PAC, PBC, PCC, PDC) control input/output configuration. With this control register, CMOS/NMOS/PMOS output Schmitt trigger input with without pull-high/low resistor structures reconfigured dynamically (i.e. on-the-fly) under software control. function input, corresponding latch control register must write input source also depends control register. control register input will read state. control register contents latches will move internal bus. latter possible instruction. output function, CMOS/NMOS/PMOS configurations selected (NMOS PMOS available only). These control registers mapped locations 13H, 15H, 19H. After chip reset, these input/output lines remain high levels floating state (depending pull-high/low options). Each these input/output latches cleared (m=12H, 14H, 18H) instructions. Some instructions first input data then follow output operations. example, read entire port states into CPU, execute defined operations (bit-operation), then write results back latches accumulator. Each line port capability waking-up device. There pull-high/low only) options available lines. Once pull-high/low option line selected, line have pull-high/low resistor. Otherwise, pull-high/low resistor absent. should noted that non-pull-high/low line operating input mode will cause floating state. recommended that unused bonded lines should output pins software instruction avoid consuming power under input floating state.
Input/output ports
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2002
HT48RB8
voltage reset microcontroller provides voltage reset circuit order monitor supply voltage device. supply voltage device within range 0.9V~VLVR such changing battery, will automatically reset device internally. includes following specifications:
voltage (0.9V~VLVR) remain their
relationship between VLVR shown below.
original state exceed 1ms. voltage state does exceed 1ms, will ignore perform reset function.
uses function with external
signal perform chip reset. Note:
VOPR voltage range proper chip operation 4MHz system clock.
voltage reset Note: make sure that system oscillator stabilized, provides extra delay 1024 system clock pulses before entering normal operation. Since voltage maintained original state exceed 1ms, therefore delay enters reset mode.
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Suspend Wake-Up Remote Wake-Up there signal signal over 3ms, HT48RB8 will into suspend mode Suspend line (bit USC) will interrupt triggered indicate HT48RB8 should jump suspend state meet 500mA suspend current spec. order meet 500mA suspend current, firmware should disable clock clear USBCKEN (bit3 SCC) suspend current about 400mA. Also user further decrease suspend current 250mA SUSP2 (bit4 SCC). SUSP2 set, user make sure cannot enable option, otherwise HT48RB8 will reset. When resume signal sent host, HT48RB8 will wake interrupt Resume line (bit USC) set. order make HT48RB8 work properly, firmware must USBCKEN (bit SCC) clear SUSP2 (bit4 SCC). Since Resume signal will cleared before Idle signal sent host Suspend line (bit USC) going when detecting Suspend line (bit0 USC), Resume line should remembered token into consideration. After finishing resume signal, suspend line will inactive interrupt triggered. following timing diagram
device with remote wake function wake-up Host sending wake-up pulse through RMWK (bit USC). Once Host receive wake-up signal from HT48RB8. will send Resume signal device. timing follow:
configure block HT48RB8 built-in 8-bit converter with channels (PB0~PB5). order make converter more flexibility, there mode: External Reference voltage Internal Reference voltage. easy configure setting ADREF (bit USR). External Reference voltage, reference voltage converter comes from external PB6/VRL PB7/VRH pins. Otherwise, reference voltage coming from MCU. PB0~PB5 6-channels input converter, easy define which channel converting configuring ACS2~ACS0 (bit ADSC). Also there four converter clock source selected setting ADCS1 (bit ADSC), ADCS0 ADSC). Once ADON (bit ADSC) send start pulse through START (bit ADSC). converter will operation. There EOCB (bit ADSC) indicate whether converter busy not. EOCB clear when conversion completed. user read converter data reading register ADR. order meet 500uA suspend current spec. user should disable clearing ADON before jump suspend mode.
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following converter timing diagrams
interface converter There registers, including (address remote wake bank STALL (43H bank PIPE (44H bank MISC (46H bank FIFO0 (48H bank FIFO1 (49H bank FIFO2 (4AH bank FIFO3 (4BH bank used function. register contains current address remote wake function control bit. initial value address value extracted from command loaded into this register until SETUP stage being finished. WKEN AD6~AD0 Bits Remote wake-up enable/disable device address Function
PIPE register represents whether corresponding endpoint accessed host not. This register only after time when host accesses corresponding endpoint. Only last accessed endpoint shown this register. STALL register shows whether corresponding endpoint works properly not. soon endpoint works improperly, related STALL STALL will cleared reset signal. PIPE EP0RW EP1RW EP2RW EP3RW STALL STL0 STL1 STL2 STL3 Bits Bits Stall endpoint Stall endpoint Stall endpoint Stall endpoint Unused bit, read Endpoint accessed Endpoint accessed Endpoint accessed Endpoint accessed Unused bit, read Function Function
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MISC register combines command status control desired endpoint FIFO action show status wanted endpoint FIFO. MISC will cleared reset signal. MISC Bits Function
After setting other status desired MISC, endpoint FIFO reR/W quested setting this After been done, this cleared This defines direction data transferring between endpoint FIFO. When this means that wants write data endpoint FIFO. After been done, this cleared before terminatR/W request represent transferring. reading action, this cleared represent that wants read data from endpoint FIFO after done. Clear requested endpoint FIFO, even endpoint FIFO ready. define which endpoint FIFO selected, SELP1,SELP0: endpoint FIFO0 endpoint FIFO1 endpoint FIFO2 endpoint FIFO3 Read only status bit, used show that data endpoint FIFO SETUP comR/W mand. This cleared firmware. That say, even busing, device will miss SETUP commands from host. Read only status bit, this used indicate that desired endpoint FIFO ready work. Read only status bit, sued indicate that 0-sized packet sent from host MCU. This should cleared firmware.
CLEAR
SELP1 SELP0
SCMD
READY LEN0
communicate with endpoint FIFO setting corresponding registers, which address listed following table. After reading current data, next data will show after 2ms. using check endpoint FIFO status response MSIC register, read/write action still going Registers FIFO0 FIFO1 FIFO2 FIFO3 Bank Address Bit7~Bit0 Data7~Data0 Data7~Data0 Data7~Data0 Data7~Data0
There some timing constrains usages illustrated here. setting MISC register, perform reading, writing clearing actions. There some examples shown following table endpoint FIFO reading, writing clearing. Actions Read FIFO0 sequence Write FIFO1 sequence Check whether FIFO0 read Check whether FIFO1 written Read 0-sized packet sequence form FIFO0 Write 0-sized packet sequence FIFO1 Note: MiSC Setting Flow Status 00H®01H®delay 2ms, check 41H®read* from FIFO0 register check ready (01H)®03H®02H 0AH®0BH®delay 2ms, check 4BH®write* FIFO1 register check ready (0BH)®09H®08H 00H®01H®delay 2ms, check (ready) (not ready)®00H 0AH®0BH®delay 2ms, check (ready) (not ready)®0AH 00H®01H®delay 2ms, check 81H®read once (01H)®03H®02H 0AH®0BH®delay 2ms, check 0BH®0FH®0DH®08H
There existing between reading action between writing action
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definitions status control register (USC; 1AH) shown. SUSP Bits Function Read only, suspend indication. When this (set SIE), indicates enters suspend mode. interrupt also triggered changing this bit. remote wake command. force host leaving suspend mode. When this delay clearing this needed insure RMWK command accepted SIE. reset indication. This set/cleared SIE. When URST this indicates reset occurred interrupt will initialized. resume indication. When leaves suspend mode, this (set SIE). This will appear 20ms waiting detect. When RESUME SIE, interrupt will generated wake-up MCU. order detecting suspend state, should USBCKEN SUSP2 register) enable detecting function. RESUME will cleared while SUSP going When detecting SUSP, RESUME (causes wake-up) should remembered token into consideration. Undefined Undefined This should Data driving USBD+/CLK when work under mouse function. This should
RMWK
URST
RESUME
(USB endpoint interrupt status register) register used indicate which endpoint accessed select converter operation modes. endpoint request flags (EP0IF, EP1IF, EP2IF EP3IF) used indicate which endpoints accessed. endpoint accessed, related endpoint request flag will interrupt will occur interrupt enabled stack full). When active endpoint request flag served, endpoint request flag cleared EP0IF Bits Function
When this (set SIE), indicates endpoint accessed interrupt will occur. When interrupt been served, this should cleared firmware. When this (set SIE), indicates endpoint accessed interrupt will occur. When interrupt been served, this should cleared firmware. When this (set SIE), indicates endpoint accessed interrupt will occur. When interrupt been served, this should cleared firmware. When this (set SIE), indicates endpoint accessed interrupt will occur. When interrupt been served, this should cleared firmware. This should forced This should reference voltage converter coming from when this Otherwise, reference voltage converter comes from external PB6/VRL PB7/VRH pins. only, FIFO read FIFO write
EP1IF
EP2IF
EP3IF ADREF FIFO-cntl
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There system clock control register implemented select clock used MCU. This register consists clock control (USBCKEN), second suspend mode control (SUSP2) system clock selection (SYSCLK). USBCKEN Bits Undefined bits clock control bit. When this indicates that clock enabled. Otherwise, clock turned-off. Function
SUSP2 SYSCLK
This used decreasing power consumption suspend mode. normal mode clean this bit=0 HALT mode this bit=1 decreasing power consumption. Undefined, should cleared This used specify system oscillator frequency used MCU. 6MHz crystal oscillator resonator used, this should 12MHz crystal oscillator resonator used, this should cleared (default). This should forced
converter implemented 6-channel 8-bit converter. reference voltage (high reference voltage reference voltage) selected coming from external pins (PB6/VRL PB7/VRH) internal power supplies (VDD VSS). used minimal maximal boundaries full-scale range converter. analog inputs, used conversion, also used general purpose line. ADSC (A/D converter status control register) register used configurations clock sources converter control operation converter. ADSC Bits Function These bits select eight converter channels conversion. converter input channels AN0~AN5 pin-shared with PB0~PB5. PB6/VRL PB7/VRH used converter reference inputs. ACS2,ACS1,ACS0 AN0/AN1/AN2/AN3/AN4/AN5/VRL/VRH converter clock source selection. ADCS1,ADCS0: 6MHz 3MHz 1.5MHz 0.75MHz Start conversion. (0®1®0: start, 0®1: reset converter data register) This used control enable/disable converter circuit. this converter enters operating mode. Otherwise, converter will turned-off conversion indication. conversion)
ACS2~ACS0
ADCS1 ADCS0
START ADON EOCB
converter data register used store result conversion. D7~D0 Bits Result conversion Function
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Mask options following table shows kinds mask option microcontroller. mask options must defined ensure proper system functioning. Chip lock bit) PA0~PA7 pull-high resistor enabled/disabled bit) PA0~PA5 pull down resistor enabled/disabled bit) PB0~PB7 pull-high resistor enabled/disabled nibble) PC0~PC7 pull-high resistor enabled/disabled nibble) PD0~PD7 pull-high resistor enabled/disabled nibble) enable/disable enable/disable clock source: fSYS/4 WDTOSC CLRWDT instruction(s): PA0~PA7 output structures: CMOS/NMOS open-drain/PMOS open-drain bit) PA0~PA7 wake-up enabled/disabled bit) converter enabled/disabled Option
Application Circuits
Crystal ceramic resonator multiple applications
Note:
resistance capacitance reset circuit should designed such ensure that stable remains within valid operating voltage range before bringing high. 0.01mF capacitor, resistor connected HT48RB8-VDD close possible. 6MHz 12MHz
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Instruction Summary
Mnemonic Arithmetic A,[m] ADDM A,[m] A,[m] ADCM A,[m] A,[m] SUBM A,[m] A,[m] SBCM A,[m] data memory data memory immediate data data memory with carry data memory with carry Subtract immediate data from Subtract data memory from Subtract data memory from with result data memory Subtract data memory from with carry Subtract data memory from with carry result data memory Decimal adjust addition with result data memory 1(1) 1(1) 1(1) 1(1) 1(1) Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Description Instruction Cycle Flag Affected
Logic Operation A,[m] A,[m] A,[m] ANDM A,[m] A,[m] XORM A,[m] CPLA data memory data memory Exclusive-OR data memory data memory data memory Exclusive-OR data memory immediate data immediate data Exclusive-OR immediate data Complement data memory Complement data memory with result 1(1) 1(1) 1(1) 1(1)
Increment Decrement INCA DECA Rotate RRCA RLCA Data Move A,[m] [m],A Operation [m].i [m].i Clear data memory data memory 1(1) 1(1) None None Move data memory Move data memory Move immediate data 1(1) None None None Rotate data memory right with result Rotate data memory right Rotate data memory right through carry with result Rotate data memory right through carry Rotate data memory left with result Rotate data memory left Rotate data memory left through carry with result Rotate data memory left through carry 1(1) 1(1) 1(1) 1(1) None None None None Increment data memory with result Increment data memory Decrement data memory with result Decrement data memory 1(1) 1(1)
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Mnemonic Branch addr [m].i [m].i SIZA SDZA CALL addr RETI Table Read TABRDC TABRDL Miscellaneous WDT1 WDT2 SWAP SWAPA HALT Note: operation Clear data memory data memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles data memory Swap nibbles data memory with result Enter power down mode 1(1) 1(1) 1(1) None None None TO,PD TO(4),PD(4) TO(4),PD(4) None None TO,PD Read code (current page) data memory TBLH Read code (last page) data memory TBLH 2(1) 2(1) None None Jump unconditionally Skip data memory zero Skip data memory zero with data movement Skip data memory zero Skip data memory zero Skip increment data memory zero Skip decrement data memory zero Skip increment data memory zero with result Skip decrement data memory zero with result Subroutine call Return from subroutine Return from subroutine load immediate data Return from interrupt 1(2) 1(2) 1(2) 1(2) 1(3) 1(3) 1(2) 1(2) None None None None None None None None None None None None None Description Instruction Cycle Flag Affected
Immediate data Data memory address Accumulator number bits addr: Program memory address Flag affected Flag affected
loading register occurs, execution cycle instructions will delayed more cycle (four system clocks). skipping next instruction occurs, execution cycle instructions will delayed more cycle (four system clocks). Otherwise original instruction cycle unchanged.
flags affected execution status. Watchdog Timer cleared executing WDT1 WDT2 instruction, cleared. Otherwise flags remain unchanged.
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Instruction Definition
A,[m] Description Operation Affected flag(s) ADCM A,[m] Description Operation Affected flag(s) A,[m] Description Operation Affected flag(s) Description Operation Affected flag(s) ADDM A,[m] Description Operation Affected flag(s) data memory carry accumulator contents specified data memory, accumulator carry flag added simultaneously, leaving result accumulator. ACC+[m]+C
accumulator carry data memory contents specified data memory, accumulator carry flag added simultaneously, leaving result specified data memory. ACC+[m]+C
data memory accumulator contents specified data memory accumulator added. result stored accumulator. ACC+[m]
immediate data accumulator contents accumulator specified data added, leaving result accumulator. ACC+x
accumulator data memory contents specified data memory accumulator added. result stored data memory. ACC+[m]
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A,[m] Description Operation Affected flag(s) Description Operation Affected flag(s) ANDM A,[m] Description Operation Affected flag(s) CALL addr Description Logical accumulator with data memory Data accumulator specified data memory perform bitwise logical_AND operation. result stored accumulator.
Logical immediate data accumulator Data accumulator specified data perform bitwise logical_AND operation. result stored accumulator.
Logical data memory with accumulator Data specified data memory accumulator perform bitwise logical_AND operation. result stored data memory.
Subroutine call instruction unconditionally calls subroutine located indicated address. program counter increments once obtain address next instruction, pushes this onto stack. indicated address then loaded. Program execution continues with instruction this address. Stack PC+1 addr
Operation Affected flag(s)
Description Operation Affected flag(s)
Clear data memory contents specified data memory cleared
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[m].i Description Operation Affected flag(s) Description Operation Affected flag(s) WDT1 Description Clear data memory specified data memory cleared [m].i
Clear Watchdog Timer Prescaler cleared (re-counting from power down (PD) time-out (TO) cleared. Prescaler
Preclear Watchdog Timer flags, Prescaler cleared (re-counting from other preclear instruction been executed. Only execution this instruction without other preclear instruction just sets indicated flag which implies this instruction been executed flags remain unchanged. Prescaler 00H*
Operation Affected flag(s)
WDT2 Description
Preclear Watchdog Timer flags, Prescaler cleared (re-counting from other preclear instruction been executed. Only execution this instruction without other preclear instruction, sets indicated flag which implies this instruction been executed flags remain unchanged. Prescaler 00H*
Operation Affected flag(s)
Description Operation Affected flag(s)
Complement data memory Each specified data memory logically complemented complement). Bits which previously contained changed vice-versa.
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CPLA Description Complement data memory place result accumulator Each specified data memory logically complemented complement). Bits which previously contained changed vice-versa. complemented result stored accumulator contents data memory remain unchanged.
Operation Affected flag(s)
Description
Decimal-Adjust accumulator addition accumulator value adjusted (Binary Coded Decimal) code. accumulator divided into nibbles. Each nibble adjusted code internal carry (AC1) will done nibble accumulator greater than adjustment done adding original value original value greater than carry set; otherwise original value remains unchanged. result stored data memory only carry flag affected. ACC.3~ACC.0 AC=1 then [m].3~[m].0 (ACC.3~ACC.0)+6, AC1=AC else [m].3~[m].0 (ACC.3~ACC.0), AC1=0 ACC.7~ACC.4+AC1 then [m].7~[m].4 ACC.7~ACC.4+6+AC1,C=1 else [m].7~[m].4 ACC.7~ACC.4+AC1,C=C
Operation
Affected flag(s) Description Operation Affected flag(s) DECA Description Operation Affected flag(s)
Decrement data memory Data specified data memory decremented [m]-1
Decrement data memory place result accumulator Data specified data memory decremented leaving result accumulator. contents data memory remain unchanged. [m]-1
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HALT Description Enter power down mode This instruction stops program execution turns system clock. contents registers retained. prescaler cleared. power down (PD) time-out (TO) cleared. PC+1
Operation
Affected flag(s) Description Operation Affected flag(s) INCA Description Operation Affected flag(s) addr Description Operation Affected flag(s) A,[m] Description Operation Affected flag(s)
Increment data memory Data specified data memory incremented [m]+1
Increment data memory place result accumulator Data specified data memory incremented leaving result accumulator. contents data memory remain unchanged. [m]+1
Directly jump program counter replaced with directly-specified address unconditionally, control passed this destination.
Move data memory accumulator contents specified data memory copied accumulator.
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Description Operation Affected flag(s) [m],A Description Operation Affected flag(s) Description Operation Affected flag(s) A,[m] Description Operation Affected flag(s) Description Operation Affected flag(s) A,[m] Description Operation Affected flag(s) Move immediate data accumulator 8-bit data specified code loaded into accumulator.
Move accumulator data memory contents accumulator copied specified data memory (one data memories).
operation operation performed. Execution continues with next instruction. PC+1
Logical accumulator with data memory Data accumulator specified data memory (one data memories) perform bitwise logical_OR operation. result stored accumulator.
Logical immediate data accumulator Data accumulator specified data perform bitwise logical_OR operation. result stored accumulator.
Logical data memory with accumulator Data data memory (one data memories) accumulator perform bitwise logical_OR operation. result stored data memory.
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Description Operation Affected flag(s) Description Operation Affected flag(s) RETI Description Operation Affected flag(s) Description Operation Affected flag(s) Description Operation Affected flag(s) Return from subroutine program counter restored from stack. This 2-cycle instruction. Stack
Return place immediate data accumulator program counter restored from stack accumulator loaded with specified 8-bit immediate data. Stack
Return from interrupt program counter restored from stack, interrupts enabled setting bit. enable master (global) interrupt bit. Stack
Rotate data memory left contents specified data memory rotated left with rotated into [m].(i+1) [m].i; [m].i:bit data memory (i=0~6) [m].0 [m].7
Rotate data memory left place result accumulator Data specified data memory rotated left with rotated into leaving rotated result accumulator. contents data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit data memory (i=0~6) ACC.0 [m].7
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Description Operation Rotate data memory left through carry contents specified data memory carry flag rotated left. replaces carry bit; original carry flag rotated into position. [m].(i+1) [m].i; [m].i:bit data memory (i=0~6) [m].0 [m].7
Affected flag(s) RLCA Description
Rotate left through carry place result accumulator Data specified data memory carry flag rotated left. replaces carry original carry flag rotated into position. rotated result stored accumulator contents data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit data memory (i=0~6) ACC.0 [m].7
Operation
Affected flag(s) Description Operation Affected flag(s) Description Operation Affected flag(s) Description Operation
Rotate data memory right contents specified data memory rotated right with rotated [m].i [m].(i+1); [m].i:bit data memory (i=0~6) [m].7 [m].0
Rotate right place result accumulator Data specified data memory rotated right with rotated into leaving rotated result accumulator. contents data memory remain unchanged. ACC.(i) [m].(i+1); [m].i:bit data memory (i=0~6) ACC.7 [m].0
Rotate data memory right through carry contents specified data memory carry flag together rotated right. replaces carry bit; original carry flag rotated into position. [m].i [m].(i+1); [m].i:bit data memory (i=0~6) [m].7 [m].0
Affected flag(s) Rev. 1.00 2002
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RRCA Description Rotate right through carry place result accumulator Data specified data memory carry flag rotated right. replaces carry original carry flag rotated into position. rotated result stored accumulator. contents data memory remain unchanged. ACC.i [m].(i+1); [m].i:bit data memory (i=0~6) ACC.7 [m].0
Operation
Affected flag(s) A,[m] Description Operation Affected flag(s) SBCM A,[m] Description Operation Affected flag(s) Description
Subtract data memory carry from accumulator contents specified data memory complement carry flag subtracted from accumulator, leaving result accumulator. ACC+[m]+C
Subtract data memory carry from accumulator contents specified data memory complement carry flag subtracted from accumulator, leaving result data memory. ACC+[m]+C
Skip decrement data memory contents specified data memory decremented result next instruction skipped. result following instruction, fetched during current instruction execution, discarded dummy cycle replaced proper instruction cycles). Otherwise proceed with next instruction cycle). Skip ([m]-1)=0, ([m]-1)
Operation Affected flag(s)
SDZA Description
Decrement data memory place result ACC, skip contents specified data memory decremented result next instruction skipped. result stored accumulator data memory remains unchanged. result following instruction, fetched during current instruction execution, discarded dummy cycle replaced proper instruction cycles). Otherwise proceed with next instruction cycle). Skip ([m]-1)=0, ([m]-1)
Operation Affected flag(s)
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Description Operation Affected flag(s) [m]. Description Operation Affected flag(s) Description data memory Each specified data memory
data memory specified data memory [m].i
Skip increment data memory contents specified data memory incremented result following instruction, fetched during current instruction execution, discarded dummy cycle replaced proper instruction cycles). Otherwise proceed with next instruction cycle). Skip ([m]+1)=0, ([m]+1)
Operation Affected flag(s)
SIZA Description
Increment data memory place result ACC, skip contents specified data memory incremented result next instruction skipped result stored accumulator. data memory remains unchanged. result following instruction, fetched during current instruction execution, discarded dummy cycle replaced proper instruction cycles). Otherwise proceed with next instruction cycle). Skip ([m]+1)=0, ([m]+1)
Operation Affected flag(s)
[m].i Description
Skip data memory specified data memory next instruction skipped. data memory following instruction, fetched during current instruction execution, discarded dummy cycle replaced proper instruction cycles). Otherwise proceed with next instruction cycle). Skip
Operation Affected flag(s)
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A,[m] Description Operation Affected flag(s) SUBM A,[m] Description Operation Affected flag(s) Description Operation Affected flag(s) SWAP Description Operation Affected flag(s) SWAPA Description Operation Affected flag(s) Subtract data memory from accumulator specified data memory subtracted from contents accumulator, leaving result accumulator. ACC+[m]+1
Subtract data memory from accumulator specified data memory subtracted from contents accumulator, leaving result data memory. ACC+[m]+1
Subtract immediate data from accumulator immediate data specified code subtracted from contents accumulator, leaving result accumulator. ACC+x+1
Swap nibbles within data memory low-order high-order nibbles specified data memory data memories) interchanged. [m].3~[m].0 [m].7~[m].4
Swap data memory place result accumulator low-order high-order nibbles specified data memory interchanged, writing result accumulator. contents data memory remain unchanged. ACC.3~ACC.0 [m].7~[m].4 ACC.7~ACC.4 [m].3~[m].0
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Description Skip data memory contents specified data memory following instruction, fetched during current instruction execution, discarded dummy cycle replaced proper instruction cycles). Otherwise proceed with next instruction cycle). Skip [m]=0
Operation Affected flag(s)
Description
Move data memory ACC, skip contents specified data memory copied accumulator. contents following instruction, fetched during current instruction execution, discarded dummy cycle replaced proper instruction cycles). Otherwise proceed with next instruction cycle). Skip [m]=0
Operation Affected flag(s)
[m].i Description
Skip data memory specified data memory following instruction, fetched during current instruction execution, discarded dummy cycle replaced proper instruction cycles). Otherwise proceed with next instruction cycle). Skip [m].i=0
Operation Affected flag(s)
TABRDC Description Operation Affected flag(s) TABRDL Description Operation Affected flag(s)
Move code (current page) TBLH data memory byte code (current page) addressed table pointer (TBLP) moved specified data memory high byte transferred TBLH directly. code (low byte) TBLH code (high byte)
Move code (last page) TBLH data memory byte code (last page) addressed table pointer (TBLP) moved data memory high byte transferred TBLH directly. code (low byte) TBLH code (high byte)
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A,[m] Description Operation Affected flag(s) XORM A,[m] Description Operation Affected flag(s) Description Operation Affected flag(s) Logical accumulator with data memory Data accumulator indicated data memory perform bitwise logical Exclusive_OR operation result stored accumulator.
Logical data memory with accumulator Data indicated data memory accumulator perform bitwise logical Exclusive_OR operation. result stored data memory. flag affected.
Logical immediate data accumulator Data accumulator specified data perform bitwise logical Exclusive_OR operation. result stored accumulator. flag affected.
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Holtek Semiconductor Inc. (Headquarters) No.3, Creation Science-based Industrial Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Sales Office) 11F, No.576, Sec.7 Chung Hsiao Rd., Taipei, Taiwan Tel: 886-2-2782-9635 Fax: 886-2-2782-9636 Fax: 886-2-2782-7128 (International sales hotline) Holtek Semiconductor (Hong Kong) Ltd. RM.711, Tower Cheung Plaza, Cheung Rd., Kowloon, Hong Kong Tel: 852-2-745-8288 Fax: 852-2-742-8657 Holtek Semiconductor (Shanghai) Inc. Floor, Building No.889, Shan Rd., Shanghai, China Tel: 021-6485-5560 Fax: 021-6485-0313 http://www.holtek.com.cn Holmate Semiconductor, Inc. 48531 Warm Springs Boulevard, Suite 413, Fremont, 94539 Tel: 510-252-9880 Fax: 510-252-9885 http://www.holmate.com Copyright 2002 HOLTEK SEMICONDUCTOR INC. information appearing this Data Sheet believed accurate time publication. However, Holtek assumes responsibility arising from specifications described. applications mentioned herein used solely purpose illustration Holtek makes warranty representation that such applications will suitable without further modification, recommends products application that present risk human life malfunction otherwise. Holtek reserves right alter products without prior notification. most up-to-date information, please visit site http://www.holtek.com.tw.
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Operating voltage: program memory data memory HALT function wake-up fe

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