FlexQTMIII Plus Volt Synchronous x10/x20 First-In/First-Out Queue
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FQV202113 FQV202103 FQV20293 FQV20283 FQV20273 FQV20263 FQV20243
FlexQTMIII Plus
Volt Synchronous x10/x20 First-In/First-Out Queue
Memory Organization
262,144 524,286 131,072 262,144 65,536 131,072 32,768 65,536
Device
FQV202113 FQV202103 FQV20293 FQV20283
Memory Organization
16,384 32,768 8,192 16,384 4,096 8,192 2,048 4,096
Device
FQV20273 FQV20263 FQV20253 FQV20243
Features
Industry leading First-In/First-Out Queues 166MHz) Write cycle time 6.0ns independent Read cycle time (Data Setup time 2.0ns) Read cycle time 6.0ns independent Write cycle time (Data Access time 4.0ns) User selectable input output port bus-sizing Endian/Little Endian user selectable byte representation 3.3V power supply input tolerant control data input pins output tolerant flags data output pins Master Reset clears previously programmed configurations including Write Read pointers Partial Reset clears Write Read pointers maintains previously programmed configurations First Word Fall Through (FWFT) Standard Timing modes Presets eight different Almost Full Almost Empty offset values Parallel/Serial programming PRAF PRAE offset values Programmable 8-bit 10-bit parallel programming modes offset values Full, Empty, Almost Full, Almost Empty, Half Full indicators PRAF PRAE operates either synchronous asynchronous modes Asynchronous output enable tri-state data output drivers Data retransmission with programmable zero normal latency modes Available package: Plastic Thin Quad Flat Pack (TQFP) (0°C 70°C) Commercial operating temperature available cycle time 6.0ns above (-40°C 85°C) Industrial operating temperature available cycle time 7.5ns above
Product Description
HBA's FlexQIII Plus offers industry leading FIFO queuing bandwidth Gbps), with wide range memory configurations (from 2,048 262,144 4,096 524,286 10). System designer full flexibility implementing deeper wider queues using FWFT mode width expansion features. Full, Empty, Half-Full indicators allow easy handshaking between transmitters receivers. User programmable Almost Full Almost Empty (Parallel/Serial) indicators allow implementation virtual queue depths. tolerant input output pins allow easy interfacing with devices operating higher voltage levels. Asynchronous Output Enable configures tri-state data output drivers. Independent Write Read controls provide rate-matching capability. Master Reset clears previously programmed configurations providing pulse MRST pin. addition, Write Read pointers queue initialized zero. Partial Reset will alter previously programmed configurations will initialize Write Read pointers zero. FWFT mode, first data written into queue appears output data after specified latency period high transition RCLK. Subsequent reads from queue will require asserting This feature useful when implementing depth expansion functions. this mode, DRDY QRDY used instead FULL EMPTY respectively.
3F3P1020A 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
2002
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FQV202113 FQV202103 FQV20293 FQV20283 FQV20273 FQV20263 FQV20243
FlexQTMIII Plus Product Description (Continued)
Standard mode, always assert whenever read operation. FULL EMPTY used instead DRDY QRDY respectively. matching feature available with following configurations: Input Width Output Width
addition, Endian Select available implementing byte re-ordering data outputs. Eight different default offset values available Almost Full PRAF Almost Empty PRAE flags. Parallel Serial programming these offset values provide total flexibility other than pre-defined default values. Both 8-bit 10-bit parallel programming modes offset values selected convenience.
PRAF PRAE HALF available either FWFT Standard mode. PRAF PRAE operate either synchronous asynchronous modes.
time, data previously read from queue retransmitted asserting high transition RCLK retransmit operation. Retransmit initializes Read pointer zero. Hence, re-reads will always start from physical (Read pointer zero), location queue. Both zero normal latency timing modes available retransmit operation. These FlexQIII Plus devices have power consumption, hence minimizing system power requirements. addition, industry standard Plastic TQFP offered save system board space. These queues ideal applications such data communication, telecommunication, graphics, multiprocessing, test equipment, network switching, etc.
3F3P1020A 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
2002
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FQV202113 FQV202103 FQV20293 FQV20283 FQV20273 FQV20263 FQV20243
FlexQTMIII Plus
Block Diagram Single Synchronous Queue 262,144 131,072 65,536 32,768 16,384 8,192 4,096 2,048 524,286 262,144 131,072 65,536 32,768 16,384 8,192 4,096
PARTIAL RESET PRST
MASTER RESET MRST)
READ CLOCK (RCLK) WRTIE CLOCK (WCLK) WRITE ENABLE WEN) LOAD LOAD) DATA SERIAL DATA ENABLE SDEN FIRST WORD FALL THROUGH/ SERIAL DATA INPUT (FWFT/SDI) FULL FLAG INPUT READY FULL DRDY PROGRAMMABLE ALMOST-FULL (PRAF) FQV202113 FQV202103 FQV20293 FQV20283 FQV20273 FQV20263 FQV20253 FQV20243 READ ENABLE OUTPUT ENABLE DATA RETRANSMIT EMPTY FLAG OUTPUT READY (EMPTY QRDY PROGRAMMABLE ALMOSTEMPTY PRAE HALF-FULL FLAG HALF BIG-ENDIAN LITTLE-ENDIAN INTERSPERSED NON-INTERSPERSED PARITY (IPAR)
MATCHING (BM1)
MATCHING (BM0)
Figure Single Device Configuration Signal Flow Diagram
3F3P1020A 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
2002
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FQV202113 FQV202103 FQV20293 FQV20283 FQV20273 FQV20263 FQV20243
FlexQTMIII Plus
WCLK IPAR LOAD SDEN FWFT/SDI
Write Control Logic
FULL DRDY PRAF EMPTY/ QRDY Flag Logic
Offset Register
Write Pointer
PRAE HALF FWFT/SDI
PFS1 PFS0
19-0 x20,
Input Register
SRAM
Output Register
Output Buffer
19-0 x20,
Read Pointer
Read Control Logic
Reset
Configuration
RETZL RCLK
MRST PRST
Figure Device Architecture
3F3P1020A 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
2002
Page
FQV202113 FQV202103 FQV20293 FQV20283 FQV20273 FQV20263 FQV20243
FlexQTMIII Plus
EMPTY/QRDY
FWFT/SDI
FULL/DRDY
WCLK
RETZL
LOAD
MRST
PRAE
RCLK
HALF
PRAF
DNC1
DNC1
IPAR
DNC1
PRST
PFS0
PFS1
Index
SDEN DNC1 DNC1 DNC1 DNC1 DNC1 DNC1 DNC1 DNC1 DNC1 DNC1 DNC1 DNC1 DNC1 DNC1
DNC1 DNC1 DNC1 DNC1 DNC1 DNC1 DNC1 DNC1 DNC1 DNC1 DNC1 DNC1 DNC1 DNC1 DNC1
DNC1
DNC1
DNC1
DNC1
DNC1
DNC1
DNC1
DNC1
DNC1
DNC1
TQFP (Drw PF-03A: Order code: View NOTES:
Connect.
Figure Device
3F3P1020A 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
2002
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FQV202113 FQV202103 FQV20293 FQV20283 FQV20273 FQV20263 FQV20243
FlexQTMIII Plus
Name Symbol Input/Output Description
Master Reset required initialize Write Read pointers first position queue setting MRST low. Standard mode, FULL PRAF will high; EMPTY PRAE will low. FWFT mode, DRDY will QRDY will high. PRAF PRAE will same state Standard mode. both modes, data outputs will low. Previous programmed configurations will maintained. Partial Reset required initialize Write Read pointers first position queue setting PRST low. Standard mode, FULL PRAF will high; EMPTY PRAE will low. FWFT mode, DRDY will QRDY will high. PRAF PRAE will same state Standard mode. both modes, data outputs will low. Previous programmed configurations will maintained. Writes data into queue during high transitions WCLK low. Controls write operation into queue offset registers during high transition WCLK. During Master Reset, LOAD select parallel programming eight default-offset values. LOAD high select serial programming eight default offset values. After Master Reset, LOAD controls write/read, to/from offset registers during high transition WCLK/RCLK respectively. conjunction with During Master Reset, select eight default-offset values. conjunction with LOAD PFS1. During Master Reset, select eight default-offset values. conjunction with LOAD PFS0.
Master Reset
MRST
Input
Partial Reset
PRST
Input
Write Clock Write Enable
WCLK
Input Input
Load Enable
LOAD
Input
06,10,14,16, 18,20,23,26, 28,30,32,34, 39,41,46,47, 48,51,52,53.
Default Programming Default Programming
PFS1 PFS0
Input Input
Data Inputs
D19-0
Input
wide input data bus.
Read Clock Read Enable
RCLK
Input Input
Reads data from queue during high transitions RCLK low. Controls read operation from queue offset registers during high transition RCLK. Setting activates data output drivers. Setting high deactivates data output drivers (High-Z).
Output Enable
Input
Table Descriptions
3F3P1020A 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
2002
Page
FQV202113 FQV202103 FQV20293 FQV20283 FQV20273 FQV20263 FQV20243
FlexQTMIII Plus
108,107,105,98, 96,92,91,87, 81,77,76,74, 73,72,63,62, 59,58,56,55
Name
Symbol
Input/Output
Description
Data Outputs
Q19-0
Output
wide output data bus.
First Word Fall Through/Serial Data Input
FWFT/SDI
Input
Selects FWFT timing Standard timing mode during Master Reset. After Master Reset, serial programming selected LOAD high), FWFT/SDI used serial data input offset registers. Serial data written during high transition WCLK. conjunction with SDEN serial programming selected, setting SDEN LOAD enables serial data input written into offset registers during high transition WCLK. During Master Reset, select input width high select input width. During Master Reset, select output width high select output width. During Master Reset, high select byte reordering data outputs select byte re-ordering data outputs. Data previously read from queue retransmitted asserting high transition RCLK retransmit operation. Retransmit initializes Read pointer zero. Hence, re-reads will always start from physical (Read pointer zero) location queue. During Master Reset, RETZL select zero latency retransmit RETZL high select normal latency retransmit. Queue full when FULL goes during high transition WCLK. This prohibits further writes into queue. FWFT mode, queue full when DRDY goes high during high transition WCLK. This prohibits further writes into queue. Queue empty when EMPTY goes during high transition RCLK. This prohibits further reads from queue. FWFT mode, queue empty when QRDY goes high during high transition RCLK. This prohibits further reads from queue. During Master Reset, IPAR select 10-bit parallel programming mode IPAR high select 8bit parallel programming mode.
Serial Data Input Enable Matching Matching Endian Select
SDEN
Input
Input
Input
Input
Retransmit
Input
Zero Latency Retransmit
RETZL
Input
Full/Data Input Ready Flag
FULL DRDY
Output
Empty/Data Output Ready Flag
EMPTY QRDY
Output
Interspersed Parity
IPAR
Input
Table Descriptions (Continued)
3F3P1020A 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
2002
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FQV202113 FQV202103 FQV20293 FQV20283 FQV20273 FQV20263 FQV20243
FlexQTMIII Plus
Name
Synchronous Partial Flag Mode
Symbol
Input/Output
Input
Description
During Master Reset, high select Synchronous Partial Flag mode select Asynchronous Partial Flag mode. Queue almost full when PRAF goes during high transition WCLK. Default (Full-offset) programmed offset values determine status PRAF Queue almost empty when PRAE goes during high transition RCLK. Default (Empty +offset) programmed offset values determine status PRAE Queue more than half full when HALF goes low. Triggered both WCLK RCLK.
Almost Full
PRAF
Output
Almost Empty
PRAE
Output
07,08,09,12, 13,15,17,19, 21,25,27,29, 31,33,36,37, 38,40,42,43, 65,68,69,70, 71,75,79,80, 83,84,85,88, 89,94,95,97, 100,101,103, 104,118,120, 122. 04,11,24,35, 49,50,60,61, 66,67,78,86, 93,99,106,121, 123,135,136. 03,22,44,45, 54,5764,82, 90,102,113, 114,118,120, 126,128,132, 133,138,139
Half Full
HALF
Output
Connect
connect.
Power
3.3V power supply.
Ground
Ground.
Table Descriptions (Continued)
3F3P1020A 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
2002
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FQV202113 FQV202103 FQV20293 FQV20283 FQV20273 FQV20263 FQV20243
FlexQTMIII Plus
Symbol VTERM TSTG IOUT
Rating Terminal Voltage with respect Storage Temperature Output Current
Com'l Ind'l -0.5 +125
Unit
NOTES:
Absolute Ratings reference only. Permanent damage device occur extended period operation outside this range. Standard operation should fall within Recommended Operating Conditions.
Table Absolute Maximum Ratings
FQV202113, FQV202103FQV20293, FQV20283 FQV20273, FQV20263, FQV20253, FQV20243 Commercial Clock 6ns, 7.5ns, 10ns Industrial Clock 7.5ns, 10ns, 15ns
Symbol Parameter Recommended Operating Conditions
Supply Voltage Com'l Ind'l Supply Voltage Input High Voltage Com'l Ind'l Input Voltage Com'l Ind'l Operating Temperature Commercial Operating Temperature Industrial Input Leakage Current (any input) Output Leakage Current Output Logic Voltage, IOH=-2mA Output Logic Voltage, Active Power Supply Current (x10 Input Output) Active Power Supply Current (x20 Input Output) Standby Current
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
3.15
3.45
3.15
3.45
Electrical Characteristics
ILI(1)
Power Consumption
ICC1(2,3) ICC1(2,3) ICC2(4)
Table Specifications
3F3P1020A 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
2002
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FQV202113 FQV202103 FQV20293 FQV20283 FQV20273 FQV20263 FQV20243
FlexQTMIII Plus
Capacitance 100MHz Ambient Temperature (25°C) Symbol Parameter
CIN(2) COUT(2,4)
NOTES:
Measurement with 0.4<=VIN<=Vcc. With output tri-stated High). Icc(1,2) measured with WCLK RCLK MHz. Design simulated, tested.
Conditions
VIN= VOUT=
Max.
Unit
Input Capacitance Output Capacitance
Table Specifications (Continued)
3F3P1020A 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
2002
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FQV202113 FQV202103 FQV20293 FQV20283 FQV20273 FQV20263 FQV20243
FlexQTMIII Plus
Commercial FQV202113-6 FQV202103-6 FQV20293-6 FQV20283-6 FQV20273-6 FQV20263-6 FQV20253-6 FQV20243-6 Symbol tWCLK tWCLKH tWCLKL tRCLK tRCLKH tRCLKL tENS tENH tRST tRSTS tRSTR tRSTF tOLZ tOHZ tFULL tEMPTY tPRAFS tPRAES tSKEW1 tSKEW2 tLOADS tLOADH Parameter Clock Cycle Frequency Data Access Time Write Clock Cycle Time Write Clock High Time Write Clock Time Read Clock Cycle Time Read Clock High Time Read Clock Time Data Set-up Time Data Hold Time Enable Set-up Time Enable Hold Time Reset Pulse Width
Commercial Industrial FQV202113-7.5 FQV202103-7.5 FQV20293-7.5 FQV20283-7.5 FQV20273-7.5 FQV20263-7.5 FQV20253-7.5 FQV20243-7.5 Min. Max. FQV202113-10 FQV202103-10 FQV20293-10 FQV20283-10 FQV20273-10 FQV20263-10 FQV20253-10 FQV20243-10 Min. Max. Unit
Min.
Max.
Reset Set-up Time Reset Recovery Time Reset Flag Output Time Output Enable Output Low-Z Output Enable Output Valid Output Enable Output High-Z(1) Write Clock Full Flag Read Clock Empty Flag Write Clock Synchronous Almost-Full Flag Read Clock Synchronous Almost-Empty Flag Skew time between Read Clock Write Clock Full Flag Empty Flag Skew time between Read Clock Write Clock PRAE PRAF Load Setup Time Load Hold Time
Table Electrical Characteristics
3F3P1020A 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
2002
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FQV202113 FQV202103 FQV20293 FQV20283 FQV20273 FQV20263 FQV20243
FlexQTMIII Plus
Commercial FQV202113-6 FQV202103-6 FQV20293-6 FQV20283-6 FQV20273-6 FQV20263-6 FQV20253-6 FQV20243-6 Symbol tRETS tHALF tPRAFA tPRAEA Parameter Retransmit Setup Time Clock HALF Write Clock Asynchronous Programmable Almost-Full Flag Read Clock Asynchronous Programmable Almost-Empty Flag Min. Max. Commercial Industrial FQV202113-7.5 FQV202103-7.5 FQV20293-7.5 FQV20283-7.5 FQV20273-7.5 FQV20263-7.5 FQV20253-7.5 FQV20243-7.5 Min. Max. 12.5 12.5 12.5 FQV202113-10 FQV202103-10 FQV20293-10 FQV20283-10 FQV20273-10 FQV20263-10 FQV20253-10 FQV20243-10 Min. Max. Unit
NOTES: Design simulated, tested. Table Electrical Characteristics (Continued)
3F3P1020A 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
2002
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FQV202113 FQV202103 FQV20293 FQV20283 FQV20273 FQV20263 FQV20243
FlexQTMIII Plus
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load, clock 6ns, 7.5ns, 10ns
3.0V 1.5V 1.5V Refer Figure
Table Test Condition
Vcc/2
Figure Test Load clock 6ns, 7.5ns, 10ns
3F3P1020A 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
2002
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FQV202113 FQV202103 FQV20293 FQV20283 FQV20273 FQV20263 FQV20243
FlexQTMIII Plus Functions
MRST
Master Reset required initialize Write Read pointers first position queue setting MRST low. Standard mode, FULL PRAF will high; EMPTY PRAE will low. FWFT mode, DRDY will QRDY will high. PRAF PRAE will same state Standard mode. both modes, data outputs will low. Previous programmed configurations will maintained. Partial Reset required initialize Write Read pointers first position queue setting PRST low. Standard mode, FULL PRAF will high; EMPTY PRAE will low. FWFT mode, DRDY will QRDY will high. PRAF PRAE will same state Standard mode. both modes, data outputs will low. Previous programmed configurations will maintained.
PRST
WCLK
Writes data into queue during high transitions WCLK activated. Synchronizes FULL DRDY PRAF flags. WCLK RCLK independent each other. Controls write operation into queue offset registers during high transition WCLK. During Master Reset, LOAD select parallel programming eight default offset values. LOAD high select serial programming eight default offset values. After Master Reset, LOAD controls write/read, to/from offset registers during high transition WCLK/RCLK respectively parallel programming. conjunction with During programming offset registers, PRAF PRAE flag status invalid. Serial programming, LOAD used enable serial loading offset registers together with SDEN Refer Figure Table details. During Master Reset, select eight default-offset values. conjunction with LOAD PFS1. Refer Table details. During Master Reset, select eight default-offset values. conjunction with LOAD PFS0. Refer Table details. wide input data bus. Reads data from queue during high transitions RCLK low. Synchronizes EMPTY QRDY PRAE flags. RCLK WCLK independent each other. Reads data from queue during high transitions RCLK low. This also advances Read pointer queue. Setting activates data output drivers. Setting high deactivates data output drivers (High-Z). does control advancement Read pointer. wide output data bus. Selects FWFT timing Standard timing mode during Master Reset. After Master Reset, serial programming selected LOAD high), FWFT/SDI used serial data input offset registers. Serial data written during high transition WCLK. conjunction with SDEN FWFT mode, DRDY QRDY used instead FULL EMPTY Refer Table flags status. Standard mode, FULL EMPTY used instead DRDY QRDY Refer Table flags status. serial programming selected, setting SDEN LOAD enables serial data written into offset registers during high transition WCLK. During serial programming, PRAF PRAE flags status invalid. Refer Figure details.
LOAD
PFS1
PFS0 D19-0 RCLK
Q19-0 FWFT/SDI
SDEN
3F3P1020A 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
2002
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FQV202113 FQV202103 FQV20293 FQV20283 FQV20273 FQV20263 FQV20243
FlexQTMIII Plus Functions (Continued)
During Master Reset, setting selects input width. high selects input width. Refer Table details. During Master Reset, select output width. high select output width. Refer Table details. During Master Reset, high select byte re-ordering data outputs select byte re-ordering data outputs. must static throughout device operation. Refer Table details. Data previously read from queue retransmitted asserting high transition RCLK retransmit operation. Retransmit initializes Read pointer zero. Hence, re-reads will always start from physical (Read pointer zero), location queue. Refer Diagram details. During Master Reset, RETZL select zero latency retransmit RETZL high select normal latency retransmit. Standard mode, queue full when FULL goes during high transition WCLK. This prohibits further writes into queue prevents advancement Write pointer. FWFT mode, queue full when DRDY goes high during high transition WCLK. This prohibits further writes into queue prevents advancement Write pointer. Refer Table behavior FULL DRDY Standard mode, queue empty when EMPTY goes during high transition RCLK. This prohibits further reads from queue prevents advancement Read pointer. FWFT mode, queue empty when QRDY goes during high transition RCLK. This prohibits further reads from queue prevents advancement Read pointer. Refer Table behavior EMPTY QRDY During Master Reset, IPAR select 10-bit parallel programming mode IPAR high select 8-bit parallel programming mode. 10-bit mode, 10-bit wide data input/output width used storing/fetching offset values. 8-bit mode, 8-bit wide data input/output used storing/fetching offset values. During Master Reset, high select Synchronous Partial Flag mode select Asynchronous Partial Flag mode. Synchronous mode, PRAF PRAE synchronous WCLK RCLK respectively. Asynchronous mode, WCLK synchronizes assertion PRAF deassertion PRAE RCLK synchronizes assertion PRAE de-assertion PRAE Synchronous mode, queue almost full when PRAF goes during high transition WCLK. Default (Full-offset) programmed offset values determine status PRAF Asynchronous mode, PRAF triggered both WCLK RCLK. Refer Table behavior PRAF Synchronous mode, queue almost empty when PRAE goes during high transition RCLK. Default (Empty+offset) programmed offset values determine status PRAE Asynchronous timing mode, PRAF triggered both WCLK RCLK. Refer Table behavior PRAE Queue more than half full when HALF goes during high transition WCLK. HALF goes high during high transition RCLK when queue less than half full. Refer Table details.
RETZL
FULL DRDY
EMPTY QRDY
IPAR
PRAF
PRAE
HALF
3F3P1020A 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
2002
Page
FQV202113 FQV202103 FQV20293 FQV20283 FQV20273 FQV20263 FQV20243
FlexQTMIII Plus
FQV20283 FQV20273 FQV20263 FQV20253 FQV20243 Selection Sequence
LOAD
SDEN
WCLK
RCLK
Parallel write offset registers: Empty Offset (Low Byte) Empty Offset (High Byte) Full Offset (Low Byte) Full Offset (High Byte) Parallel read from offset registers: Empty Offset (Low Byte) Empty Offset (High Byte) Full Offset (Low Byte) Full Offset (High Byte)
Mode Serial shift into registers: bits FQV20283 bits FQV20273 bits FQV20263 bits FQV20253 bits FQV20243 each rising WCLK edge Starting with Empty Offset (Low Byte) Ending with Full Offset (High Byte)
Parallel write registers: PRAE Byte PRAE High Byte PRAF Byte PRAF High Byte Parallel read from registers: PRAE Byte PRAE High Byte PRAF Byte PRAF High Byte
Other Modes Serial shift into registers: bits FQV20283 bits FQV20273 bits FQV20263 bits FQV20253 bits FQV20243 each rising WCLK edge Starting with Empty Offset (Low Byte) Ending with Full Offset (High Byte)
Operation Write Memory
Read Memory Operation
Figure Programmable Flag Offset Programming Sequence (FQV20283, FQV20273, FQV20263, FQV20253 FQV20243)
3F3P1020A 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
2002
Page
FQV202113 FQV202103 FQV20293 FQV20283 FQV20273 FQV20263 FQV20243
FlexQTMIII Plus
LOAD
SDEN
WCLK
RCLK
FQV202113 FQV202103 FQV20293 Selection Sequence
Parallel write offset registers: Empty Offset (Low Byte) Empty Offset (Mid Byte) Empty Offset (High Byte) Full Offset (Low Byte) Full Offset (Mid Byte) Full Offset (High Byte) Parallel read from offset registers: Empty Offset (Low Byte) Empty Offset (Mid Byte) Empty Offset (High Byte) Full Offset (Low Byte) Full Offset (Mid Byte) Full Offset (High Byte)
Mode Serial shift into registers: bits FQV202113 bits FQV202103 bits FQV20293 each rising WCLK edge Starting with Empty Offset (Low Byte) Ending with Full Offset (High Byte)
Parallel write registers: PRAE Byte PRAE Byte PRAE High Byte PRAF Byte PRAF Byte PRAF High Byte Parallel read from registers: PRAE Byte PRAE Byte PRAE High Byte PRAF Byte PRAF Byte PRAF High Byte
Other Modes Serial shift into registers: bits FQV202113 bits FQV202103 bits FQV20293 each rising WCLK edge Starting with Empty Offset (Low Byte) Ending with Full Offset (High Byte)
Operation Write Memory
Read Memory Operation
Figure Programmable Flag Offset Programming Sequence (FQV202113, FQV202103, FQV20293)
3F3P1020A 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
2002
Page
FQV202113 FQV202103 FQV20293 FQV20283 FQV20273 FQV20263 FQV20243
FlexQTMIII Plus
Device
PRAF Programming (bits)
D/Q15 D/Q17 D/Q7 D/Q15 D/Q17 D/Q7 D/Q15 D/Q17 D/Q7 D/Q14 D/Q16 D/Q7 D/Q13 D/Q15 D/Q7 D/Q12 D/Q14 D/Q7 D/Q11 D/Q13 D/Q7 D/Q10 D/Q12 D/Q7 Non-IPAR IPAR Non-IPAR IPAR Non-IPAR IPAR Non-IPAR IPAR Non-IPAR IPAR Non-IPAR IPAR Non-IPAR IPAR Non-IPAR IPAR D/Q15
PRAE Programming (bits)
Non-IPAR IPAR Non-IPAR IPAR Non-IPAR IPAR Non-IPAR IPAR Non-IPAR IPAR Non-IPAR IPAR Non-IPAR IPAR Non-IPAR IPAR D/Q17 D/Q7 D/Q15 D/Q17 D/Q7 D/Q15 D/Q17 D/Q7 D/Q14 D/Q16 D/Q7 D/Q13 D/Q15 D/Q7 D/Q12 D/Q14 D/Q7 D/Q11 D/Q13 D/Q7 D/Q10 D/Q12 D/Q7
FQV202113 FQV202103 FQV20293 FQV20283 FQV20273 FQV20263 FQV20253 FQV20243
Condition Applies Write Cycle with input Width and/or Read Cycle with output Width
Device
PRAF Programming (bits)
D/Q7 Byte Byte High Byte Byte Byte High Byte Byte High Byte Byte High Byte Byte High Byte Byte High Byte Byte High Byte Byte High Byte D/Q7 D/Q1 D/Q7
PRAE Programming (bits)
D/Q7 D/Q7 D/Q1 D/Q7 D/Q7 D/Q7 D/Q7 D/Q7 D/Q6 D/Q7 D/Q5 D/Q7 D/Q4 D/Q7 D/Q3 D/Q7 D/Q2 Byte Byte High Byte Byte Byte High Byte Byte High Byte Byte High Byte Byte High Byte Byte High Byte Byte High Byte Byte High Byte
FQV202113
FQV202103
D/Q7 D/Q0 D/Q7 D/Q7 D/Q7 D/Q6 D/Q7 D/Q5 D/Q7 D/Q4 D/Q7 D/Q3 D/Q7 D/Q2
FQV20293 FQV20283 FQV20273 FQV20263 FQV20253 FQV20243
Condition Applies Write Cycle with input Width Read Cycle with output Width (except mode)
3F3P1020A 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
2002
Page
FQV202113 FQV202103 FQV20293 FQV20283 FQV20273 FQV20263 FQV20243
FlexQTMIII Plus
Device
PRAF Programming (bits)
D/Q7 Byte Byte High Byte Byte Byte High Byte Byte Byte High Byte Byte High Byte Byte High Byte Byte High Byte Byte High Byte Byte High Byte D/Q7 D/Q2 D/Q7
PRAE Programming (bits)
D/Q7 D/Q7 D/Q2 D/Q7 D/Q7 D/Q1 D/Q7 D/Q7 D/Q0 D/Q7 D/Q7 D/Q7 D/Q6 D/Q7 D/Q5 D/Q7 D/Q4 D/Q7 D/Q3 Byte Byte High Byte Byte Byte High Byte Byte Byte High Byte Byte High Byte Byte High Byte Byte High Byte Byte High Byte Byte High Byte
FQV202113
FQV202103
D/Q7 D/Q1 D/Q7
FQV20293
D/Q7 D/Q0 D/Q7 D/Q7 D/Q7 D/Q6 D/Q7 D/Q5 D/Q7 D/Q4 D/Q7 D/Q3
FQV20283 FQV20273 FQV20263 FQV20253 FQV20243
Condition Applies Write Cycle with input Width Read Cycle with output Width (only mode) Table Parallel Offset Write/Read Cycle Register Location
Device
FQV202113 FQV202103 FQV20293 FQV20283 FQV20273 FQV20263 FQV20253 FQV20243
Standard Mode
262,144 524,288 131,072 262,144 65,536 131,072 32,768 65,536 16,384 32,768 8,192 16,384 4,096 8,192 2,048 4,096
FWFT Mode
262,145 524,289 131,073 262,145 65,537,x 131,073 32,769 65,537 16,385 32,769 8,193 16,385 4,097 8,193 2,049 4,097
Table Maximum Depth Queue Standard FWFT Mode
3F3P1020A 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
2002
Page
FQV202113 FQV202103 FQV20293 FQV20283 FQV20273 FQV20263 FQV20243
FlexQTMIII Plus
Data Width Cycle PRAE Byte Cycle PRAE High Byte
D/Q9 D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0
Cycle PRAF Byte Cycle PRAF High Byte
FQV20293, FQV20283, FQV20273, FQV20263, FQV20253, FQV20243 Parallel Offset Write/Read Cycles Width Condtion Applies Write Cycle with input Width and/or Read Cycle output with Width (except FQV20293 mode)
Data Width Cycle PRAE Byte Cycle PRAE Byte Cycle PRAE High Byte
D/Q9 D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0
Cycle PRAF Byte Cycle PRAF Byte Cycle PRAF High Byte
FQV202113, FQV202103, FQV20293 Parallel Offset Write/Read Cycles Width Condtion Applies FQV20293 mode FQV202113, FQV202103 modes
3F3P1020A 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
2002
Page
FQV202113 FQV202103 FQV20293 FQV20283 FQV20273 FQV20263 FQV20243
FlexQTMIII Plus
Mode Bits Offset Registers
Other Modes Bits Offset Registers
bits FQV202113 bits FQV202103 bits FQV20293 bits FQV20283 bits FQV20273 bits FQV20263 bits FQV20253 bits FQV20243
Note: Don't Care applies unused bits
bits FQV202113 bits FQV202103 bits FQV20293 bits FQV20283 bits FQV20273 bits FQV20263 bits FQV20253 bits FQV20243
Note: Don't Care applies unused bits
Figure Parallel Offset Write/Read Cycle Diagram
3F3P1020A 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
2002
Page
FQV202113 FQV202103 FQV20293 FQV20283 FQV20273 FQV20263 FQV20243
FlexQTMIII Plus
Data Width Cycle PRAE Non-Interspersed Parity Interspersed Parity
D/Q19 D/Q18 D/Q17 D/Q16 D/Q15 D/Q14 D/Q13 D/Q12 D/Q11 D/Q10
D/Q9
D/Q8
D/Q7
D/Q6
D/Q5
D/Q4
D/Q3
D/Q2
D/Q1
D/Q0
Data Width Cycle PRAF Non-Interspersed Parity Interspersed Parity
D/Q19 D/Q18 D/Q17 D/Q16 D/Q15 D/Q14 D/Q13 D/Q12 D/Q11 D/Q10
D/Q9
D/Q8
D/Q7
D/Q6
D/Q5
D/Q4
D/Q3
D/Q2
D/Q1
D/Q0
FQV20293, FQV20283, FQV20273, FQV20263, FQV20253, FQV20243 Parallel Offset Write/Read Cycles Width Condtion Applies Write Cycle with input Width and/or Read Cycle output Width
Data Width Cycle PRAE Non-Interspersed Parity Interspersed Parity Cycle PRAE Non-Interspersed Parity Interspersed Parity
D/Q19 D/Q18 D/Q17 D/Q16 D/Q15 D/Q14 D/Q13 D/Q12 D/Q11 D/Q10
D/Q9
D/Q8
D/Q7
D/Q6
D/Q5
D/Q4
D/Q3
D/Q2
D/Q1
D/Q0
Cycle PRAF Non-Interspersed Parity Interspersed Parity Cycle PRAF Non-Interspersed Parity Interspersed Parity FQV202113, FQV202103 Parallel Offset Write/Read Cycles Width Condtion Applies Write Cycle with input Width and/or Read Cycle output Width
Figure Parallel Offset Write/Read Cycles Diagram (Continued)
3F3P1020A 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
2002
Page
FQV202113 FQV202103 FQV20293 FQV20283 FQV20273 FQV20263 FQV20243
FlexQTMIII Plus
FQV202113
y(1) (y+1) 262,144 262,145 [524,288-(x+1)] (524,288 524,287 524,288
FULL
PRAF
HALF
PRAE
EMPTY
FQV202103
FQV202113
FULL
PRAF
HALF
PRAE
EMPTY
y(1) (y+1) 131,072 131,073 [262,144-(x+1)] (262,144 262,143 262,144
FQV20293
FQV202103
FULL
PRAF
HALF
PRAE
EMPTY
y(1) (y+1) 65,536 65,537 [131,072-(x+1)] (131,072 131,071 131,072
FQV20283
FQV20293
FULL
PRAF
HALF
PRAE
EMPTY
y(1) (y+1) 32,768 32,769 [65,536-(x+1)] (65,536 65,535 65,536
FQV20273
FQV20283
FULL
PRAF
HALF
PRAE
EMPTY
y(1) (y+1) 16,384 16,385 [32,768-(x+1)] (32,768 32,767 32,768
NOTES:
Table values
Table Status Flags (Standard Mode)
3F3P1020A 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
2002
Page
FQV202113 FQV202103 FQV20293 FQV20283 FQV20273 FQV20263 FQV20243
FlexQTMIII Plus
FQV20263
FQV20273
FULL
PRAF
HALF
PRAE
EMPTY
y(1) (y+1) 8,192 8,193 [16,384-(x+1)] (16,384 16,383 16,384
FQV20253
FQV20263
FULL
PRAF
HALF
PRAE
EMPTY
y(1) (y+1) 4,096 4,097 [8,192-(x+1)] (8,192 8,191 8,192
FQV20243
FQV20253
FULL
PRAF
HALF
PRAE
EMPTY
y(1) (y+1) 2,048 2,049 [4,096-(x+1)] (4,096 4,095 4,096
FQV20243 y(1) (y+1) 1,024 1,025 [2,048-(x+1)] (2,048-x) 2,047 2,048
NOTES:
Table values
FULL
PRAF
HALF
PRAE
EMPTY
Table Status Flags (Standard Mode) (Continued)
3F3P1020A 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
2002
Page
FQV202113 FQV202103 FQV20293 FQV20283 FQV20273 FQV20263 FQV20243
FlexQTMIII Plus
FQV202113
y+1(1) (y+2) 262,145 262,146 [524,289-(x+1)] (524,289-x) 524,288 524,289
DRDY
PRAF
HALF
PRAE
QRDY
FQV202103
FQV202113
FULL
PRAF
HALF
PRAE
EMPTY
y+1(1) (y+2) 131,073 131,074 [262,145-(x+1)] (262,145-x) 262,144 262,145
FQV20293
FQV202103
FULL
PRAF
HALF
PRAE
EMPTY
y+1(1) (y+2) 65,637 65,638 [131,073-(x+1)] (131,073-x) 131,072 131,073
FQV20283
FQV20293
DRDY
PRAF
HALF
PRAE
QRDY
y+1(1) (y+2) 32,769 32,770 [65,537-(x+1)] (65,537 65,536 65,537
FQV20273
FQV20283
DRDY
PRAF
HALF
PRAE
QRDY
y+1(1) (y+2) 16,385 16,386 [32,769-(x+1)] (32,769-x) 32,768 32,769
NOTES: Table values
Table Status Flags (FWFT Mode)
3F3P1020A 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
2002
Page
FQV202113 FQV202103 FQV20293 FQV20283 FQV20273 FQV20263 FQV20243
FlexQTMIII Plus
FQV20263
FQV20273
DRDY
PRAF
HALF
PRAE
QRDY
y+1(1) (y+2) 8,193 8,194 [16,385-(x+1)] (16,385 16,384 16,385
FQV20253
FQV20263
FULL
PRAF
HALF
PRAE
EMPTY
y+1(1) (y+2) 4,097 4,098 [8,193-(x+1)] (8,193 8,192 8,193
FQV20243
FQV20253
FULL
PRAF
HALF
PRAE
EMPTY
y+1(1) (y+2) 2,049 2,050 [4,097-(x+1)] (4,097-x) 4,096 4,097
FQV20243
y+1(1) (y+2) 1,025 1,026 [2,049 -(x+1)] (2,049 2,048 2,049
NOTES:
Table values
DRDY
PRAF
HALF
PRAE
QRDY
Table Status Flags (FWFT Mode) (Continued)
3F3P1020A 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
2002
Page
FQV202113 FQV202103 FQV20293 FQV20283 FQV20273 FQV20263 FQV20243
FlexQTMIII Plus
Width
D/Q19
Byte Byte Byte
D/Q9
Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte
Sequence
Write Read Write Read Read Write Write Read Write Write Read Read Write Read Write Read Read Write Write Read
Byte
Byte Byte Byte
Byte
Table Bus-Matching Table
3F3P1020A 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
2002
Page
FQV202113 FQV202103 FQV20293 FQV20283 FQV20273 FQV20263 FQV20243
FlexQTMIII Plus
LOAD
PFS0
PFS1
FQV20273 FQV20263 FQV20253 FQV20243 Offsets
1,023
LOAD
PFS0
PFS1
FQV20283 Offsets Other Modes Mode
16,383 8,191 4,095 1,023 2,047
FQV202113 FQV202103 FQV20293 Offsets
16,383 8,191 4,095 1,023 2,047
NOTES:
1,023
PRAF offset, PRAE offset.
Table Default Programmable Flag Offsets
3F3P1020A 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
2002
Page
FQV202113 FQV202103 FQV20293 FQV20283 FQV20273 FQV20263 FQV20243
FlexQTMIII Plus Timing Diagrams
FT/SDI PFS1/PFS0 RSTS 1/BM RETZL IPAR
RSTR
RSTR
RSTR
RSTR
SDEN FULL FULL DRDY PRAE PRAF
Diagram Master Reset Timing
3F3P1020A 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
2002
Page
FQV202113 FQV202103 FQV20293 FQV20283 FQV20273 FQV20263 FQV20243
FlexQTMIII Plus
tRST
PRST
tRSTS
tRSTR
tRSTS
tRSTR
tRSTS
tRSTS
SDEN
tRSTF FWFT 1,QRDY
EMPTY QRDY
FWFT EMPTY tRSTF FWFT FULL
FULL DRDY
FWFT DRDY tRSTF
PRAE
tRSTF
PRAF HALF
tRSTF
Diagram Partial Reset Timing
3F3P1020A 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
2002
Page
tWCLK tWCLKH tWCLKL Write
3F3P1020A
Write
Write
WCLK
tFULL tFULL tFULL tSKEW1
tSKEW1
tFULL
FULL
RCLK
tENH tENS tENH
tENS
Data Read Next Data Read
2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
Output Register Data
NOTES:
time between rising edge RCLK rising edge WCLK greater equal than tSKEW1, FULL will high (after WCLK cycle plus tFULL). tSKEW1 met, then FULL will assert more WCLK cycles.
LOAD High, Low.
Diagram Write Cycle Full Flag Timing (Standard Mode)
FQV202113 FQV202103 FQV20293 FQV20283 FQV20273 FQV20263 FQV20243
FlexQTMIII Plus
2002
Page
3F3P1020A
tRCLK tRCLKH
tRCLKL
RCLK tENH tENS tENH tENS
tENS
tENH
tEMPTY tEMPTY tEMPTY
EMPTY Last Word tOHZ tOEN tOLZ Last Word
tOLZ
tSKEW1
WCLK tENS tENH tENS tENH
2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
NOTES:
time between rising edge WCLK rising edge RCLK greater equal than tSKEW11, EMPTY will high (after RCLK cycle plus tEMPTY). tSKEW1 met, then EMPTY will assert more RCLK cycles.
LOAD High. First word latency: tSKEW1 tEMPTY tRCLK.
Diagram Read Cycle, Empty Flag First Data Word Latency Timing (Standard Mode)
FQV202113 FQV202103 FQV20293 FQV20283 FQV20273 FQV20263 FQV20243
FlexQTMIII Plus
2002
Page
3F3P1020A
tSKEW2 DW[y+2] DW[y+3] DW[y+4] DW[(D-1)/2+1] DW[(D-1)/2+2] DW[(D-1)/2+3] DW[D-x-3] DW[D-x] DW[D-x+1] DW[D-x+2] DW[D-x+2] DW[D-1] tENH tEMPTY tPRAES tHALF tPRAFS tFULL
WCLK
tENS
tSKEW1
RCLK
Output Register Data
QRDY
PRAE
HALF
2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
PRAF
DRDY
NOTES:
time between rising edge WCLK rising edge RCLK greater equal than tSKEW1, QRDY will (after RCLK cycle plus tEMPTY). tSKEW1 met, then QRDY will assert more RCLK cycles.
time between rising edge WCLK rising edge RCLK greater equal than tSKEW2, PRAE will high (after RCLK cycle plus tPRAES). tSKEW2 met, then PRAE will assert more RCLK cycles.
LOAD High, Low.
PRAE offset, PRAF offset. maximum queue depth. Please refer Table Depth. First word latency: tSKEW1 tEMPTY tRCLK
Diagram Write Timing (FWFT Mode)
FQV202113 FQV202103 FQV20293 FQV20283 FQV20273 FQV20263 FQV20243
FlexQTMIII Plus
2002
Page
FQV202113 FQV202103 FQV20293 FQV20283 FQV20273 FQV20263 FQV20243
FlexQTMIII Plus
RCLK tENS
tENH tRETS tENS
tENH
tSKEW2 WCLK tRETS
DWi+1
tENS
tENH
tEMPTY
EMPTY
tEMPTY
tPRAES
PRAE
tHALF
HALF
tPRAFS
PRAF
NOTES:
Upon completion retransmit setup, read operation begin only after EMPTY returns high. Low. Words written queue after MRST Where 1,2,3. depth. Upon reset completion, there must more than words written queue retransmit setup valid.
Diagram Retransmit Timing (Standard Mode)
3F3P1020A 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
2002
Page
FQV202113 FQV202103 FQV20293 FQV20283 FQV20273 FQV20263 FQV20243
FlexQTMIII Plus
RCLK tENS
tENH tRETS tENS
tENH
DWi+1 tSKEW2 WCLK tRETS
tENS
tENH
tEMPTY
QRDY
tEMPTY
tPRAES
PRAE
tHALF
HALF
tPRAFS PRAF
NOTES:
Upon completion retransmit setup, read operation begin only after QRDY returns low. Low. Words written queue after MRST Where 1,2,3. depth. Upon reset completion, there must more than words written queue retransmit setup valid. Please refer Table Depth.
Diagram Retransmit Timing (FWFT Mode)
3F3P1020A 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
2002
Page
FQV202113 FQV202103 FQV20293 FQV20283 FQV20273 FQV20263 FQV20243
FlexQTMIII Plus
RCLK tENS DWi+1
tENH
tSKEW2
WCLK tRETS tENS
tENH
EMPTY
tPRAES
PRAE
tHALF
HALF
tPRAFS
PRAF
NOTES:
part empty point retransmit, Empty Flag EMPTY will updated based RCLK (Retransmit Clock cycle). Valid data will appear output. Low; enables data read outputs DW1= first word written queue after Master Reset; DW2= second word written queue after Master Reset. more than written queue between reset (Master Partial) retransmit setup. Therefore, FULL will high throughout retransmit setup procedure. Please refer Table Depth. There must least words written zero latency retransmit from queue before retransmit operation invoked. RETZL during MRST
Diagram Zero Latency Retransmit Timing (Standard Mode)
3F3P1020A 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
2002
Page
FQV202113 FQV202103 FQV20293 FQV20283 FQV20273 FQV20263 FQV20243
FlexQTMIII Plus
RCLK tENS
tENH
tSKEW2
WCLK tRETS tENS
tENH
QRDY tPRAES PRAE tHALF
HALF
tPRAFS
PRAF
NOTES:
part empty point retransmit, output ready flag QRDY will updated based RCLK (Retransmit Clock cycle). Valid data will appear output. more than words written queue between reset (Master Partial) retransmit setup. Therefore, DRDY will throughout retransmit setup procedure. Please refer Table Depth. Low. DW1, DW2, first, second third words written queue after Master Reset. There must least words written queue before retransmit operation invoked. RETZL during MRST
Diagram Zero Latency Retransmit Timing (FWFT Mode)
3F3P1020A 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
2002
Page
FQV202113 FQV202103 FQV20293 FQV20283 FQV20273 FQV20263 FQV20243
FlexQTMIII Plus
WCLK tENS
SDEN
tENH
tENH
tLOADS
LOAD
tLOADH
tLOADH
PRAE Offset
PRAF Offset
*Refer Table
Diagram Serial Loading Programmable Flag Registers (Standard FWFT Mode)
FQV202113 Other Modes
FQV202103
FQV20293
FQV20283
FQV20273
FQV20263
FQV20253
FQV20243
Table Reference Table Diagram
3F3P1020A 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
2002
Page
FQV202113 FQV202103 FQV20293 FQV20283 FQV20273 FQV20263 FQV20243
FlexQTMIII Plus
tWCLK tWCLKH WCLK tLOADS
LOAD
tWCLKL
tLOADH
tLOADH
tENS
tENH
tENH
PRAE offset (Low Byte)
PRAE offset (High Byte)
PRAF offset (Low Byte)
PRAF offset (High Byte)
Diagram Parallel Loading Programmable Flag Registers (Standard FWFT Mode)
tRCLK tRCLKH RCLK tLOADS
LOAD
tRCLKL
tLOADH
tLOADH
tENS
tENH
tENH
Data Output Register PRAE offset (Low Byte)
PRAE offset (High Byte)
PRAF offset (Low Byte)
PRAF offset (High Byte)
Diagram Parallel Read Programmable Flag Registers (Standard FWFT Mode)
3F3P1020A 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
2002
Page
FQV202113 FQV202103 FQV20293 FQV20283 FQV20273 FQV20263 FQV20243
FlexQTMIII Plus
tWCLKH
WCLK
tWCLKL tENS tENH tPRAFS
words Queue words Queue
tPRAFS
words Queue
PRAF
tSKEW2
RCLK
tENS
tENH
NOTES:_
PRAF offset. maximum queue depth. Please refer Table Depth. time between rising edge RCLK rising edge WCLK greater equal than tSKEW2, PRAF will high (after WCLK cycle plus tPRAFS). tSKEW2 met, then PRAF will assert more WCLK cycles. PRAF synchronizes rising edge WCLK only.
Diagram Synchronous Programmable Almost-Full Flag Timing (Standard FWFT Mode)
tWCLKH
WCLK
tWCLKL
tWCLKH
PRAE
tWCLKL
words Queue(2) words Queue(3) tSKEW2 tPRAES
words Queue(2) words Queue(3) tPRAES tENS tENH
words Queue(2) words Queue(3)
RCLK
NOTES:_
PRAE offset. Standard Mode. FWFT Mode. time between rising edge WCLK rising edge RCLK greater equal than tSKEW2, PRAE will high (after RCLK cycle plus tPRAES). tSKEW2 met, then PRAE will assert more RCLK cycles. PRAE synchronizes rising edge RCLK only.
Diagram Synchronous Programmable Almost-Empty Flag Timing (Standard FWFT Mode)
3F3P1020A 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
2002
Page
FQV202113 FQV202103 FQV20293 FQV20283 FQV20273 FQV20263 FQV20243
FlexQTMIII Plus
tWCLKH WCLK tENS
tWCLKL
tENH
tPRAFA PRAF words Queue words Queue tPRAFA RCLK tENS tENH words Queue
NOTES:_
PRAF offset. maximum queue depth. Please refer Table Depth. PRAF asserted WCLK transition reset high RCLK transition. Select this mode setting during Master Reset.
Diagram Asynchronous Programmable Almost-Full Flag Timing (Standard FWFT Mode)
tWCLKH WCLK tENS
tWCLKL
tENH
tPRAEA PRAE
words Queue(2); words Queue(3) words Queue(2); words Queue words Queue(2); words Queue(3)
tPRAEA
RCLK tENS tENH
NOTES:_
PRAE offset. Standard Mode. FWFT Mode. PRAE asserted RCLK transition reset high WCLK transition. Select this mode setting during Master Reset.
Diagram Asynchronous Programmable Almost-Empty Flag Timing (Standard FWFT Mode)
3F3P1020A 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
2002
Page
FQV202113 FQV202103 FQV20293 FQV20283 FQV20273 FQV20263 FQV20243
FlexQTMIII Plus
tWCLKH WCLK tENS
tWCLKL
tENH
tHALF HALF words Queue(1); [(D+1)/2] words Queue(2)
words Queue(1); [(D+1)/2 words Queue(2) tHALF
words Queue(1); [(D+1)/2] words Queue(2)
RCLK tENS tENH
NOTES:
Standard Mode. FWFT Mode. Please refer Table Depth.
Diagram Half-Full Flag Timing (Standard FWFT Mode)
3F3P1020A 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
2002
Page
FQV202113 FQV202103 FQV20293 FQV20283 FQV20273 FQV20263 FQV20243
FlexQTMIII Plus
Order Information:
Device Family Device Type XXXXX V202113 (524,288 Power Speed (ns) Package** Temperature Range Blank Commercial (0°C 70°C) Industrial (-40° 85°C)
(262,144
V202103 (262,144
(131,072
V20293 V20283 V20273 V20263 V20253 V20243
(131,072 (65,536 (65,536 (32,768 (32,768 (16,384 (16,384 (8,192 (8,192 (4,096 (4,096 (2,048
*Speed available only Commercial temp (0°C 70°C) **Package Plastic Thin Quad Flat Pack (TQFP)
Example:
FQV20283L6PF FQV20273L10PFI
(64k 6ns, Commercial temp) (32k 10ns, Industrial temp)
2107 North First Street, Suite Jose, 95131, www.hba.com
Tel: 408.453.8885 Fax: 408.453.8886
Taiwan Suite 8F-9, Shui-Lee Hsinchu, Taiwan, R.O.C. www.hba.com
Tel: 886.3.516.9119 Fax: 886.3.516.9118
3F3P1020A 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
2002
Page
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