FlexQTMI Volt Synchronous First-In/First-Out Queue Memory Co
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FQV245 FQV235 FQV225 FQV215 FQV205
FlexQTMI
Volt Synchronous First-In/First-Out Queue
Memory Configuration
4,096 2,048 1,024
Device
FQV245 FQV235 FQV225 FQV215 FQV205
Features:
Industry leading First-In/First-Out Queues 133MHz) Independent Write Read cycle time 3.3V power supply input tolerant control data input pins output tolerant flags data output pins Reset clears previously programmed configurations including Write Read pointers. Preset Almost Full PRAF Almost Empty PRAE offsets values Parallel programming PRAF PRAE offset values Full, Empty, Almost Full, Almost Empty, Half Full indicators Asynchronous output enable tri-state data output drivers Available package: Plastic Thin Quad Flat Package (TQFP), Slim Thin Quad Flat Package (STQFP) (0°C 70°C) Commercial operating temperature available cycle time 7.5ns above (-40°C 85°C) Industrial operating temperature available cycle time 10ns above
Product Description:
HBA's FlexQI offers industry leading FIFO queuing bandwidth Gbps), with wide range memory configurations (from 4,096 18). System designer full flexibility implementing deeper wider queues with Write WEXI WEXO Read REXI REXO expansion features using daisy chain technique. Full, Empty, Half Full indicators allow easy handshaking between transmitters receivers. User programmable Almost Full Almost Empty (Parallel) indicators allow implementation virtual queue depths. tolerant input output pins allow easy interfacing with devices operating higher voltage levels. Asynchronous Output Enable configures tri-state data output drivers. Independent Write Read controls provide rate-matching capability. Data written into queue high transition WCLK asserted. Data read from queue high transition RCLK asserted. Reset clears previously programmed configurations providing pulse pin. addition, Write Read pointers queue initialized zero. These FlexQI devices have power consumption, hence minimizing system power requirements. addition, industry standard Plastic TQFP STQFP offered save system board space. These queues ideal applications such data communication, telecommunication, graphics, multiprocessing, test equipment, network switching, etc.
3F118A 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
2002
Page
FQV245 FQV235 FQV225 FQV215 FQV205
FlexQTMI
Block Diagram Single Synchronous Queue 4,096 ,048 1,024 RESET (RST
WRITE CLOCK (WCLK) WRITE ENABLE LOAD LOAD DATA (D17 FULL FLAG FULL PROGRAMMABLE (PRAE) HALF FULL FLAG HALF FQV245 FQV235 FQV225 FQV215 FQV205
READ CLOCK (RCLK) READ ENABLE OUTPUT ENABLE DATA (Q17 EMPTY FLAG EMPTY PROGRAMMABLE PRAF)
WEXO
REXO
FIRST LOAD FIRST READ EXPANSION (REXI)
WRITE EXPANSION (WEXI
Figure Single Device Configuration Signal Flow Diagram
3F118A 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
2002
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FQV245 FQV235 FQV225 FQV215 FQV205
FlexQTMI
WCLK LOAD
Write Control Logic Offset Register
FULL DRDY PRAF Flag Logic
EMPTY/ QRDY PRAE WEXO) HALF
Write Pointer
D17-0
Input Register
SRAM
Output Register
Output Buffer
17-0
FIRST Read Pointer
WEXI WEXO /(HALF) REXI REXO
RCLK Expansion Logic Read Control Logic Reset
Figure Device Architecture
3F118A 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
2002
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FQV245 FQV235 FQV225 FQV215 FQV205
FlexQTMI
RCLK
EMPTY
LOAD
WEXO/HALF
PRAF
FIRST
WCLK
FULL
PRAE
REXO
WEXI
REXI
TQFP (Drw PF-01A; Order Code: STQFP (Drw TF-01A; Order Code: View Figure Device
3F118A 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
2002
Page
FQV245 FQV235 FQV225 FQV215 FQV205
FlexQTMI
Name Symbol Input/Output Description
Reset required initialize Write Read pointers first position queue setting low. FULL PRAF will high; EMPTY PRAE will low. data outputs will low. Previous programmed configurations will maintained. Writes data into queue during high transitions WCLK low. Controls write operation into queue offset registers during high transition WCLK.
LOAD controls write/read, to/from offset registers during high transition WCLK/RCLK respectively. conjunction with
Reset
Input
Write Clock Write Enable Load Enable
WCLK
Input Input Input
LOAD
First Load
FIRST
Input
single device configuration, FIRST low. depth expansion configuration, FIRST first device high other devices daisy chain. single device configuration, WEXI low. depth expansion configuration, WEXI connected WEXO previous device daisy chain. wide input data bus. Reads data from queue during high transitions RCLK low. Controls read operation from queue offset registers during high transition RCLK. single device configuration, REXI low. depth expansion configuration, REXI connected REXO previous device daisy chain. Setting activates data output drivers. Setting high deactivates data output drivers (High-Z). wide output data bus. depth expansion configuration, REXO connected REXI next device daisy chain. Queue full when FULL goes during high transition WCLK. This prohibits further writes into queue.
Write Expansion
WEXI
Input
Data Inputs
D17-0
Input
Read Clock Read Enable Read Expansion
RCLK
Input Input
REXI
Input
Output Enable
Input
Data Outputs Read Expansion Full Flag
Q17-0
Output
REXO
Output
FULL
Output
Table Descriptions
3F118A 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
2002
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FQV245 FQV235 FQV225 FQV215 FQV205
FlexQTMI
Name
Empty Flag
Symbol
EMPTY
Input/Output
Output
Description
Queue empty when EMPTY goes during high transition RCLK. This prohibits further reads from queue. Queue almost full when PRAF goes during high transition WCLK. Default (Full-offset) programmed offset values determine status PRAF Queue almost empty when PRAE goes during high transition RCLK. Default (Empty+offset) programmed offset values determine status PRAE single device configuration, queue more than half full when WEXO HALF goes low. depth expansion configuration, WEXO HALF connected WEXI next device daisy chain. 3.3V power supply. Ground.
Almost Full
PRAF
Output
Almost Empty
PRAE
Output
Write Expansion Out/Half Full
WEXO HALF
Output
Power Ground
Table Descriptions (Continued)
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2002
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FQV245 FQV235 FQV225 FQV215 FQV205
FlexQTMI
Symbol
Rating
Terminal Voltage with respect Storage Temperature Output Current
Com'l Ind'l
-0.5 +125
Unit
VTERM TSTG IOUT
NOTES:
Absolute Ratings reference only. Permanent damage device occur extended period operation outside this range. Standard operation should fall within Recommended Operating Conditions.
Table Absolute Maximum Ratings
FQV245 FQV235 FQV225 FQV215 FQV205
Commercial Clock 7.5ns, 10ns, 15ns, 20ns Industrial Clock 10ns, 15ns, 20ns
Symbol
Parameter
Supply Voltage Com'l/Ind'l Supply Voltage Input High Voltage Com'l/Ind'l Input Voltage Com'l/Ind'l Operating Temperature Commercial Operating Temperature Industrial Input Leakage Current (any input) Output Leakage Current Output Logic Voltage, IOH=-2mA Output Logic Voltage, Active Power Supply Current Standby Current
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
Recommended Operating Conditions
Electrical Characteristics
ILI(1)
Power Consumption
ICC1(2,3) ICC2(4)
Table Specifications
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2002
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FQV245 FQV235 FQV225 FQV215 FQV205
FlexQTMI
Capacitance 100MHz Ambient Temperature (25°C) Symbol Parameter
Conditions
Max.
Unit
CIN(2) COUT(2,4)
NOTES:
Input Capacitance Output Capacitance
Measurement with 0.4<=VIN<=Vcc With output tri-stated High) Icc(1,2) measured with WCLK RCLK Design simulated, tested.
VIN= VOUT=
Table Specifications (Continued)
3F118A 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
2002
Page
FQV245 FQV235 FQV225 FQV215 FQV205
FlexQTMI
Commercial FQV245-7.5 FQV235-7.5 FQV225-7.5 FQV215-7.5 FQV205-7.5 Symbol
tWCLK tWCLKH tWCLKL tRCLK tRCLKH tRCLKL tENS tENH tRST tRSTS tRSTR tRSTF tOLZ tOHZ tFULL tEMPTY tPRAF tPRAE tHALF tXIS tSKEW1 tSKEW2
Commercial Industrial FQV245-10 FQV235-10 FQV225-10 FQV215-10 FQV205-10
Min. Max.
FQV245-15 FQV235-15 FQV225-15 FQV215-15 FQV205-15
Min. Max.
FQV245-20 FQV235-20 FQV225-20 FQV215-20 FQV205-20
Min. Max. Unit
Parameter
Clock Cycle Frequency Data Access Time Write Clock Cycle Time Write Clock High Time Write Clock Time Read Clock Cycle Time Read Clock High Time Read Clock Time Data Set-up Time Data Hold Time Enable Set-up Time Enable Hold Time Reset Pulse Width
Min.
Max.
Reset Set-up Time Reset Recovery Time Reset Flag Output Time Output Enable Output Low-Z Output Enable Output Valid Output Enable Output High-Z Write Clock Full Flag Read Clock Empty Flag Clock Programmable Almost-Full Flag Clock Programmable Almost-Empty Flag Clock Half-Full Flag Clock Expansion Expansion Pulse Width Expansion Set-Up Time Skew time between Read Clock Write Clock Full Flag Skew time between Read Clock Write Clock Empty Flag
NOTES:
Pulse widths less than minimum values allowed. Design simulated, tested.
Table Electrical Characteristics
3F118A 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
2002
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FQV245 FQV235 FQV225 FQV215 FQV205
FlexQTMI
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load*, clock 10ns, 15ns, 20ns Output Load, clock 7.5ns 3.0V 1.5V 1.5V Figure Figure
*Include scope capacitances Table Test Condition
Vcc/
3.3V
D.U.T. 30pF*
Figure Test Load clock 7.5ns
Figure Output Load clock 10ns, 15ns, 20ns *Includes scope capacitances.
3F118A 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
2002
Page
FQV245 FQV235 FQV225 FQV215 FQV205
FlexQTMI Functions
Reset required initialize Write Read pointers first position queue setting low. FULL PRAF will high; EMPTY PRAE will low. data outputs will low. Previous programmed configurations will maintained. Writes data into queue during high transitions WCLK low. Synchronizes FULL PRAF flags. WCLK RCLK independent each other. Controls write operation into queue offset registers during high transition WCLK.
LOAD controls write/read, to/from offset registers during high transition WCLK/RCLK respectively parallel programming. conjunction with
WCLK
LOAD
FIRST
single device configuration, FIRST low. depth expansion configuration, FIRST first device high other devices daisy chain. single device configuration, WEXI low. depth expansion configuration, WEXI connected WEXO previous device daisy chain. wide input data bus. Reads data from queue during high transitions RCLK low. Synchronizes EMPTY PRAE flags. RCLK WCLK independent each other. Reads data from queue during high transitions RCLK low. This also advances Read pointer queue. Setting activates data output drivers. Setting high deactivates data output drivers (High-Z). does control advancement Read pointer. wide output data bus. depth expansion configuration, REXO connected REXI next device daisy chain. Queue full when FULL goes during high transition WCLK. This prohibits further writes into queue prevents advancement Write pointer. Refer Table behavior FULL Queue empty when EMPTY goes during high transition RCLK. This prohibits further reads from queue prevents advancement Read pointer. Refer Table behavior EMPTY Queue almost full when PRAF goes during high transition WCLK. PRAF goes high during high transition RCLK. Default (Full-offset) programmed offset values determine status PRAF Refer Table behavior PRAF Queue almost empty when PRAE goes during high transition RCLK. PRAE goes high during high transition WCLK. Default (Empty+offset) programmed offset values determine status PRAE Refer Table behavior PRAE single device configuration, queue more than half full when HALF goes during high transition WCLK. Queue less than half full when HALF goes high during high transition RCLK. Refer Table details. depth expansion configuration, WEXO connected WEXI next device daisy chain single device configuration, REXI low. depth expansion configuration, REXI connected REXO previous device daisy chain.
WEXI
D17-0 RCLK
Q17-0
REXO FULL
EMPTY
PRAF
PRAE
WEXO HALF
REXI
3F118A
2002
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2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
FQV245 FQV235 FQV225 FQV215 FQV205
FlexQTMI
FQV245 FQV235 FQV225 FQV215 FQV205 Selection Sequence
Parallel write offset registers: Empty Offset Full Offset Parallel read from offset registers: Empty Offset Full Offset Operation Write Memory Parallel write registers: PRAE PRAF Parallel read from registers: PRAE PRAF
LOAD
WCLK
RCLK
Read Memory Operation
Figure Programmable Flag Offset Programming Sequence
Device
FQV245 FQV235 FQV225 FQV215 FQV205
PRAF Programming (bits)
D/Q11-0 D/Q10-0 D/Q9-0 D/Q8-0 D/Q7-0
PRAE Programming (bits)
D/Q11-0 D/Q10-0 D/Q9-0 D/Q8-0 D/Q7-0
Table Parallel Offset Register Data Mapping Table
Device
FQV245 FQV235 FQV225 FQV215 FQV205
Default
007FH 007FH 007FH 003FH 001FH
Table Default Values Offset Registers
3F118A 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
2002
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FQV245 FQV235 FQV225 FQV215 FQV205
FlexQTMI
FQV245 4,096
Data Width
D/Q17 D/Q16 D/Q15 D/Q14 D/Q13 D/Q12 D/Q11 D/Q10 D/Q9 D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0
Cycle PRAE Cycle PRAF FQV235 2,048 Data Width Cycle PRAE Cycle PRAF FQV225 1,024 Data Width Cycle PRAE Cycle PRAF FQV215 Data Width Cycle PRAE Cycle PRAF FQV205 Data Width Cycle PRAE Cycle PRAF
D/Q17 D/Q16 D/Q15 D/Q14 D/Q13 D/Q12 D/Q11 D/Q10 D/Q9 D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0
D/Q17 D/Q16 D/Q15 D/Q14 D/Q13 D/Q12 D/Q11 D/Q10 D/Q9 D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0
D/Q17 D/Q16 D/Q15 D/Q14 D/Q13 D/Q12 D/Q11 D/Q10 D/Q9 D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0
D/Q17 D/Q16 D/Q15 D/Q14 D/Q13 D/Q12 D/Q11 D/Q10 D/Q9 D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0
Bits Offset Registers bits FQV245 bits FQV235 bits FQV225 bits FQV215 bits FQV205 Note: Don't Care applies unused bits
Figure Parallel Offset Write/Read Cycles Diagram
3F118A 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
2002
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FQV245 FQV235 FQV225 FQV215 FQV205
FlexQTMI
FQV245
y(1) (y+1) 2,048 2,049 [4,096-(x+1)] (4,096 -x(2)) 4,095 4,096
FULL
PRAF
HALF
PRAE
EMPTY
FQV235
y(1) (y+1) 1,024 1,025 [2,048-(x+1)] (2,048 -x(2)) 2,047 2,048
FULL
PRAF
HALF
PRAE
EMPTY
FQV225
y(1) (y+1) [1,024-(x+1)] (1,024 -x(2)) 1,023 1,024
FULL
PRAF
HALF
PRAE
EMPTY
FQV215
y(1) (y+1) [512-(x+1)] (512 -x(2))
FULL
PRAF
HALF
PRAE
EMPTY
FQV205
y(1) (y+1) [256-(x+1)] (256 -x(2))
NOTES:
FULL
PRAF
HALF
PRAE
EMPTY
PRAE offset. Default Values: FQV205 FQV215 FQV245/FQV235/FQV225 127.
PRAF offset. Default Values: FQV205 FQV215 FQV245/FQV235/FQV225 127.
Table Status Flags
3F118A 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
2002
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FQV245 FQV235 FQV225 FQV215 FQV205
FlexQTMI Timing Diagrams
tRST
tRSTS
tRSTR
LOAD
tRSTF
EMPTY PRAE
tRSTF
FULL PRAF HALF
tRSTF
NOTES:
After reset, outputs will tri-state clocks (RCLK, WCLK) free-running during reset.
Diagram Reset Timing
3F118A 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
2002
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FQV245 FQV235 FQV225 FQV215 FQV205
FlexQTMI
tWCLK tWCLKH tWCLKL
WCLK
Data Valid
tENH tENS
Operation
tFULL
tFULL
FULL
tSKEW1
RCLK
NOTES:
tSKEW1 minimum time between rising RCLK edge rising WCLK edge guarantee that FULL will high during current clock cycle. time between rising edge RCLK rising edge WCLK equal less than tSKEW1, then FULL change state until next WCLK edge.
Diagram Write Cycle Timing
3F118A 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
2002
Page
FQV245 FQV235 FQV225 FQV215 FQV205
FlexQTMI
tRCLK tRCLKH RCLK tENS tENH tRCLKL
tEMPTY EMPTY tEMPTY
tOLZ
Valid Data
tOHZ
tSKEW1 WCLK
NOTES:
tSKEW1 minimum time between rising WCLK edge rising RCLK edge guarantee that EMPTY will high during current clock cycle. time between rising edge WCLK rising edge RCLK less than tSKEW1, then EMPTY change state until next RCLK edge.
Diagram Read Cycle Timing
3F118A 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
2002
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FQV245 FQV235 FQV225 FQV215 FQV205
FlexQTMI
WCLK
tENS
tSKEW2
RCLK
tFRL(1)
tEMPTY
EMPTY
tENS
tOLZ
NOTES:
tFRL latency from first write first Read. When tSKEW2 greater than equal minimum specification, tFRL (maximum) tRCLK tSKEW2. When tSKEW2 less than minimum specification, tFRL (maximum) equals either tRCLK tSKEW2 tRCLK tSKEW2. Latency Timing applies only Empty Boundary EMPTY low).
Diagram First Data Word Latency after Reset with Simultaneous Read Write
3F118A 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
2002
Page
FQV245 FQV235 FQV225 FQV215 FQV205
FlexQTMI
Write Write
WCLK
tSKEW 1(1) tSKEW 1(1)
tFULL
Data Write
Data Write
tFULL
tFULL
FULL
RCLK
tENS tENH tENS tENH
Data Read Next Data Read
Output Register Data
NOTES:
tSKEW1 minimum time between rising RCLK edge rising WCLK edge guarantee that FULL will high during current clock cycle. time between rising edge RCLK rising edge WCLK less than tSKEW1, then FULL change state until next WCLK edge.
Diagram Full Flag Timing
3F118A 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
2002
Page
FQV245 FQV235 FQV225 FQV215 FQV205
FlexQTMI
WCLK tENS tSKEW2 RCLK tFRL(1) tEMPTY tSKEW2 tEMPTY tFRL(1)
tENH
tENS
tENH
tEMPTY
EMPTY
Output Register Data
NOTES:
tFRL latency from first write first Read. When tSKEW2 greater than equal minimum specification, tFRL (maximum) tRCLK SKEW2. When tSKEW2 less than minimum specification, tFRL (maximum) equals either tRCLK tSKEW2, tRCLK tSKEW2. Latency Timing applies only Empty Boundary EMPTY low).
Diagram Empty Flag Timing
3F118A 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
2002
Page
FQV245 FQV235 FQV225 FQV215 FQV205
FlexQTMI
tWCLKH WCLK tENS tENH tWCLK tWCLKL
LOAD
tENS
PRAE offset
PRAE offset
PRAF offset
PRAF offset
Diagram Write Programmable Registers
tRCLKH
tRCLK
tRCLKL
RCLK
tENS tENH
LOAD
tENS
PRAE offset
PRAF offset
PRAE offset
PRAF offset
Diagram Read Programmable Registers
tWCLKH
tWCLKL
WCLK
tENS tENH
tPRAE
PRAE
words Queue
words Queue
words Queue
tPRAE
RCLK
tENS tENH
NOTES:
PRAE offset.
Diagram Programmable Almost-Empty Flag Timing
3F118A 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
2002
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FQV245 FQV235 FQV225 FQV215 FQV205
FlexQTMI
tWCLKH WCLK tENS tENH tWCLKL
tPRAF
PRAF
(x+1) words Queue memory(1)
words Queue memory(2) tPRAF
(x+1) words Queue memory(1)
RCLK tENS tENH
NOTES:
PRAF offset. maximum queue depth words FQV205; words FQV215; 1,024 words FQV225; 2,048 words FQV235; 4,096 words FQV245.
Diagram Programmable Almost-Full Flag Timing
tWCLKH
tWCLKL
WCLK
tENS tENH
tHALF
HALF
words Queue memory(1)
words Queue memory(2) tHALF
words Queue memory(1)
RCLK
tENS tENH
NOTES:
maximum queue depth words FQV205; words FQV215; 1,024 words FQV225; 2,048 words FQV235; 4,096 words FQV245.
Diagram Half-Full Flag Timing
3F118A 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
2002
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FQV245 FQV235 FQV225 FQV215 FQV205
FlexQTMI
WCLK
Note
WEXO
tENS
NOTES: Write Last Physical Location. Diagram Write Expansion Timing
RCLK Note REXO
tENS
NOTES:
Read from Last Physical Location.
Diagram Read Expansion Timing
WEXI tXIS WCLK
Diagram Write Expansion Timing
REXI
tXIS RCLK
Diagram Read Expansion Timing
3F118A 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
2002
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FQV245 FQV235 FQV225 FQV215 FQV205
FlexQTMI Width Expansion Configuration
Simply connecting together control signals multiple devices increase word width. Status flags detected from device. exceptions Empty Flag Full Flag. Because variations skew between RCLK WCLK, possible flag assertion de-assertion vary cycle between FIFOs. avoid problems user must create composite flags ANDing Empty Flags every FIFO, separately ANDing Full Flags. Figure demonstrates 36-bit width using FQV245 205s. word width attained adding additional FQV245 205s.
Block Diagram Synchronous Queue 4,096 2,048 1,024
RESET (RST
RESET (RST
DATA
READ CLOCK (RCLK) WRITE CLOCK (WCLK) READ ENABLE (REN WRITE ENABLE (WEN OUTPUT ENABLE LOAD LOAD PROGRAMMABLE (PRAE HALF- FULL (HALF FQV245 FQV235 FQV225 FQV215 FQV205 FULL FULL FULL EMPTY FULL FQV245 FQV235 FQV225 FQV215 FQV205 EMPTY PROGRAMMABLE (PRAF)
EMPTY FLAG EMPTY DATA
FIRST LOAD FIRST WRITE EXPANSION (WEXI READ EXPANSION REXI
NOTES:
connect output control signals directly together.
Figure Width Expansion Configuration
3F118A 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
2002
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FQV245 FQV235 FQV225 FQV215 FQV205
FlexQTMI Depth Expansion Configuration (with Programmable Flags)
These devices easily adapted applications requiring more than 4,096 2,048 1,024 words buffering. Figure shows Depth Expansion using three FQV245 205s. Maximum depth limited only signal loading. Follow these steps: first device must designated grounding First Load FIRST control input. other devices must have FIRST high state. Write Expansion WEXO each device must tied Write Expansion WEXI next device. Read Expansion REXO each device must tied Read Expansion REXI next device. Load LOAD pins tied together. Half-Full Flag HALF available this Depth Expansion Configuration. EMPTY FULL PRAF PRAE created with composite flags ORing together every respective flags monitoring. composite PRAF PRAE flags precise.
Block Diagram Synchronous Queue 12,288 6,144 3,072 1,536
WEXO
REXO
WCLK
RCLK
FQV245 FQV235 FQV225 FQV215 FQV205
LOAD
FIRST FULL
EMPTY PRAE REXI
PRAF
WEXI
WEXO WCLK
REXO
LOAD
FQV245 FQV235 FQV225 FQV215 FQV205
RCLK
DATA
DATA
FIRST FULL
EMPTY PRAE REXI
PRAF WEXI
WEXO
REXO
WRITE CLOCK WRITE ENABLE RESET
WCLK
RCLK
FQV245 FQV235 FQV225 FQV215 FQV205
READ CLOCK READ ENABLE OUTPUT ENABLE
LOAD
FULL
LOAD
FULL
EMPTY PRAE WEXI REXI
EMPTY PRAE
PRAF
PRAF
FIRST LOAD (FIRST
Figure Block Diagram Multiple Devices with Programmable Flags used Depth Expansion Configuration
3F118A 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
2002
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FQV245 FQV235 FQV225 FQV215 FQV205
FlexQTMI Order Information:
Device Family
Device Type XXXX V245 (4,096 V235 (2,048 V225 (1,024 V215 (512 V205 (256
Power
Speed (ns)
Package**
Temperature Range Blank Commercial (0°C 70°C) Industrial (-40° 85°C)
*Speed 7.5ns available only Commercial temp (0°C 70°C). Slower speeds available upon request. **Package Plastic Thin Quad Flat Pack (TQFP), Slim Thin Quad Flat Pack (STQFP)
Example: FQV235L7-5TF FQV225L10PFI (32k 7.5ns, Commercial temp) (16k 10ns, Industrial temp)
2107 North First Street, Suite Jose, 95131, www.hba.com
Tel: 408.453.8885 Fax: 408.453.8886
Taiwan Suite 8F-9, Shui-Lee Hsinchu, Taiwan, R.O.C. www.hba.com
Tel: 886.3.516.9119 Fax: 886.3.516.9118
3F118A 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
2002
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