80-Channel SEG/COM Driver MAY. 2002 Version SPLD80A4 Ta
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SPLD80A4
80-Channel SEG/COM Driver
MAY. 2002 Version
SPLD80A4
Table Contents
PAGE
GENERAL DESCRIPTION. BLOCK DIAGRAM FEATURES. SIGNAL DESCRIPTIONS FUNCTIONAL DESCRIPTIONS. ELECTRICAL SPECIFICATIONS 6.1. ABSOLUTE MAXIMUM RATINGS 6.2. CHARACTERISTICS. 6.3. TIMING PANEL DIMENSION SEGMENTS COMMONS) 6.4. TIMING CHARACTERISTIC OPERATION APPLICATION CIRCUITS. 7.1. APPLICATION CIRCUIT (1). 7.2. APPLICATION CIRCUIT (2). PACKAGE/PAD LOCATIONS 8.1. ASSIGNMENT 8.2. ORDERING INFORMATION 8.3. LOCATIONS DISCLAIMER. REVISION HISTORY
Sunplus Technology Co., Ltd. Proprietary Confidential
MAY. 2002 Version:
SPLD80A4
80-CHANNEL SEG/COM DRIVER
GENERAL DESCRIPTION
SPLD80A4, matrix common/segment driver, fabricated power CMOS technology. This includes 80-bit shift register, 80-bit data latch 80-bit 4-level driver. converts serial data parallel data outputs waveform LCD.
FEATURES
Supply voltage: 2.4V 3.6V 3.6V 5.5V driver voltage: Bias voltage supplied externally Built-in double triple voltage converters Serial data input Chain function
BLOCK DIAGRAM
Four types driving configurations Mode Common Segment
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MAY. 2002 Version:
SPLD80A4
SIGNAL DESCRIPTIONS
Mnemonic data shift clock; also used clock double/triple voltage generator. data shifted 80-bit latch falling edge `CP`. data setup time data hold time required between `DIN` `CP`. alternate signal data load. When `LOAD` `HIGH`, shift register contents transferred driver through level shifter. DO80 When `LOAD` `LOW`, last data applied this When `MODE` When `MODE` display data which transferred when `LOAD` high, held. data input (mode=0); segment data input(mode=1). shifted transferred driver. data output(mode=0); common data input(mode=1). `LOW`, 80th shift register content output from `DO80`. state `CS`. CUP1 Coupling capacitor Master enable: generate voltage tripler disable This should controlled CPU. Before entering standby mode, `MEN` must Only programmed `LOW` turn double/triple voltage generator. driver programmed master. VSS(GND) CUP2 VSS2 MODE Ground input Coupling capacitor Double voltage output, `MEN' assigned `LOW', VSS2 will grounded. Triple voltage output, `MEN` assigned `LOW`, will grounded. This clock needed double/triple voltage generator. frequency suggested between 50kHz 300kHz depending loading between VEE. Mode select, combined with com/seg, modes selected. MODE=0 selects pure driver. MODE=1 indicates combined driver. Common/Segment select Power input reference voltage input highest:V1 lowest:V5 Type Segment/Common output Description
`HIGH`, data applied `DO80` will shifted bit-33 bit-49 depends
Sunplus Technology Co., Ltd. Proprietary Confidential
MAY. 2002 Version:
SPLD80A4
FUNCTIONAL DESCRIPTIONS
SPLD80A4 provides four types driving configurations various applications: Mode Segment Common O[80:1] C[1:80] O[48:1] S[1:48]; O[80:49] C[32:1] O[32:1] S[1:32]; O[80:33] C[48:1] O[80:1] S[1:80]
MODE
O[16:1]
O[32:17]
O[48:33]
O[64:49]
O[80:65]
COM/SEG
Data
Display Output Level
COMMON
SEGMENT
Sunplus Technology Co., Ltd. Proprietary Confidential
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SPLD80A4
ELECTRICAL SPECIFICATIONS
6.1. Absolute Maximum Ratings
Characteristics Supply Voltage Supply Voltage Input Voltage Range
conditions AC/DC Electrical Characteristics.
Symbol IVEEI
Ratings 7.0V -0.5V VDD+0.5V
Note: Stresses beyond those given Absolute Maximum Rating table cause operational errors damage device. normal operational
6.2. Characteristics
Characteristics Symbol Limit Min. -100 Typ. Max. Unit Test Condition 2-battery 3-battery 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V
Operating Voltage Operating Current Standby Current Input High Level Input Level Output High Output Sink
ISTBY
6.3. Timing Panel Dimension Segments Commons)
Assignments: DO80 High, MODE High SEGMENTS[48.1] O[48.1] COMMONS[32.1] O[80.49] Voltage Define: COMMON-Selection Alternative Voltage COMMON-NonSelection Alternative Voltage SEGMENTS Turn Voltage SEGMENTS Turn Voltage Pixel Turn Differential Voltage (VDD
Note: Data COM1 Should shifted SPLD80A4 before Change High. (which indicate Start Frame).
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SPLD80A4
Frame Duty COM1 Selected Period COM2 Selected Period
COM1
COM2
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6.4. Timing Characteristic Operation
(Operation Condition: Voltage 5.0V, Frequency 5.0MHz) Parameter Data Latch Setup Time Data Latch Hold Time High High Width Common-Outputs High Segment-Outputs transition High (Hold Time)
Note: that Signal must "NonOverlap"
Symbol TWLD TLCOM TLSEG TDFFP TLDFP
Min.
Max.
Unit
Depend Load Depend Load
TWCP CP80
TWLD
TLSEG
TLCOM
SEGMENTS
COMMONS
TLDFP
TDFFP
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MAY. 2002
SPLD80A4
VSS2
LCDEN (P34P) LD(LOAD) SPLD80A4 DO80 (P32P) RESBP O80-1 MODE O80-1 MODE SPL512A (P35P) (P33P) SPLD80A4
O80-1
CUP1 CUP2
SPLD80A4 VSS2
VSS2
MODE
RESBP Rosc
SEG[160-81] SEG[80-1] SEG160-1 COM80-1
APPLICATION CIRCUITS
Suggest 50KHz~200KHz
7.1. Application Circuit
SPLD80A4 Application circuit
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Panel
Sunplus Technology Co., Ltd.
Version:
MAY. 2002
SPLD80A4
0.1µF
VSS2
doubler- short VSS2 tripler short
MODE DO80 SPLD80A4 O48-1 O80-49 VSS2 CUP1 0.1µF CUP2
Note Connect substrate floating.
SEG[48:1] COM[32:1]
0.1µF
0.1µF
0.1µF
SEG48-1 COM32-1
7.2. Application Circuit
Device
Sunplus Technology Co., Ltd.
SPLD80A4 1/32duty, segments application circuit
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PACKAGE/PAD LOCATIONS
8.1. Assignment
Chip Size: 5570µm 3380µm This substrate should connected
Note1: Chip size included scribe line. Note2: ensure function properly, please bond pins. Note3: 0.1µF capacitor between should placed close possible.
8.2. Ordering Information
Product Number SPLD80A4-nnnnV-C
Note1: Code number (nnnnV) assigned customer. Note2: Code number (nnnn 0000 9999); version
Package Type Chip form
Sunplus Technology Co., Ltd. Proprietary Confidential
MAY. 2002 Version:
SPLD80A4
8.3. Locations
Name -2605 -2605 -2605 -2605 -2605 -2605 -2605 -2605 -2605 -2605 -2605 -2605 -2605 -2605 -2605 -2605 -2605 -2605 -2605 -2605 -2411 -2250 -2100 -1954 -1810 -1675 -1540 -1403 -1268 -1128 -993 -852 -717 -577 -442 -301 -166 1408 1238 1069 -204 -357 -497 -632 -773 -908 -1053 -1209 -1363 -1518 -1518 -1518 -1518 -1518 -1518 -1518 -1518 -1518 -1518 -1518 -1518 -1518 -1518 -1518 -1518 -1518 -1518 -1518 -1518 -1518 -1518 -1518 -1518 Name MODE DO80 CUP2 CUP1 VSS2 1057 1192 1327 1471 1616 2605 2605 2605 2605 2605 2605 2605 2605 2605 2605 2605 2605 2605 2605 2605 2605 2605 2605 2605 2605 2605 1625 1480 1336 1201 1066 -160 -295 -436 -571 -1518 -1518 -1518 -1518 -1518 -1518 -1451 -1290 -1133 -982 -830 -695 -556 -421 -281 -146 1088 1233 1378 1517 1517 1517 1517 1517 1517 1517 1517 1517 1517 1517 1517 1517 1517 1517 1517 1517 MAY. 2002 Version:
Sunplus Technology Co., Ltd. Proprietary Confidential
SPLD80A4
Name -711 -846 -986 -1121 -1262 -1397 -1537 1517 1517 1517 1517 1517 1517 1517 Name -1672 -1813 -1957 -2101 -2263 -2425 1517 1517 1517 1517 1517 1517
Sunplus Technology Co., Ltd. Proprietary Confidential
MAY. 2002 Version:
SPLD80A4
DISCLAIMER
information appearing this publication believed accurate. Integrated circuits sold Sunplus Technology covered warranty patent indemnification provisions stipulated terms sale only. SUNPLUS makes warranty, express, statutory implied description regarding information this publication FURTHERMORE, SUNPLUS MAKES WARRANTY SUNPLUS reserves right halt production alter specifications regarding freedom described chip(s) from patent infringement. MERCHANTABILITY FITNESS PURPOSE. prices time without notice. publication current before placing orders.
Accordingly, reader cautioned verify that data sheets other information this Products described herein intended normal commercial applications. Please note that application circuits
Applications involving unusual environmental reliability requirements, e.g. military equipment medical life support equipment, specifically recommended without additional processing SUNPLUS such applications. illustrated this document reference purposes only.
Sunplus Technology Co., Ltd. Proprietary Confidential
MAY. 2002 Version:
SPLD80A4
REVISION HISTORY
Date JAN. 1999 DEC. 1999 Revision Original Modify format "DISCLAIMER" FEB. 2000 "Timing Panel Dimension Segments Commons)" "Timing Characteristic Operation" SEP. 2001 Revise segment output signal sequence from O[80:1] O[1:80], O[48:1] O[1:48], O[32:1] O[1:32] Correct chip size Note1 Note3 "8.1 Assignment" Renew document format MAY. 2002 Revise working voltage range from 2.4V 3.5V(For 2-battery) 2.4V 3.6V(For 2-battery) Revise "6.3 Timing Panel Dimension" from Segments Commons Segments Commons Description Page
Sunplus Technology Co., Ltd. Proprietary Confidential
MAY. 2002 Version:
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