SST34HF1621 SST34HF1641 SST3 4HF16 SRAM (x8/x16 mboMe morie
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Mbit Concurrent SuperFlash Mbit SRAM ComboMemory
SST34HF1621 SST34HF1641
SST3 4HF16 SRAM (x8/x16 mboMe morie
FEATURES:
Flash Organization: Dual-Bank Architecture Concurrent Read/Write Operation Mbit: Mbit Mbit SRAM Organization: Mbit: 256K 128K Mbit: 512K 256K Single 2.7-3.3V Read Write Operations Superior Reliability Endurance: 100,000 Cycles (typical) Greater than years Data Retention Power Consumption: Active Current: (typical) Standby Current: (typical) Hardware Sector Protection (WP#) Protects outer most sectors KWord) larger bank holding unprotects holding high Hardware Reset (RST#) Resets internal state machine reading data array Sector-Erase Capability Uniform KWord sectors Block-Erase Capability Uniform KWord blocks Read Access Time Flash: SRAM: Latched Address Data Fast Erase Word-Program: Sector-Erase Time: (typical) Block-Erase Time: (typical) Chip-Erase Time: (typical) Word-Program Time: (typical) Chip Rewrite Time: seconds (typical) Automatic Write Timing Internal Generation End-of-Write Detection Toggle Data# Polling Ready/Busy# CMOS Compatibility JEDEC Standard Command Conforms Common Flash Memory Interface (CFI) Packages Available 56-ball LFBGA (8mm 10mm)
PRODUCT DESCRIPTION
SST34HF1621/1641 ComboMemory devices integrate CMOS flash memory bank with 256K 128K 512K 256K CMOS SRAM memory bank Multi-Chip Package (MCP). These devices fabricated using SST's proprietary, high-performance CMOS SuperFlash technology incorporating split-gate cell design thick oxide tunneling injector attain better reliability manufacturability compared with alternate approaches. SST34HF1621/1641 devices ideal applications such cellular phones, GPSs, PDAs other portable electronic devices power small form factor system. SST34HF1621/1641 features dual flash memory bank architecture allowing concurrent operations between flash memory banks SRAM. devices read data from either bank while Erase Program operation progress opposite bank. flash memory banks partitioned into Mbit Mbit with bottom sector protection options storing boot code, program code, configuration/parameter data user data.
©200 lico Stora chno Inc. S711 72-0 5-00 2/02
SuperFlash technology provides fixed Erase Program times, independent number Erase/Program cycles that have occurred. Therefore, system software hardware does have modified de-rated necessary with alternative flash technologies, whose Erase Program times increase with accumulated Erase/Program cycles. SST34HF1621/1641 devices offer guaranteed endurance 10,000 cycles. Data retention rated greater than years. With high performance Word-Program, flash memory banks provide typical Word-Program time µsec. entire flash memory bank erased programmed word-byword typically seconds SST34HF1621/1641, when using interface features such oggle Data# Polling indicate completion Program operation. protect against inadvertent flash write, SST34HF1621/ 1641 devices contain on-chip hardware software data protection schemes.
erFlash regi trade marks lico rage chno logy, Inc. oncu rrent Supe ash, CSF, Comb oMemo trade marks lico rage chno logy, Inc. cificatio ject witho otice.
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF1621 SST34HF1641
Data Sheet flash SRAM operate independent memory banks with respective bank enable signals. memory bank selection done bank enable signals. SRAM bank enable signal, BES1# BES2, selects SRAM bank. flash memory bank enable signal, BEF#, used with Software Data Protection (SDP) command sequence when controlling Erase Program operations flash memory bank. memory banks superimposed same memory address space where they share common address lines, data lines, which minimize power consumption area. contention elimin ated device will recognize both bank enables being simultaneously active. Designed, manufactured, tested applications requiring power small form factor, SST34HF1621/ 1641 offered both commercial extended temperatures small footprint package meet board space constraint requirements.
Flash Bank Read Write Write Operation Write Operation Bank Write Read Operation Write Operation Write SRAM Operation Operation Read Read Write Write
Note: purposes this table, write means Block-, Sector, Chip-Erase, Word-Program applicable appropriate bank.
Flash Read Operation
Read operation SST34HF1621/1641 controlled BEF# OE#, both have system obtain data from outputs. BEF# used devic selection. When BEF# high, chip deselected only standby power consumed. output control used gate data from output pins. data high impedance state when either BEF# high. Refer Read cycle timing diagram further details (Figure
Device Operation
SST34HF1621/1641 uses BES1#, BES2 BEF# control operation either flash SRAM memory bank. When BEF# low, flash bank activated Read, Program Erase operation. When BES1# low, BES2 high SRAM activated Read Write operation. BEF# BES1# cannot level, BES2 cannot high level same time. bank enable signals asserted, contention will result device suffer permanent damage. address, data, control lines shared flash SRAM memory banks which minimizes power consumption loading. device goes into standby when BEF# BES1# bank enables raised (Logic High) when BEF# high BES2 low.
Flash Word-Program Operation
SST34HF1621/1641 programmed word-byword basis. Before Program operations, memory must erased first. Program operation consists three steps. first step three-byte load sequence Software Data Protection. second step load word address word data. During Word-Program operation, addresses latched falling edge either BEF# WE#, whichever occurs last. data latched rising edge either BEF# WE#, whichever occurs first. third step internal Program operation which initiated after rising edge fourth BEF#, whichever occurs first. Program operation, once initiated, will completed typically within Figures BEF# controlled Program operation timing diagrams Figure flowcharts. During Program operation, only valid reads Data# Polling oggle Bit. During internal Program operation, host free perform additional tasks. commands issued during internal Program operation ignored.
Concurrent Read/Write Operation
Dual bank architecture SST34HF1621/1641 devices allows Concurrent Read/Write operation whereby user read from bank while program erase other bank. This operation used when user needs read system code bank while updating data other bank. Figure Dual-Bank Memory Organization.
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Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF1621 SST34HF1641
Flash Sector/Block-Erase Operation
Sector/Block-Erase operation allows system erase device sector-by-sector block-by-block basis. SST34HF1621/1641 offer both Sector-Erase Block-Erase mode. sector architecture based uniform sector size KWord. Block-Erase mode based uniform block size KWord. SectorErase operation initiated executing six-byte command sequence with Sector-Erase command (30H) sector address (SA) last cycle. Block-Erase operation initiated executing six-byte command sequence with Block-Erase command (50H) block address (BA) last cycle. sector block address latched falling edge sixth pulse, while command (30H 50H) latched rising edge sixth pulse. internal Erase operation begins after sixth pulse. Figures timing waveforms. commands issued during Sector- Block-Erase operation ignored.
actual completion nonvolatile write asynchronous with system; therefore, either Ready/Busy# (RY/ BY#), Data# Polling (DQ7) Toggle (DQ6) read simultaneous with completion Write cycle. this occurs, system possibly erroneous result, i.e., valid data appear conflict with either DQ6. order prevent spurious rejection, erroneous result occurs, software routine should include loop read accessed location additional times. both reads valid, then device completed Write cycle, otherwise rejection valid.
Ready/Busy# (RY/BY#)
SST34HF1621/1641 includes Ready/Busy# (RY/ BY#) output signal. RY/BY# actively pulled during internal Program/Erase operation. status RY/BY# valid after rising edge fourth CE#) pulse Program operation. Sector-, Block- Bank-Erase, RY/BY# valid after rising edge sixth (CE#) pulse. RY/BY# open drain output that allows several devices tied parallel external pull resistor. Ready/Busy# high impedance whenever high RST# low.
Flash Chip-Erase Operation
SST34HF1621/1641 provide Chip-Erase operation, which allows user erase unprotected sectors/ blocks state. This useful when device must quickly erased. Chip-Erase operation initiated executing sixbyte command sequence with Chip-Erase command (10H) address 5555H last byte sequence. Erase operation begins with rising edge sixth BEF#, whichever occurs first. During Erase operation, only valid read oggle Data# Polling. able command sequence, Figure timing diagram, Figure flowchart. commands issued during Chip-Erase operation ignored.
Flash Data# Polling
When SST34HF1621/1641 internal Program operation, attempt read will produce complement true data. Once Program operation completed, will produce true data. Note that even though have valid data immediately following completion internal Write operation, remaining data outputs still invalid: valid data entire data will appear subsequent successive Read cycles after interval During internal Erase operation, attempt read will produce `0'. Once internal Erase operation completed, will produce `1'. Data# Polling (DQ7) valid after rising edge fourth BEF#) pulse Program operation. Sector-, Block- Chip-Erase, Data# Polling (DQ7) valid after rising edge sixth BEF#) pulse. After completion Program operation, Data# Polling remains active device return Read mode approximately Figure Data# Polling (DQ7) timing diagram Figure flowchart.
Flash Write Operation Status Detection
SST34HF1621/1641 provide hardware software means detect completion Write (Program Erase) cycle, order optimize system Write cycle time. hardware detection uses Ready/Busy# (RY/BY#) pin. software detection includes status bits: Data# Polling (DQ7) oggle (DQ6). End-of-Write detection mode enabled after rising edge WE#, which initiates internal Program Erase operation.
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Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF1621 SST34HF1641
Flash Toggle
During internal Program Erase operation, consecutive attempts read will produce alternating i.e., toggling between When internal Program Erase operation completed, will stop toggling. After completion Program operation, will stop toggling approximately device then ready next operation. Toggle (DQ6) valid after rising edge fourth BEF#) pulse Program operation. Sector-, Block- Chip-Erase, oggle (DQ6) valid after rising edge sixth BEF#) pulse. Figure Toggle timing diagram Figure flowchart.
Hardware Reset (RST#)
RST# provides hardware method resetting device read array data. When RST# held least TRP, in-progress operation will terminate return Read mode (see Figure 18). When internal Program/Erase operation progress, minimum period TRHR required after RST# driven high before valid Read take place (see Figure 17). Erase operation that been interrupted needs reinitiated after device resumes normal operation mode ensure data integrity.
Software Data Protection (SDP)
SST34HF1621/1641 provide JEDEC standard Software Data Protection scheme data alteration operations, i.e., Program Erase. Program operation requires inclusion three-byte sequence. three-byte load sequence used initiate Program operation, providing optimal protection from inadvertent Write operations, e.g., during system power-up power-down. Erase operation requires inclusion six-byte sequence. SST34HF1621/1641 shipped with Software Data Protection permanently enabled. able specific software command codes. During command sequence, invalid commands will abort device Read mode within TRC. contents DQ15DQ8 "Don't Care" during command sequence.
Data Protection
SST34HF1621/1641 provide both hardware software features protect nonvolatile data from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: BEF# pulse less than will initiate Write cycle. Power Up/Down Detection: Write operation inhibited when less than 1.5V. Write Inhibit Mode: Forcing low, BEF# high, high will inhibit Write operation. This prevents inadvertent writes during power-up power-down.
Common Flash Memory Interface (CFI) Hardware Block Protection
SST34HF1621/1641 provide hardware block protection which protects outermost KWord larger bank.The block protected when held low. Figure Block-Protection location. user disable block protection driving high thus allowing erase program data into protected sectors. must held high prior issuing write command remain stable until after entire Write operation completed. SST34HF1621/1641 also contain information describe characteristics device. order enter Query mode, system must write threebyte sequence, same Software Entry command with (CFI Query command) address 555H last byte sequence. Once device enters Query mode, system read data addresses given ables through system must write Exit command return Read mode from Query mode.
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Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF1621 SST34HF1641
Product Identification
Product Identification mode identifies devices SST34HF1621/1641 manufacturer SST. This mode accessed software operations only. hardware device Read operation, which typically used programmers cannot used this device because shared lines between flash SRAM multi-chip package. Therefore, application high voltage damage this device. Users software Product Identification operation identify part (i.e., using device when using multiple manufacturers same socket. details, Tables software operation, Figure software entry read timing diagram Figure entry command sequence flowchart. TABLE
ADDRESS Manufacturer's Device SST34HF1621 SST34HF1641 0001H 0001H 2761H 2761H
T1.2
SRAM Operation
With BES1# low, BES2 BEF# high, SST34HF162x operates 256K 128K CMOS SRAM, SST34HF164x operates 512K 256K CMOS SRAM, with fully static operation requiring external clocks timing strobes. CIOs configures SRAM SRAM operation modes. SST34HF162x SRAM mapped into first KByte/128 KWord address space device, SST34HF164x SRAM mapped into first KByte/256 KWord address space. When BES1#, BEF# high BES2 low, memory banks deselected device enters standby. Read Write cycle times equal. control signals UBS# LBS# provide access upper data byte lower data byte. able SRAM Read Write data byte control modes operation.
DATA 00BFH
0000H
SRAM Read
SRAM Read operation SST34HF1621/1641 controlled BES1#, both have with BES2 high system obtain data from outputs. BES1# BES2 used SRAM bank selection. output control used gate data from output pins. data high impedance state when high. Refer Read cycle timing diagram, Figure further details.
Product Identification Mode Exit/ Mode Exit
order return standard Read mode, Software Product Identification mode must exited. Exit accomplished issuing Software Exit command sequence, which returns device Read mode. This command also used reset device Read mode after inadvertent transient condition that apparently causes device behave abnormally, e.g., read correctly. Please note that Software Exit/ Exit command ignored during internal Program Erase operation. able software command codes, Figure timing waveform Figure flowchart.
SRAM Write
SRAM Write operation SST34HF1621/1641 controlled BES1#, both have low, BES2 have high system write SRAM. During Word-Write operation, addresses data referenced rising edge either BES1#, WE#, falling edge BES2 whichever occurs first. write time measured from last falling edge BES#1 rising edge BES2 first rising edge BES1#, falling edge BES2. Refer Write cycle timing diagram, Figures further details.
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Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF1621 SST34HF1641
Address Buffers SuperFlash Memory (Bank RST# BEF# LBS# UBS# BES1# BES2 CIOs RY/BY#
SuperFlash Memory (Bank Control Logic Buffers
DQ15
Address Buffers Most significant address
Mbit Mbit SRAM
B1.1
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Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF1621 SST34HF1641
Bottom Sector Protection; KWord Blocks; KWord Sectors
FFFFFH F8000H F7FFFH F0000H EFFFFH E8000H E7FFFH E0000H DFFFFH D8000H D7FFFH D0000H CFFFFH C8000H C7FFFH C0000H BFFFFH B8000H B7FFFH B0000H AFFFFH A8000H A7FFFH A0000H 9FFFFH 98000H 97FFFH 90000H 8FFFFH 88000H 87FFFH 80000H 7FFFFH 78000H 77FFFH 70000H 6FFFFH 68000H 67FFFH 60000H 5FFFFH 58000H 57FFFH 50000H 4FFFFH 48000H 47FFFH 40000H 3FFFFH 38000H 37FFFH 30000H 2FFFFH 28000H 27FFFH 20000H 1FFFFH 18000H 17FFFH 10000H 00FFFFH 008000H 007FFFH 001000H 000FFFH 000000H Block Block Block
Bank Bank
Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block
KWord Sector Protection (Four KWord Sectors)
Block
F02.1
FIGURE SST34HF1621/1641,
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Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF1621 SST34HF1641
VIEW (balls facing down)
SST34HF1621/1641
DQ15 DQ14
DQ13 DQ12 VDDS CIOs VDDF DQ11
BES2 RST# RY/BY# LBS# UBS#
DQ10
BEF# BES1#
56-lfbga P01.2
FIGURE TABLE
Symbol
LFBGA
Name Functions provide flash address, -A0. provide SRAM address, provide SRAM address input byte mode (x8). When CIOs VIL, SRAM Byte mode provides most significant address input. When CIOs VIH, SRAM Word mode becomes Don't Care pin. output data during Read cycles receive input data during Write cycles. Data internally latched during flash Erase/Program cycle. outputs tri-state when high BES1# high BES2 BEF# high. activate Flash memor bank when BEF#
Address Inputs Address Input (SRAM)
-DQ0
Data Inputs/Outputs
BEF# BES1# BES2 UBS# LBS# CIOs RST# RY/BY#
Flash Memory Bank Enable
SRAM Memory Bank Enable activate SRAM memor bank when BES1# SRAM Memory Bank Enable activate SRAM memor bank when BES2 high Output Enable Write Enable Upper Byte Control (SRAM) Lower Byte Control (SRAM) Configuration (SRAM) Write Protect Reset Ready/Busy# gate data output buffers control Write operations enable 5-DQ enable 7-DQ0 CIOs Word mode (x16), CIOs Byte mode (x8) protect unprotect sectors from Erase Program operation Reset return device Read mode output status Program Erase Operation RY/BY# open drain output, 100K pull-up resistor required allow RY/BY# transition high indicating device ready read. 2.7-3.3V Power Supply Flash only 2.7-3.3V Power Supply SRAM only Unconnected pins
T2.5
Ground Power Supply (Flash) Power Supply (SRAM) Connection
Most Significant Address
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Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF1621 SST34HF1641
Data Sheet TABLE
BEF# Flash Read Flash Write Flash Erase SRAM Read BES1# Output Disable BES22 SRAM Write Product Identification4 HIGH-Z HIGH-Z HIGH-Z HIGH-Z HIGH-Z HIGH-Z CIOs3 LBS# UBS# HIGH-Z HIGH-Z HIGH-Z HIGH-Z HIGH-Z HIGH-Z
Mode Full Standby
Manufacturer's Device
T3.6
other value. apply BEF# BES1# BES2 same time SRAM configuration input CIOs; (word mode), (byte mode) Software mode only With 9-A1 0;SST Manufacturer's 00BFH, read with SST34HF1621/1641 Device 2761H, read with
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Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF1621 SST34HF1641
Data Sheet TABLE
Write Cycle Addr Word-Program Sector-Erase Block-Erase Chip-Erase Software Entry Query Entr Software Exit/ Exit 5555H 5555H 5555H 5555H 5555H 5555H 5555H Data Write Cycle Addr 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH Data2 Write Cycle Addr 5555H 5555H 5555H 5555H 5555H 5555H 5555H Data2
T4.4
Command Sequence
Write Cycle Addr1 5555H 5555H 5555H Data2 Data
Write Cycle Addr 2AAAH 2AAAH 2AAAH Data2
Write Cycle Addr 5555H Data
Address format 4-A0 (Hex),Address -A19 VIH, other value, Command sequence. Data format -DQ8 VIH, other value, Command sequence. Program Word address Sector-Erase; uses 9-A11 address lines Block-Erase; uses address lines device does remain Software Product Identification mode powered down. Manufacturer's 00BFH, read with With 0-A1 SST34HF1621/1641 Device 2761H, read with
TABLE
Data 0051H 0052H 0059H 0001H 0007H 0000H 0000H 0000H 0000H 0000H 0000H
T5.0
Address
Data Query Unique ASCII string "QRY"
Primar command Address Primary Extended Table Alternate command (00H none exists) Address Alter nate extended Table (00H none exits)
Refer publication more details.
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Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF1621 SST34HF1641
Data Sheet TABLE
Data 0027H 0036H 0000H 0000H 0004H 0000H 0004H 0006H 0001H 0000H 0001H 0001H Data
Address
(Program/Erase)
Volts, -DQ0 millivolts
(Program/Erase)
Volts, -DQ0 millivolts (00H pin) (00H pin) Typical time Word-Program Typical time size buffer program (00H suppor ted) Typical time individual Sector/Block-Erase Typical time Chip-Erase Maximum time Word-Program times typical Maximum time buffer program times typical Maximum time individual Sector/Block-Erase times typical Maximum time Chip-Erase times typical
T6.0
TABLE
Data 0015H 0001H 0000H 0000H 0000H 0002H 00FFH 0003H 0008H 0000H 001FH 0000H 0000H 0001H Bytes KByte/block (0100H 256)
T7.0
Address
Data Device size Byte (15H Bytes) Flash Device Interface description; 0001H x16-only asynchronous interface Maximum number byte multi-byte (00H suppor ted) Number Erase Sector/Block sizes suppor device Sector Information Number sectors; 256B sector size) 1023 1024 sectors (03FF 1023) Bytes KByte/sector (0008H Block Information Number blocks; 256B block size) blocks (001F
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Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF1621 SST34HF1641
Data Sheet Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" cause permanent damage device. This stress rating only functional operation device these conditions conditions greater than those defined operational sections this data sheet implied. Exposure absolute maximum stress rating conditions affect device reliability.) Operating Temperature -20°C +85°C Storage Temperature -65°C +125°C Voltage Ground Potential .-0.5V +0.3V Transient Voltage (<20 Ground Potential -1.0V +1.0V Package Power Dissipation Capability 25°C) 1.0W Surface Mount Lead Soldering Temperature Seconds) 240°C Output Short Circuit Current2
VDDS Outputs shorted more than second. more than output shorted time.
Range Commercial Extended Ambient Temp +70°C -20°C +85°C
2.7-3.3V 2.7-3.3V
Input Rise/Fall Time Output Load Figures
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Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF1621 SST34HF1641
Data Sheet TABLE
Symbol
2.7-3.3V)
Limits Parameter Active Current Read Flash SRAM Concurrent Operation Write1 Flash SRAM 3.0V 3.3V BEF#=VIL BES1#=VIH BES2=VIL OE#=VIH BEF#=VIH BES1#=VIL BES2=V Max, BEF#=BES1#=VIH BES2=VIL Max, BEF#=V WE#=V I/O=VIL /VIH Reset=VS S±0.3V VIN=GND =GND =100 =-100 =-500
Units
Test Conditions Address input=VIL /VIH f=1/T Min, Max, open OE#=VIL WE#=VIH
BEF#=VIL BES1#=VIH BES2=VIL BEF#=VIH BES1#=VIL BES2=V BEF#=VIH BES1#=VIL BES2=V
VILC VIHC
Standby Current
Auto Power Mode 3.0V 3.3V Reset Current Input Leakage Current Output Leakage Current Input Voltage Input Voltage (CMOS) Input High Voltage Input High Voltage (CMOS) Flash Output Voltage Flash Output High Voltage SRAM Output Voltage SRAM Output High Voltage
VDD-0.3 VDD-0.2
active while Erase Program progress.
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Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF1621 SST34HF1641
Data Sheet TABLE
Symbol
Parameter Power-up Read Operation Power-up Write Operation Minimum Units
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE 25°C, Mhz, other pins open)
Parameter CI/O1 Description Capacitance Input Capacitance Test Condition VI/O Maximum
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE
Symbol ILTH Parameter Endurance Data Retention Latch Minimum Specification 10,000 Units Cycles Years Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard
This parameter measured only initial qualification after design process change that could affect this parameter.
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Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF1621 SST34HF1641
CHARACTERISTICS
TABLE SRAM
SST34HF1621/1641-70 Symbol Parameter Read Cycle Time Address Access Time Bank Enable Access Time Output Enable Access Time UBS#, LBS# Access Time BES# Active Output Output Enable Active Output UBS#, LBS# Active Output BES# High-Z Output Output Disable High-Z Output UBS#, LBS# High-Z Output Output Hold from Address Change SST34HF1621/1641-90 Units
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE SRAM
SST34HF1621/1641-70 Symbol Parameter Write Cycle Time Bank Enable End-of-Write Address Valid End-of-Write Address Set-up Time Write Pulse Width Write Recovery Time UBS#, LBS# End-of-Wr Output Disable from Output Enable from High Data Set-up Time Data Hold from Write Time SST34HF1621/1641-90 Units
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Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF1621 SST34HF1641
Data Sheet TABLE 2.7-3.3V
SST34HF1621/1641-70 Symbol Parameter Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time BEF# Active Output Active Output BEF# High High-Z Output High High-Z Output Output Hold from Address Change RST# Pulse Width RST# High Before Read RST# Read SST34HF1621/1641-90 Units
This parameter measured only initial qualification after design process change that could affect this parameter. This parameter applies Sector-Erase Block-Erase operations. This parameter does apply Chip-Erase operations.
TABLE
Symbol
Parameter Word-Program Time Address Setup Time Address Hold Time BEF# Setup Time BEF# Hold Time High Setup Time High Hold Time BEF# Pulse Width Pulse Width Pulse Width High BEF# Pulse Width High Data Setup Time Data Hold Time Software Access Exit Time RY/BY# Delay Time Recover Time Sector-Erase Block-Erase Chip-Erase
Units
This parameter measured only initial qualification after design process change that could affect this parameter.
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Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF1621 SST34HF1641
TRCS ADDRESSESAMSS-0 TAAS BES1# TBES TOHS
BES2
TBES TBLZS TBHZS TOES TOLZS TOHZS TBYES TBYLZS DATA VALID TBYHZS
UBS#, LBS#
DQ15-0 AMSS Most Significant SRAM Address
F15.0
FIGURE SRAM
TWCS ADDRESSES AMSS-0 TASTS TAWS TBWS BES1# BES2 UBS#, LBS# TODWS NOTE TOEWS TDSS TDHS NOTE TBWS TBYWS TWPS TWRS
DQ15-8, DQ7-0
VALID DATA
F16.2 Notes: High during Write cycle, outputs will remain high impedance. BES1# goes BES2 goes high coincident with after goes Low, output will remain high impedance. BES1# goes High BES2 goes coincident with before goes High, output will remain high impedance. Because signals output state this time, input signals reverse polarity must applied.
FIGURE SRAM (WE#
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Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF1621 SST34HF1641
TWCS ADDRESSES AMSS-0 TWPS TWRS
TBWS BES1#
BES2
TBWS TAWS TASTS TBYWS
UBS#, LBS# TDSS DQ15-8, DQ7-0 TDHS
NOTE
VALID DATA
NOTE
F18.0
Notes: High during Write cycle, outputs will remain high impedance. Because signals output state this time, input signals reverse polarity must applied.
FIGURE SRAM (UBS#, LBS#
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Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF1621 SST34HF1641
ADDRESS A19-0
BEF#
TCHZ DQ15-0 HIGH-Z TCLZ DATA VALID DATA VALID
F04.0
TOLZ
TOHZ
HIGH-Z
FIGURE
ADDRESS A19-0 5555 RY/BY# DQ15-0 XXAA XX55 XXA0 DATA WORD (ADDR/DATA) VALID TWPH 2AAA 5555 ADDR
BEF#
F05.3
Note: VIH, other value.
FIGURE
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Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF1621 SST34HF1641
ADDRESS A19-0 5555 BEF# RY/BY# DQ15-0 XXAA XX55 XXA0 DATA WORD (ADDR/DATA) VALID TCPH 2AAA 5555 ADDR
F06.3
Note: VIH, other value.
FIGURE BEF#
ADDRESS A19-0 BEF# TOEH DATA# DATA# VALID DATA
F07.2
TOES
FIGURE
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Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF1621 SST34HF1641
ADDRESS A19-0 BEF# TOEH
READ CYCLES WITH SAME OUTPUTS VALID DATA
F08.3
FIGURE TOGG
SIX-BYTE CODE CHIP-ERASE ADDRESS A19-0 5555 2AAA 5555 5555 2AAA 5555
TSCE
BEF#
RY/BY# DQ15-0 XXAA XX55 XX80 XXAA XX55 XX10
VALID
F09.6
Note: This device also supports BEF# controlled Chip-Erase operation. BEF# signals interchageable long minimum timings met. (See Table VIH, other value.
FIGURE
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Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF1621 SST34HF1641
SIX-BYTE CODE BLOCK-ERASE ADDRESS A19-0 5555 2AAA 5555 5555 2AAA
BEF#
RY/BY#
DQ15-0
XXAA
XX55
XX80
XXAA
XX55
XX50
VALID
F10.5
Note: This device also supports BEF# controlled Block-Erase operation. BEF# signals interchageable long minimum timings met. (See Table Block Address VIH, other value.
FIGURE
SIX-BYTE CODE SECTOR-ERASE ADDRESS A19-0 5555 2AAA 5555 5555 2AAA
BEF#
RY/BY# DQ15-0
XXAA
XX55
XX80
XXAA
XX55
XX30
F11.5
VALID
Note: This device also supports BEF# controlled Sector-Erase operation. BEF# signals interchageable long minimum timings met. (See Table Sector Address VIH, other value.
FIGURE
©200 Sili Storag chno Inc.
-05-0
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF1621 SST34HF1641
THREE-BYTE SEQUENCE SOFTWARE ENTRY ADDRESS A14-0 5555 2AAA 5555 0000 0001
BEF#
TWPH DQ15-0 XXAA XX55 XX90 00BF
Device
TIDA
F12.6
Device 2761H SST34HF1621 2761H SST34HF1641 Note: VIH, other value
FIGURE
THREE-BYTE SEQUENCE QUERY ENTRY ADDRESS A14-0 5555 2AAA 5555
BEF#
TWPH DQ15-0 XXAA XX55 XX98
F13.2
TIDA
Note: VIH, other value.
FIGURE
©200 Sili Storag chno Inc.
-05-0
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF1621 SST34HF1641
THREE-BYTE SEQUENCE SOFTWARE EXIT RESET
ADDRESS A14-0
5555
2AAA
5555
DQ15-0
XXAA
XX55
XXF0 TIDA
BEF#
F14.3
Note: VIH, other value
FIGURE /CFI
RY/BY# RST#
CE#/OE# TRHR
F29.0
FIGURE RST#
RY/BY# RST#
F30.0
FIGURE RST# R©200 Sili Storag chno Inc.
-05-0
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF1621 SST34HF1641
VIHT
INPUT
REFERENCE POINTS
OUTPUT
VILT
F19.0
test inputs driven (0.9 logic VILT (0.1 logic "0". Measurement reference points inputs outputs (0.5 (0.5 Input rise fall times (10% 90%)
Note: VINPUT Test OUTPUT Test INPU HIGH Test Test
FIGURE
TESTER
F20.0
FIGURE
©200 Sili Storag chno Inc.
-05-0
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF1621 SST34HF1641
Start
Load data: XXAAH Address: 5555H
Load data: XX55H Address: 2AAAH
Load data: XXA0H Address: 5555H
Load Word Address/Word Data
Wait Program (TBP, Data# Polling bit, Toggle operation) Program Completed
F21.4
Note: VIH, other value.
FIGURE
©200 Sili Storag chno Inc.
-05-0
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF1621 SST34HF1641
Internal Timer Program/Erase Initiated
Toggle Program/Erase Initiated
Data# Polling Program/Erase Initiated
Wait TBP, TSCE,
Read word
Read
Program/Erase Completed
Read same word
true data?
Does match? Program/Erase Completed
Program/Erase Completed
F22.0
FIGURE
©200 Sili Storag chno Inc.
-05-0
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF1621 SST34HF1641
Query Entry Command Sequence
Software Product Entry Command Sequence
Software Exit/CFI Exit Command Sequence
Load data: XXAAH Address: 5555H
Load data: XXAAH Address: 5555H
Load data: XXAAH Address: 5555H
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX98H Address: 5555H
Load data: XX90H Address: 5555H
Load data: XXF0H Address: 5555H
Wait TIDA
Wait TIDA
Wait TIDA
Read data
Read Software
Return normal operation
F23.3
Note: VIH, other value.
FIGURE ID/CFI
©200 Sili Storag chno Inc.
-05-0
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF1621 SST34HF1641
Chip-Erase Command Sequence Load data: XXAAH Address: 5555H
Sector-Erase Command Sequence Load data: XXAAH Address: 5555H
Block-Erase Command Sequence Load data: XXAAH Address: 5555H
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX80H Address: 5555H
Load data: XX80H Address: 5555H
Load data: XX80H Address: 5555H
Load data: XXAAH Address: 5555H
Load data: XXAAH Address: 5555H
Load data: XXAAH Address: 5555H
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX10H Address: 5555H
Load data: XX30H Address:
Load data: XX50H Address:
Wait TSCE
Wait
Wait
Chip erased FFFFH
Sector erased FFFFH
Block erased FFFFH
F24.2
Note: VIH, other value.
FIGURE
©200 Sili Storag chno Inc.
-05-0
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF1621 SST34HF1641
PRODUCT ORDERING INFORMATION
Device Speed Suffix1 Suffix2 Package Modifier balls Package Type LFBGA (8mm 10mm 1.4mm, 0.4mm ball size) LFBGA (8mm 10mm 1.4mm, 0.45mm ball size) Temperature Range Commercial +70°C Extended -20°C +85°C Minimum Endurance =10,000 cycles Read Access Speed Bank Split SRAM Density SRAM Mbit Mbit Flash Density Mbit Voltage 2.7-3.3V
SST34 HF16
Valid combinations SST34HF1621 SST34HF1621-70-4C-LFP SST34HF1621-90-4C-LFP SST34HF1621-70-4E-LFP SST34HF1621-90-4E-LFP SST34HF1621-70-4C-L1P SST34HF1621-90-4C-L1P SST34HF1621-70-4E-L1P SST34HF1621-90-4E-L1P
Valid combinations SST34HF1641 SST34HF1641-70-4C-LFP SST34HF1641-90-4C-LFP SST34HF1641-70-4E-LFP SST34HF1641-90-4E-LFP
Note:
SST34HF1641-70-4C-L1P SST34HF1641-90-4C-L1P SST34HF1641-70-4E-L1P SST34HF1641-90-4E-L1P
Valid combinations those products mass production will mass production. Consult your sales representative confirm availability valid combinations determine availability combinations.
©200 Sili Storag chno Inc.
-05-0
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF1621 SST34HF1641
PACKAGING DIAGRAMS
BOTTOM VIEW VIEW
10.00 0.20 5.60 0.80
0.80 CORNER 1.30 0.10 5.60 8.00 0.20
0.40 0.05 (56X) CORNER
SIDE VIEW
0.12 0.32 0.05
56-lfbga-LFP-8x10-400mic-8
SEATING PLANE
Note: Although many dimensions similar those JEDEC Publication MO-210, this specific package registered. linear dimensions millimeters. Coplanarity: 0.12 actual shape corners slightly different than portrayed drawing.
(LFBGA)
Note: This package will replaced which increases ball size from 400-micron 450-micron. Check with factory migration schedule.
©200 Sili Storag chno Inc.
-05-0
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF1621 SST34HF1641
BOTTOM VIEW VIEW
10.00 0.20 5.60 0.80
0.80 CORNER 1.30 0.10 5.60 8.00 0.20
0.45 0.05 (56X) CORNER
SIDE VIEW
0.12 0.35 0.05
SEATING PLANE
56-lfbga-L1P-8x10-450mic-3
Note: Although many dimensions similar those JEDEC Publication MO-210, this specific package registered. linear dimensions millimeters. Coplanarity: 0.12 actual shape corners slightly different than portrayed drawing.
(LFBGA)
Silicon Storage Technology, Inc. 1171 Sonora Court Sunnyvale, 94086 Telephone 408-735-9110 408-735-9036 www.SuperFlash.com www.sst.com
©200 Sili Storag chno Inc. -05-0
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