Skew CMOS Clock Driver Tri-State Versions TS88915T Description

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Skew CMOS Clock Driver Tri-State Versions TS88915T Description

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Military Temperature Range Fully Compatible with TS68040 Five Skew Outputs Five Outputs (Q0-Q4) with Output-to-Output Skew Each Being Phase Frequency Locked SYNC Input Three Additional Outputs Available: 2X_Q Output Runs Twice System Frequency Output Runs System Frequency Output Inverted (180° Phase Shift) Selectable Clock Inputs Selectable CLOCK Inputs Available Test Redundancy Purposes Test Mode (PLL_EN) Provided Frequency Testing Outputs Into High Impedance (3-state) Board Test Purposes Input Frequency Range From 2X_Q FMAX Three Input/Output Ratios Input/Output Phase-locked Frequency Ratios 1:2, Available Part-to-part Skew Phase Variation from Part-to-part Between SYNC FEEDBACK Inputs Less than (Derived From Specification, which Defines Part-to-part Skew) CMOS Compatible Outputs Drive Either CMOS Inputs Inputs TTL-level Compatible LOCK Indicator (LOCK) Indicates Phase-locked State
Skew CMOS Clock Driver Tri-State Versions TS88915T
Description
TS88915T Clock Driver utilizes phazed-locked loop (PLL) technology lock skew outputs' frequency phase onto input reference clock. designed provide clock distribution high performance microprocessors such TS68040, TSPC603E,TSPC603P,TSPC603R, bridge, RAM's, MMU's.
Screening/Quality
This Product Manufactured: Based Upon Generic Flow MIL-STD-883 According Atmel-Grenoble Standard
suffix Ceramic Grid Array
suffix LDCC Leaded Ceramic Chip Carrier
Rev. 2122A-HIREL-06/02
Introduction
TS88915T CMOS Clock Driver using phase-locked loop (PLL) technology. allows high current skew outputs lock onto single input distribute with essentially zero delay multiple components board. also allows TS88915T multiply frequency input clock distribute locally higher (2X) system frequency. Multiple 88915's lock onto single reference clock, which ideal applications when central system clock must distributed synchronously multiple boards (see Figure 12).
Figure TS88915T Block Diagram (All Versions)
FEEDBACK LOCK
SYNC[0]
PHASE/FREQ. DETECTOR
CHARGE PUMP/ LOOP FILTER
SYNC[1]
VOLTAGE CONTROLLED OSCILLATOR
REF_SEL
EXT. NETWORK (RC1 pin)
PLL_EN
2X_Q
(÷1) FREQ_SEL OE/RST
DIVIDE
(÷2)
TS88915T
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TS88915T
Assignments
29-lead Grid Array (PGA)
Figure 29-lead (Bottom View)
F/SL GNDA VCCA SYC0 FDBK R/SL TS88915T (BOTTOM VIEW) SYC1 P/EN LOCK
28-lead Ceramic Leaded Chip Carrier (LDCC)
Figure 28-lead LDCC (Top View)
OE/RST 2X_Q TS88915T (TOP VIEW)
FEEDBACK REF_SEL SYNC[0] (AN) (AN) SYNC[1]
LOCK
FREQ_SEL
PLL_EN
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Signal Description
Table Signal Index
Name SYNC[0] SYNC[1] REF_SEL FREQ_SEL FEEDBACK Q(0-4) 2x_Q LOCK OE/RST PLL_EN VCC, Input Input Input Input Input Input Output Output Output Output Output Input Input Power Signal Function Reference Clock Input Reference Clock Input Chooses Reference Between SYNC[0] SYNC[1] Doubles Internal Frequency Feedback Input Phase Detector Input External Network Clock Output (Locked SYNC) Inverse Clock Output Clock Output Frequency (Synchronous) Clock Output Frequency (Synchronous) Indicates Phase Lock been Achieved (High when Locked) Output Enable/Asynchronous Reset (Active Low) Disables Phase-lock Frequency Testing Power Ground pins Pins "analog" supply pins internal only
Scope Applicable Documents Requirements
General Design Construction
Terminal Connections
This drawing describes specific requirements clock driver TS88915T, compliance with MIL-STD-883 class Atmel standard screening. MIL-STD-883: Test methods procedures electronics. MIL-PRF-38535 appendix General specifications microcircuits.
microcircuits accordance with applicable documents specified herein.
Depending package, terminal connections shall shown Figure Figure Lead material finish shall specified MIL-STD-1835 (see "Package Mechanical Data" page 17). macrocircuits packaged hermetically sealed ceramic packages, which conform case outlines MIL-STD-1835, "Package Mechanical Data" page precise case outlines described specification (see "Package Mechanical Data" page 178) into MIL-STD-1835.
Lead Material Finish
Package
TS88915T
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TS88915T
Absolute Maximum Ratings
Stresses above absolute maximum rating cause permanent damage device. Extended operation maximum levels degrade performance affect reliability. Table Absolute Maximum Rating TS88915T
Parameter Supply Voltage Input Voltage Storage Temperature Range Power Dissipation Package LDCC Package Thermal Resistance Junction-Case PGA29 LDCC28 Note: Symbol Tstg -0.5 -0.5 +150 Unit
°C/W
Functional operating conditions given electrical specifications. Stresses beyond absolute maximums listed affect device reliability cause permanent damage device. Caution: Input voltage must greater than supply voltage more than 2.5V times including during power-on reset.
Mechanical Environment Marking
microcircuits shall meet environmental requirements either MIL-STD-883 class devices Atmel standard screening. document that defines markings identified related reference documents. Each microcircuit legible permanently marked with following information minimum: Atmel Logo Manufacturer's Part Number Class Identification Date-code Inspection Identifier Available Country Manufacturing
Electrical Characteristics
General Requirements
static dynamic electrical characteristics specified inspection purposes relevant measurement conditions given below: Table Static Electrical Characteristics Electrical Variants Table Dynamic Electrical Characteristics TS88915T Versions)
2122A-HIREL-06/02
Static Characteristics
Electrical Characteristics (Voltages Referenced GND) -55°C +125°C version; 5.0V
Symbol Parameter Minimum High-Level Input Voltage Maximum Low-Level Input Voltage Minimum High-Level Output Voltage Test Conditions Vout 0.1V 0.1V Vout 0.1V 0.1V VIL, mA(1) VIL, mA(1) ICCT Notes: Maximum Low-Level Output Voltage VIL, mA(6) Maximum Input Leakage Current Maximum ICC/Input Maximum Quiescent Supply Current (per package) GND, VCCmax 2.1V, VCCmax GND, VCCmax VCCmin VCCmax Limits 4.01 4.51 0.44(4) 0.50(5) 0.20 ±1.0
Unit
Maximum Tri-State Leakage Current VIL,VO GND, VCCmax respectively LOCK output. PLL_EN input guaranteed meet this specification. Maximum test duration output loaded time. Specification value static tests 25°C minimum rated operating temperature. Specification value static tests maximum rated operating temperature. Specifications values which used compability with Power
Capacitance Power Specifications
Symbol Note: Parameter Input Capacitance Power Dissipation Capacitance Power Dissipation with Thevenin Termination Power Dissipation with Parallel Termination mW/Output output. Typical Values mW/Output mW/Device mW/Output mW/Device Unit Conditions 5.0V 5.0V 5.0V 25°C 5.0V 25°C
Dynamic Characteristics
Frequency Specifications
-55°C +125°C, 5.0V
Guaranteed Minimum Symbol fmax(1) Note: Parameter Maximum Operating Frequency (2X_Q Output) 88915T-70 88915T-100 Unit
Maximum Operating Frequency (Q0-Q4, Outputs) Maximum Operating Frequency guaranteed with part phase-locked condition, outputs loaded with terminated VCC/2.
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SYNC Input Timing Requirements
Minimum Symbol tRISE/FALL, SYNC Inputs tCYCLE, SYNC Inputs Parameter Rise/Fall Time, SYNC Inputs From 2.0V Input Clock Period, SYNC Inputs 88915T-70 28.5(1) 88915T-100 20.0(1) Maximum 200(2) Unit
Duty Cycle SYNC Inputs Input Duty Cycle, SYNC Inputs Notes: These tCYCLE minimum values valid when output feed back connected FEEDBACK pin. Information Table Note specification notes describe this specification limits depending what output feed back, FREQ_SEL high low.
Characteristics -55°C +125°C, 5.0V Load terminated VCC/2)
Symbol tRISE/FALL Outputs tRISE/FALL(1) 2X_Q Output tPULSE WIDTH(1) (Q0-Q4, Q/2) tPULSE WIDTH(1) (2X_Q Output) Parameter Rise/Fall Time, Outputs (Between VCC) Rise/Fall Time into Load, with Termination(2) Output Pulse Width: VCC/2 Output Pulse Width: 2X_Q 1.5V 40-49 50-65 66-100 Unit Conditions Into Load Terminated VCC/2 tRISE: 0.8V 2.0V tFALL: 2.0V 0.8V Into Load Terminated VCC/2 Must termination(2)
0.5tCYCLE 0.5(2)
0.5tCYCLE 0.5(2)
0.5tCYCLE 1.5(2) 0.5tCYCLE 0.5tCYCLE 0.5tCYCLE 0.5tCYCLE 1.5(2) 0.5tCYCLE 0.5tCYCLE
0.5tCYCLE 1.5(2) 0.5tCYCLE 0.5tCYCLE 0.5tCYCLE 0.5tCYCLE 1.5(2) 0.5tCYCLE 0.5tCYCLE
tPULSE WIDTH(1) (2X_Q Output)
Output Pulse Width: 2X_Q VCC/2
Into Load Terminated VCC/2 Note Figure detailed explanation
tPD(1)(3) SYNC Feedback
SYNC Input Feedback Delay (Measured SYNC0 FEEDBACK input pins)
(With from VCC) -1.05 -1.05 -0.40 -0.30
(With from GND) +1.25 tSKEWr (Rising)(5)
(1)(4)
+3.25 Outputs into matched load Terminated VCC/2 Outputs into matched load Terminated VCC/2 Outputs into matched load Terminated VCC/2
Output-to-Output Skew between Outputs Q0-Q4, (Rising edges only)
tSKEWf (1)(4) (Falling)
Output-to-Output Skew between Outputs Q0-Q4 (Falling edges only)
tSKEWall (1)(4) (Falling)
Output-to-Output Skew 2X_Q, Q/2, Q0-Q4 Rising, Falling
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Characteristics -55°C +125°C, 5.0V Load terminated VCC/2) (Continued)
Symbol tLOCK(5) tPZL Parameter Time required acquire Phase-Lock from time SYNC inputs signal received Output Enable Time OE/RST 2X_Q, Q0Q4, Output Disable Time OE/RST 2X_Q, Q0Q4, Unit Conditions Also time lock indicator High Measured with PLL_EN
tPHZ, tPLZ
Notes:
Measured with PLL_EN These specifications tested, they guaranteed statistical characterization. General specification Note tCYCLE this specification 1/Frequency which particular output running. specification's min/max values shift closer zero larger pull resistor used. Under equally loaded conditions fixed temperature voltage. With fully powered-on, output properly connected FEEDBACK pin. tLOCK maximum with tLOCK minimum with 0.01
Figure Output/Input Switching Waveforms Timing Diagrams (These waveforms represent hook-up configuration Figure
SYNC INPUT (SYNC[1] SYNC[0])
tCYCLE SYNC INPUT
FEEDBACK INPUT
OUTPUT
tSKEWall
tSKEWr
tSKEWf
tSKEWr
Q0-Q4 OUTPUTS tCYCLE OUTPUTS
OUTPUT
2X_Q OUTPUT
TS88915T
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TS88915T
Application Information
General Specification Several specifications only measured when TS88915T phaselocked operation. TS88915T units fabricated with transistor properties Notes
intentionally varied create cell designed experimental matrix. These specs (tRISE/FALL tPULSE WIDTH 2X_Q output) guarantee that TS88915T meets TS68040 P-Clock input specification MHz). these specs guaranteed Atmel, termination scheme shown below Figure must used. Figure TS68040 P-Clock Input Termination Scheme
TS88915 2X_Q Output (CLOCK TRACE) TS68040 P_Clock Input 1.5Z0
Z0-7
meet TS68040 P-clock input specification tpulse width MHz) FREQ-SEL must low. This configuration improve accuracy 88915T duty cycle. wiring diagrams explanations Figure Figure Figure demonstrate input output frequency relationships three possible feedback configurations. allowable SYNC input range each case also indicated. There allowable SYNC frequency ranges, depending whether FREQ_SEL high low. Although shown, possible feed back output, thus creating 180° phase shift between SYNC input outputs. Table below summarizes allowable SYNC frequency range each possible configuration. Table Allowable SYNC Input Frequency Range Different Feedback Configurations
FREQ_SEL Level HIGH HIGH HIGH HIGH FEEDBACK Output (Q0-Q4) 2X_Q (Q0-Q4) 2X_Q Allowable SYNC Input Frequency Range (MHz) (2X_Q FMAX Spec)/4 (2X_Q FMAX Spec)/2 (2X_Q FMAX Spec)/2 (2X_Q FMAX Spec) (2X_Q FMAX Spec)/8 (2X_Q FMAX Spec)/4 (2X_Q FMAX Spec)/4 (2X_Q FMAX Spec)/2 Corresponding Frequency Range (2X_Q FMAX Spec) (2X_Q FMAX Spec) (2X_Q FMAX Spec) (2X_Q FMAX Spec) (2X_Q FMAX Spec) (2X_Q FMAX Spec) (2X_Q FMAX Spec) (2X_Q FMAX Spec) Phase Relationships Outputs Rising SYNC Edge 180° 180°
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resistor tied either Analog Analog shown Figure required ensure jitter present TS88915T outputs. This technique causes phase offset between SYNC input output connected FEEDBACK input, measured input pins. spec describes this offset varies with process, temperature voltage. specs arrived measuring phase relationship lots described Note while part phase-locked operation. actual measurements made with SYNC input (1.0 edge rate from 0.8V 2.0V) with output feed back. phase measurements made 1.5V. output terminated FEEDBACK input with GND. Figure Depiction Fixed SYNC Feedback Offset (tPD) Which Present When Resistor Tied
EXTERNAL LOOP FILTER REFERENCE RESISTOR ANALOG With resistor tied this fashion, specification measured input pins -0.775 0.275 REFERENCE RESISTOR
With resistor tied this fashion, specification measured input pins 2.25
3.0V SYNC INPUT 2.25 OFFSET FEEDBACK OUTPUT 5.0V FEEDBACK OUTPUT SYNC INPUT
3.0V -0.775 OFFSET 5.0V
tSKEWr specification guarantees that rising edges outputs Q/2, will always fall within window within part. However, relative position each output within this window specified, window must added each side specification limits calculate total part-to-part skew. this reason absolute distribution these outputs provided Table When taking skew data, used reference, measurements relative this output. information Table derived from measurements taken from process lots described Note over temperature voltage range.
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Table Relative Position Outputs Q/2, Q0-Q4, 2X_Q,Within tSKEWr Spec Window
Output 2X_Q (ps) -274 -633 (ps)
Calculation Total Output-to-Output skew Between Multiple Parts (Part-to-Part Skew) combining specification information Note worst case Output-to-Output skew between multiple TS88915's connected parallel calculated. This calculation assumes that parts have common SYNC input clock with equal delay that input signal each part. This skew value valid TS88915 output pins only (equally loaded), does include trace delays varying loads.With resistor tied analog shown Note spec. limits between SYNC output (connected FEEDBACK pin) -1.05 -0.5 calculate skew given output between more parts, absolute value distribution that output given Table must subtracted added lower upper spec limits respectively. output [276-(-44)] absolute value distribution. Therefore [-1.05 0.32] -1.37 lower limit, [0.5 0.32] -0.18 upper limit. Therefore worst case skew output between number part [(-1.37)-(-0.18)] 1.19 worst case skew distribution output, absolute worst case Output-to-Output skew between multiple parts. Note explains that specification measured guaranteed configuration output connected FEEDBACK SYNC input running MHz. fixed offset (tPD) described above some dependence input frequency what frequency running. graphs Figure demonstrate this dependence. data presented Figure from devices representing process extremes, measurements were also taken voltage extremes (VCC 5.25V 4.75V). Therefore data Figure realistic representation variation tPD.
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Figure
-0.50 -0.50
-0.75
SYNC FEEDBACK -1.00 (ns)
-1.25
-1.00 SYNC FEEDBACK (ns)
-1.50
-1.50
-2.00 10.0 12.5 15.0 17.5 12.5 17.5 22.5 27.5 SYNC INPUT FREQUENCY (MHz) SYNC INPUT FREQUENCY (MHz)
versus Frequency output feed back, including process voltage variation 25°C (with resistor tied analog VCC)
versus Frequency output feed back, including process voltage variation 25°C (with resistor tied analog VCC)
SYNC FEEDBACK (ns)
10.0 12.5 15.0 17.5 SYNC INPUT FREQUENCY (MHz)
SYNC FEEDBACK (ns)
SYNC INPUT FREQUENCY (MHz)
versus Frequency output feed back, including process voltage variation 25°C (with resistor tied analog GND)
versus Frequency output feed back, including process voltage variation 25°C (with resistor tied analog GND)
Lock indicator (LOCK) will reliably indicate phase-locked condition SYNC input frequencies down MHz. frequencies below MHz, frequency correction pulses going into phase detector from SYNC FEEDBACK pins sufficient allow lock indicator circuitry accurately predict phase-locked condition. TS88915T guaranteed provide stable phase-locked operation down appropriate minimum input frequency given Table even though LOCK frequencies below MHz.
Timing Notes
TS88915T aligns rising edges FEEDBACK input SYNC input, therefore SYNC input does require duty cycle. skew specs measured between VCC/2 crossing point appropriate output edges. skews specified `windows', "deviation around center point". output connected FEEDBACK input (this situation shown), output frequency would match SYNC input frequency, 2X_Q out-
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would twice SYNC frequency, output would half SYNC frequency. Figure Figure Figure below. Figure Wiring Diagram Frequency Relationship with Output Feed Back
SIGNAL FEEDBACK SIGNAL
HIGH
2X_Q
FEEDBACK CRYSTAL INPUT
OSC. EXTERNAL LOOP FILTER
REF_SEL SYNC[0] ANALOG ANALOG
CLOCK OUTPUTS
FQ_SEL
PLL_EN
HIGH
HIGH
Figure Wiring Diagram Frequency Relationship with Output Feed Back
FEEDBACK SIGNAL
HIGH
2X_Q
SIGNAL
FEEDBACK
CRYSTAL INPUT OSC. EXTERNAL LOOP FILTER
SIGNAL
REF_SEL SYNC[0] ANALOG ANALOG
CLOCK OUTPUTS
FQ_SEL
PLL_EN
HIGH HIGH
Figure Wiring Diagram Frequency Relationship with 2X_Q Output Feed Back
FEEDBACK SIGNAL
HIGH
2X_Q
FEEDBACK REF_SEL
CRYSTAL INPUT SYNC[0] OSC. EXTERNAL LOOP FILTER
SIGNAL
ANALOG ANALOG
CLOCK OUTPUTS
FQ_SEL
PLL_EN
HIGH
HIGH
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Notes Concerning Loop Filter Board Layout Issues
Figure shows loop filter analog isolation scheme which will effective most applications. following guidelines should followed ensure stable jitter-free operation: loop filter analog isolation components should tied close package possible. Stray current passing through parasitics long traces cause undesirable voltage transients pin. resistors, frequency bypass capacitor, high frequency bypass capacitor form wide bandwidth filter that will minimize 88915T's sensitivity voltage transients from system digital supply ground planes. This filter will typically ensure that step deviation digital supply will cause more than phase deviation 88915T outputs. step deviation using recommended filter values should cause more than phase deviation; bypass capacitor used (instead step should cause more than phase deviation. good bypass techniques used board design near components which cause digital ground noise, above described step deviations should occur 88915T's digital supply. purpose bypass filtering scheme shown Figure give 88915T additional protection from power supply ground plane transients that occur high frequency, high speed digital system. There special requirements forth loop filter resistors 330). loop filter capacitor (0.1 ceramic chip capacitor, same standard bypass capacitor. reference resistor injects current into internal charge pump PLL, causing fixed offset between outputs SYNC input. This also prevents excessive jitter caused inherent dead-band. (2X_Q output) running above MHz, resistor provides correct amount current injection into charge pump (2-3 µA). versions, running below MHz, resistor should used (instead addition bypass capacitors used analog filter Figure there should bypass capacitor between each other (digital) four pins board ground plane. This will reduce output switching noise caused 88915T outputs, addition reducing potential noise `analog' section chip. These bypass capacitors should also tied close package possible.
TS88915T
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TS88915T
Figure Recommended Loop Filter Analog Isolation Scheme TS88915T
BOARD
ANALOG FREQ BYPASS HIGH FREQ BYPASS ANALOG LOOP FILTER/FCO SECTION TS88915T (NOT DRAWN SCALE)
ANALOG
Note:
separate analog power supply necessary should used. Following these prescribed guidelines that necessary TS88915T normal digital environment.
Figure Representation Potential Multi-Processing Application Utilizing TS88915T Frequency Multiplication Board-to-board Skew
CMMU TS88915T CMMU CARD
CLOCK
CMMU
CMMU SYSTEM CLOCK SOURCE CMMU TS88915T DISTRIBUTE CLOCK
CMMU
CMMU
CARD
CMMU
CMMU CLOCK POINT
CMMU
TS88915T
MEMORY CONTROL
MEMORY CARDS CLOCK POINT
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TS88915T System Level Testing Functionality
Tri-State functionality been added TS88915T ease system board testing. Bringing OE/RST will outputs (except LOCK) into high impedance state. long PLL_EN low, Q0-Q4, outputs will remain state after OE/RST until falling SYNC edge seen. 2X_Q output will inverse SYNC signal this mode. tri-state functionality will used, pull-up pull-down resistor must tied FEEDBACK input prevent from floating when feedback output goes into high impedance. With PLL_EN selected SYNC signal gated directly into signal clock distribution network, bypassing disabling VCO. this mode outputs directly driven SYNC input (per block diagram). This mode also used frequency board testing. Note: outputs into 3-state during normal operation, loop will broken phase-lock will lost. will take maximum (tLOCK spec) regain phase-lock after OE/RST goes back high.
Preparation Delivery
Packaging
Microcircuits prepared delivery accordance with MIL-PRF-38535.
Certificate Compliance Atmel offers certificate compliances with each shipment parts, affirming products compliance either with MIL-STD-883 guarantying parameters tested temperature extremes entire temperature range.
Handling
devices must handled with certain precautions avoid damage accumulation static charge. Input protection devices have been designed chip minimize effect this static buildup. However, following handling practices recommended: Devices Should Handled Benches With Conductive Grounded Surfaces Ground Test Equipment, Tools Operator Handle Devices Leads. Store Devices Conductive Foam Carriers. Avoid Plastic, Rubber, Silk Areas. Maintain Relative Humidity Above Percent Practical.
TS88915T
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TS88915T
Package Mechanical Data
29-pin
Inches 0.017 0.594 0.17 0.045 0.045 0.100 0.019 0.43 0.606 0.107 0.19 0.055 0.055 15.087 4.32 1.143 1.143
Millimeters 15.392 2.72 4.83 1.397 1.397 2.54 0.48
2122A-HIREL-06/02
28-pin LDCC
Note:
This package compatible with PLCC
Ordering Information
TS88915T
Device Type
Maximum Output Frequency 100:
Temperature range -55, +125°C -40, +85°C
Screening level Standard B/T: according MIL-STD-883 D/T: Burn-in Package LDCC
Note:
availability different versions, contact your Atmel sales office.
TS88915T
2122A-HIREL-06/02
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2122A-HIREL-06/02

Skew CMOS Clock Driver Tri-State Versions TS88915T Description

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