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SAA7108AE; SAA7109AE HD-CODEC Product specification 2003 Phi


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SAA7108AE; SAA7109AE HD-CODEC
Product specification 2003
Philips Semiconductors
Product specification
HD-CODEC
CONTENTS 8.10 8.11 8.12 8.13 8.14 8.15 8.16 8.17 8.18 8.19 8.20 8.21 FEATURES Video decoder Video scaler Video encoder Common features APPLICATIONS GENERAL DESCRIPTION ORDERING INFORMATION QUICK REFERENCE DATA BLOCK DIAGRAMS PINNING FUNCTIONAL DESCRIPTION DIGITAL VIDEO ENCODER PART Reset conditions Input formatter Cursor insertion Y-CB-CR matrix Horizontal scaler Vertical scaler anti-flicker filter FIFO Border generator Oscillator Discrete Time Oscillator (DTO) Low-pass Clock Generation Circuit (CGC) Encoder processor Triple data path Timing generator Pattern generator sync pulses I2C-bus interface Power-down modes Programming graphics acquisition scaler video encoder Input levels formats FUNCTIONAL DESCRIPTION DIGITAL VIDEO DECODER PART Decoder Decoder output formatter Scaler VBI-data decoder capture (subaddresses 7FH) Image port output formatter (subaddresses 87H) Audio clock generation (subaddresses 3FH) 10.1 10.2 10.3 10.4 10.5 10.6 10.7 11.1 11.2 16.1 16.2 17.1 17.2 17.3 18.1 18.2 19.1 19.2 19.3 19.4
SAA7108AE; SAA7109AE
INPUT/OUTPUT INTERFACES PORTS DIGITAL VIDEO DECODER PART Analog terminals Audio clock signals Clock real-time synchronization signals Video expansion port port) Image port port) Host port 16-bit extension video data port) Basic input output timing diagrams ports BOUNDARY SCAN TEST Initialization boundary scan circuit Device identification codes LIMITING VALUES THERMAL CHARACTERISTICS CHARACTERISTICS DIGITAL VIDEO ENCODER PART CHARACTERISTICS DIGITAL VIDEO DECODER PART TIMING Digital video encoder part Digital video decoder part APPLICATION INFORMATION Reconstruction filter Analog output voltages Suggestions board layout I2C-BUS DESCRIPTION Digital video encoder part Digital video decoder part PROGRAMMING START SET-UP DIGITAL VIDEO DECODER PART Decoder part Audio clock generation part Data slicer data type control part Scaler interfaces PACKAGE OUTLINE SOLDERING DATA SHEET STATUS DEFINITIONS DISCLAIMERS PURCHASE PHILIPS COMPONENTS
2003
Philips Semiconductors
Product specification
HD-CODEC
FEATURES Video decoder
SAA7108AE; SAA7109AE
analog inputs, internal analog source selectors, e.g. CVBS CVBS) CVBS) analog preprocessing channels differential CMOS style best performance Fully programmable static gain Automatic Gain Control (AGC) selected CVBS channel Switchable white peak control built-in analog anti-aliasing filters 9-bit video CMOS Analog-to-Digital Converters (ADCs), digitized CVBS signals available Image Port Data (IPD) port under I2C-bus control On-chip clock generator Line-locked system clock frequencies Digital horizontal sync processing clock generation, horizontal vertical sync detection Requires only crystal (either 24.576 32.11 MHz) standards Automatic detection field frequency, automatic switching between NTSC standards Luminance chrominance signal processing BGHI, combination NTSC NTSC-Japan, NTSC NTSC 4.43 SECAM User programmable luminance peaking aperture correction Cross-colour reduction NTSC chrominance comb filtering delay line correcting phase errors Brightness Contrast Saturation (BCS) control on-chip multi functional real-time output pins controlled I2C-bus Multi-standard data slicer decoding World Standard Teletext (WST), North-American Broadcast Text System (NABTS), Closed Caption (CC), Wide Screen Signalling (WSS), Video Programming System (VPS), Vertical Interval Time Code (VITC) variants (EBU/SMPTE) etc. Standard Y-CB-CR format (8-bit) output
Macrovisionis trademark Macrovision Corporation.
Enhanced output format output containing: active video CVBS data INTERCAST applications data rate) decoded data Detection copy protected input signals according MacrovisionTM(1) standard. used prevent unauthorized recording pay-TV video tape signals. Video scaler
Both downscaling Conversion square pixel format NTSC lines (video phone) Phase accuracy better than 1/64 pixel line, horizontally vertically Independent scaling definitions even fields Anti-alias filter horizontal scaling Provides output scaled active video CVBS data INTERCAST, WAVE-PHORE, POPCON applications general data decoding sample rate converted) Local video output Y-CB-CR format (VMI, VIP, ZV).
2003
Philips Semiconductors
Product specification
HD-CODEC
Video encoder
SAA7108AE; SAA7109AE
Adjustable output levels DACs Programmable horizontal vertical input synchronization phase Programmable horizontal sync output phase Internal Colour Generator (CBG) Optional support various Vertical Blanking Interval (VBI) data insertion Macrovision Pay-per-View copy protection system rev. 7.01, rev. rev. 1.03 (525p) option; this applies SAA7108AE only. device protected patent numbers 4631603, 4577216 4819098 other intellectual property rights. Macrovision anti-copy process device licensed non-commercial home only. Reverse engineering disassembly prohibited. Please contact your nearest Philips Semiconductors sales office more information. Common features
Digital PAL/NTSC encoder with integrated high quality scaler anti-flicker filter output from Supports Intel® Digital Video (DVO) voltage interfacing graphics controller crystal-stable subcarrier generation Maximum graphics pixel clock double edged clocking, synthesized on-chip from external source Programmable assignment clock edge bytes double edged mode) Synthesizable pixel clock (PIXCLK) with minimized output jitter, used reference clock VGC, well PIXCLK output bi-phase PIXCLK input (VGC clock loop-through possible) Hot-plug detection through dedicated interrupt Supported resolutions NTSC legacy video output 1280 1024 graphics data frame rate Supported resolutions HDTV output 1920 1080 interlaced graphics data frame rate Three Digital-to-Analog Converters (DACs) CVBS (BLUE, CB), (GREEN, CVBS) (RED, sample rate (signals parenthesis optionally selected), 10-bit resolution Non-interlaced CB-Y-CR input maximum sampling Downscaling upscaling from 400% Optional interlaced CB-Y-CR input Digital Versatile Disk (DVD) signals Optional non-interlaced output drive second monitor (bypass mode, maximum MHz) bytes Look-Up Table (LUT) Support hardware cursor HDTV 1920 1080 interlaced 1280 progressive, including 3-level sync pulses Programmable border colour underscan area Programmable line anti-flicker filter On-chip crystal oscillator (3rd-harmonic fundamental crystal) Fast I2C-bus control port (400 kHz) Encoder master slave
tolerant digital ports I2C-bus controlled (full read-back ability external controller, rate kbits/s) Versatile power-save modes Boundary scan test circuit complies with "IEEE Std. 1149.b1-1994" (separate codes decoder encoder) Monolithic CMOS device BGA156 package Moisture Sensitive Level (MSL): APPLICATIONS
Notebook (low-power consumption) PCMCIA card application based graphics cards editing Image processing Video phone applications INTERCAST teletext applications Security applications Hybrid satellite set-top boxes.
2003
Philips Semiconductors
Product specification
HD-CODEC
GENERAL DESCRIPTION
SAA7108AE; SAA7109AE
inputs intended interface host graphics controller designed low-voltage signals down 3.45 video decoder, 9-bit video input processor, combination 2-channel analog pre-processing circuit including source selection, anti-aliasing filter Analog-to-Digital Converter (ADC), automatic clamp gain control, Clock Generation Circuit (CGC), digital multi-standard decoder (PAL BGHI, combination NTSC NTSC-Japan, NTSC NTSC 4.43 SECAM). decoder includes brightness, contrast saturation control circuit, multi-standard data slicer data bypass. pure compatible) CMOS circuit SAA7108AE; SAA7109AE, consisting analog front-end digital video decoder, digital video encoder analog back-end, highly integrated circuit especially designed desktop video applications. decoder based principle line-locked clock decoding able decode colour PAL, SECAM NTSC signals into ITU-R BT.601 compatible colour component values. encoder operate fully independently variable pixel clock, transporting graphics input data, line-locked, single crystal-stable video encoding clock. option, possible slave video PAL/NTSC encoding video decoder clock with encoder FIFO acting buffer decouple line-locked decoder clock from crystal-stable encoder clock.
SAA7108AE; SAA7109AE multi-standard video decoder encoder chip, offering high quality video input output processing required PC-99 specifications. enables hardware manufacturers implement versatile video functions significantly reduced printed-circuit board area very competitive costs. Separate pins supply voltages well I2C-bus control boundary scan test have been provided video encoder decoder sections ensure both flexible handling optimized noise behaviour. video encoder used encode graphics data maximum 1280 1024 resolution (optionally 1920 1080 interlaced) NTSC video signals. programmable scaler anti-flicker filter (maximum lines) ensures properly sized flicker-free display CVBS S-video output. Alternatively, three Digital-to-Analog Converters (DACs) output signals together with composite sync feed SCART connectors. When scaler/interlacer bypassed, second monitor connected outputs separate V-syncs well, thereby serving auxiliary monitor maximum 1280 1024 resolution/60 (PIXCLK MHz). Alternatively this port provide signals HDTV monitors. encoder section includes sync/clock generator on-chip DACs.
ORDERING INFORMATION TYPE NUMBER PACKAGE NAME BGA156 DESCRIPTION plastic ball grid array package; balls; body 1.15 VERSION SOT472-1
SAA7108AE SAA7109AE
2003
Philips Semiconductors
Product specification
HD-CODEC
QUICK REFERENCE DATA SYMBOL VDDD VDDA Tamb PA+D Note PARAMETER digital supply voltage analog supply voltage ambient temperature analog digital power dissipation note
SAA7108AE; SAA7109AE
CONDITIONS
MIN. 3.15 3.15
TYP.
MAX. 3.45 3.45
UNIT
Power dissipation extremely dependent programming selected application. BLOCK DIAGRAMS
handbook, full pagewidth
digital video input output port
analog video input
CVBS,
ANALOG VIDEO ACQUISITION DEMODULATOR
SCALER
port (IPD)
digital video output
VIDEO DECODER PART VIDEO ENCODER PART digital video Y-CB-CR/RGB graphics input SCALER INTERLACER VIDEO ENCODER CVBS, analog video output
MHB903
Fig.1 Simplified block diagram.
2003
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PD11 INPUT FORMATTER FIFO UPSAMPLING CURSOR Y-CB-CR MATRIX DECIMATOR PIXCLKI FIFO BORDER GENERATOR VIDEO ENCODER OUTPUT TRIPLE HORIZONTAL SCALER VERTICAL SCALER VERTICAL FILTER BLUE_CB_CVBS GREEN_VBS_CVBS RED_CR_C_CVBS
Philips Semiconductors
HD-CODEC
Fig.2 Block diagram (video encoder part).
andbook, full pagewidth
SAA7108AE SAA7109AE
PIXEL CLOCK SYNTHESIZER CRYSTAL OSCILLATOR XTALIe XTALOe TTX_SRES VSVGC HSVGC SDAe SCLe RESe TIMING GENERATOR I2C-BUS CONTROL PIXCLKO FSVGC TTXRQ_XCLKO2
HSM_CSYNC
SAA7108AE; SAA7109AE
MBL785
Product specification
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full pagewidth
AI12 AI21 AI22
ANALOG DUAL
AI23 AI24 AOUT AI1D AI2D AGND
DIGITAL DECODER WITH ADAPTIVE COMB FILTER
EVENT CONTROLLER
IMAGE PORT MAPPING
2003
RESd XTOUTd XTALId XTALOd AI11
Philips Semiconductors
HD-CODEC
LLC2
RTS0
XCLK
[7:0]
XTRI [7:0] SDAd SCLd
TEST5
TEST3
TEST1 TEST0
RTCO
RTS1
XRDY
TEST4
TEST2
A13, D12, C12, B12, A12, C11, B11, CONTROL
REAL-TIME OUTPUT
EXPANSION PORT MAPPING
I2C-BUS
PORT FORMATTING CLOCK GENERATION POWER-ON CONTROL
chrominance 16-bit input
PROGRAMMING REGISTER ARRAY
REGISTER
SAA7108AE SAA7109AE
E14, D14, C14, B14, E13, D13, C13,
[7:0] IGPH IGPV IGP0 IGP1
FIR-PREFILTER HORIZONTAL LINE VERTICAL PRESCALER FINE FIFO SCALING (PHASE) BUFFER SCALER SCALING
VIDEO FIFO
BOUNDARY SCAN TEST
AUDIO CLOCK GENERATION
GENERAL PURPOSE DATA SLICER
TEXT FIFO
8(16)
ICLK
D11, F11, D10, G11, E11, H11, J11, N12, VDDId VDDEd VDDAd VSSId VSSEd VSSAd VIDEO/TEXT ARBITER
ITRDY ITRI
SAA7108AE; SAA7109AE
TCLKd TDId
ASCLK
MBL791
AMCLK
VDDXd
TRSTd TMSd TDOd
ALRCLK AMXCLK
VSSXd
Product specification
pins RTCO ALRCLK used configuration I2C-bus interface definition crystal oscillator frequency RESET (pin strapping).
Fig.3 Block diagram (video decoder part).
Philips Semiconductors
Product specification
HD-CODEC
PINNING SYMBOL TRSTe XTALIe XTALOe DUMP VSSXe RSET VDDAe HPD0 HPD3 HPD7 TDIe VDDAe DUMP VSSAe VDDAe TEST1 HPD1 HPD4 IPD0 IPD4 PD11 PD10 TTX_SRES TTXRQ_XCLKO2 VSSIe BLUE_CB_CVBS 2003 TYPE(1) I/pu I/pu
SAA7108AE; SAA7109AE
DESCRIPTION encoder input with CB-Y-CR Tables assignment encoder input with CB-Y-CR Tables assignment test reset input Boundary Scan Test (BST) (encoder); active LOW; with internal pull-up; notes crystal input (encoder) crystal output (encoder) reference (encoder), resistor connected VSSAe ground oscillator (encoder) reference (encoder), resistor connected VSSAe analog supply voltage (encoder) Host Port Data (HPD) output output output Tables assignment with different encoder input formats Tables assignment with different encoder input formats encoder input with CB-Y-CR Tables assignment encoder input with CB-Y-CR Tables assignment test data input (encoder); note analog supply voltage (encoder) reference (encoder); connected analog ground (encoder) analog supply voltage (encoder) scan test input connect output output output Image Port Data (IPD) output Tables assignment with different encoder input formats Tables assignment with different encoder input formats teletext input sync reset input (encoder) teletext request output 13.5 clock output crystal oscillator (encoder) digital ground core (encoder) BLUE CVBS output
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
SYMBOL GREEN_VBS_CVBS RED_CR_C_CVBS VDDAe TEST2 HPD2 HPD5 IPD1 IPD5 TDOe RESe TMSe VDDIEe VSSIe VDDXe HSM_CSYNC VDDAe VDDEd VDDId HPD6 IPD2 IPD6 TCKe SCLe HSVGC VSSEe VSSId n.c. IPD3 IPD7 VSVGC PIXCLKI VDD(DVO) VDDId IGPV IGP0
TYPE(1) I/pu I/pu
DESCRIPTION GREEN CVBS output CVBS output analog supply voltage (encoder) scan test input connect output output output output test data output (encoder); note reset input (encoder); active test mode select input (encoder); note digital supply voltage core peripheral cells (encoder) digital ground core (encoder) supply voltage oscillator (encoder) vertical synchronization output monitor (non-interlaced) horizontal synchronization output monitor (non-interlaced) composite sync RGB-SCART analog supply voltage (encoder) digital supply voltage peripheral cells (decoder) digital supply voltage core (decoder) output output output test clock input (encoder); note I2C-bus serial clock input (encoder) horizontal synchronization output Video Graphics Controller (VGC) (optional input) digital ground peripheral cells (encoder) digital ground core (decoder) connected output output vertical synchronization output (optional input) pixel clock input (looped through) encoder input with CB-Y-CR Tables assignment digital supply voltage cells digital supply voltage core (decoder) Detector; hot-plug interrupt pin, HIGH connected multi-purpose vertical reference output with output general purpose output signal with output
2003
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
SYMBOL FSVGC SDAe PIXCLKO VDDEd IGPH IGP1 ITRI VSSEd VSSEd ICLK TEST0 TEST4 TEST5 TEST3 VDDId VDDId AMXCLK ALRCLK
TYPE(1) I/(O) (I/)O
DESCRIPTION frame synchronization output (optional input) I2C-bus serial data input/output (encoder) composite blanking output VGC; active pixel clock output digital supply voltage peripheral cells (decoder) multi-purpose horizontal reference output with output general purpose output signal with output programmable control signals output encoder input with CB-Y-CR Tables assignment encoder input with CB-Y-CR Tables assignment encoder input with CB-Y-CR Tables assignment digital ground peripheral cells (decoder) digital ground peripheral cells (decoder) clock output (optional clock input) scan test output, connect data qualifier output scan test output, connect scan test input, connect scan test input, connect digital supply voltage core (decoder) digital supply voltage core (decoder) audio master external clock input audio left/right clock output; strapped supply resistor indicate that default 24.576 crystal (ALRCLK internal pull-down) been replaced 32.110 crystal (ALRCLK notes target ready input output control signal port pins digital ground core (decoder) digital ground core (decoder) audio master clock output, must less than crystal clock real-time status sync information line audio serial clock output digital supply voltage core (decoder) vertical reference
ITRDY XTRI XPD7 XPD6 VSSId VSSId AMCLK RTS0 ASCLK XPD5 XPD4 XPD3 VDDId 2003
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
SYMBOL VSSEd VDDEd VDDXd VDDEd RTS1 VDDId SDAd RTCO
TYPE(1) (I/)O
DESCRIPTION digital ground peripheral cells (decoder) digital supply voltage peripheral cells (decoder) supply voltage oscillator (decoder) digital supply voltage peripheral cells (decoder) real-time status sync information line digital supply voltage core (decoder) I2C-bus serial data input/output (decoder) real-time control output; contains information about actual system clock frequency, field rate, odd/even sequence, decoder status, subcarrier frequency phase sequence (see external document "RTC Functional Description", available request); RTCO enabled I2C-bus RTCE; notes Table line-locked clock output (13.5 nominal) clock data qualifier test mode select input (decoder); note test clock input (decoder); note analog ground (decoder) analog supply voltage (decoder) analog supply voltage (decoder) analog test output connect) I2C-bus serial clock input (decoder) reset output signal; active (decoder) digital ground peripheral cells (decoder) line-locked clock output nominal) horizontal reference data input ready test reset input (decoder); active LOW; with internal pull-up; notes test data output (decoder); note test data input (decoder); note analog ground (decoder) analog ground (decoder) analog ground (decoder) analog ground (decoder) connected substrate analog supply voltage (decoder) analog ground (decoder) analog ground (decoder) chip enable reset input (with internal pull-up)
LLC2 XPD2 XPD1 XCLK TMSd TCKd VSSAd VDDAd VDDAd AOUT SCLd RESd VSSEd XPD0 XRDY TRSTd TDOd TDId VSSAd VSSAd VSSAd AGND VDDAd VSSAd VSSAd 2003
I/pu I/pu I/pu I/pu
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
SYMBOL XTALId XTALOd XTOUTd VSSXd AI24 AI23 AI2D AI22 AI21 AI12 AI1D AI11 Notes
TYPE(1)
DESCRIPTION crystal input (decoder) crystal output (decoder) crystal oscillator output signal (decoder); auxiliary signal ground crystal oscillator (decoder) analog input analog input differential analog input channel connect ground capacitor analog input analog input analog input differential analog input channel connect ground capacitor analog input
type: input, output, supply, pull-up. board design without boundary scan implementation connect TRSTe TRSTd ground. This provides easy initialization Boundary Scan Test (BST) circuit. TRSTe TRSTd used force Test Access Port (TAP) controller TEST_LOGIC_RESET state (normal operation) once. accordance with "IEEE1149.1" standard pads TDIe (TDId), TMSe (TMSd), TCKe (TCKd) TRSTe (TRSTd) input pads with internal pull-up resistor TDOe (TDOd) 3-state output pad. strapping done connecting supply resistor. During power-up reset sequence corresponding pins switched input mode read strapping level. default setting strapping resistor necessary (internal pull-down). ALRCLK: 24.576 crystal (default); 32.110 crystal. RTCO: operates I2C-bus slave address pin; RTCO slave address 42H/43H (default); RTCO slave address 40H/41H.
handbook, halfpage
MBL788
SAA7108AE SAA7109AE
Fig.4 configuration.
2003
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HD-CODEC
PD10
TTX_ SRES TMSe HSVGC TEST3 XPD6 XPD3 XCLK XRDY
TRSTe TTXRQ_ XCLKO2 VDDIEe VSSEe VDD(DVO) PIXCLKO VSSEd VDDId VSSId VDDId TRSTd
XTALIe TDIe VSSIe
XTALOe VDDAe
DUMP DUMP
VSSXe VSSAe
HPD3 HPD4 HPD5
HPD7 IPD0 IPD1
RSET VDDAe HPD0 VDDAe TEST1 HPD1
IPD4 IPD5
BLUE_ GREEN_ RED_CR_C_ VDDAe TEST2 HPD2 CB_CVBS VBS_CVBS CVBS VDDXe HSM_CSYNC VDDAe VDDEd VDDId VSSId VDDId VDDEd VSSEd
TDOe TCKe
RESe SCLe
VSSIe
HPD6 n.c. IGPH ICLK
IPD2 IPD3 IGPV IGP1 TEST0
IPD6 IPD7 IGP0 ITRI
VSVGC PIXCLKI FSVGC TEST4 XTRI XPD5 XPD2 XPD0 SDAe TEST5 XPD7 XPD4 XPD1
VDDId AMXCLK ALRCLK ITRDY VSSId TMSd TDOd VSSXd VSSEd TCKd TDId AI24 VDDEd VSSAd VSSAd AI23 VDDXd VDDAd VSSAd AI2D VDDEd RTS1 VDDId AMCLK SDAd RESd VSSAd AI1D RTS0 RTCO VSSEd VSSAd AI11 ASCLK LLC2
SAA7108AE; SAA7109AE
VDDAd AOUT SCLd VSSAd AGND VDDAd AI22 AI21 AI12
Product specification
XTALId XTALOd XTOUTd
Philips Semiconductors
Product specification
HD-CODEC
FUNCTIONAL DESCRIPTION DIGITAL VIDEO ENCODER PART
SAA7108AE; SAA7109AE
ease analog post filtering signals twice oversampled before digital-to-analog conversion. total filter transfer characteristics (scaler anti-flicker filter taken into account) illustrated Figs three DACs realized with full 10-bit resolution. CR-Y-CB dematrix bypassed (optionally) order provide upsampled CR-Y-CB input signals. 8-bit multiplexed CB-Y-CR formats "ITU-R BT.656" format) compatible, codes decoded optionally, when device operated slave mode. assignment input data rising falling clock edge Tables order display interlaced signals through euro-connector set, separate digital composite sync signal (pin HSM_CSYNC) generated; advanced periods crystal clock order adapted processing set. SAA7108AE; SAA7109AE synthesizes necessary internal signals, colour subcarrier frequency synchronization signals from that clock. also possible connect RTCO decoder section RTCI encoder section. Thus, information containing actual subcarrier frequency, PAL-ID etc. available case line-locked clock decoder section used re-encoding encoder section. Wide screen signalling data loaded I2C-bus inserted into line standards using field rate. data program dependent automatic start stop such featured VCRs loadable I2C-bus. also contains Closed Caption extended data services encoding (line 21), supports teletext insertion appropriate stream format clock rate (see Fig.51). also possible load data copy generation management system into line every field (525/60 line counting). number possibilities provided setting different video parameters such Black blanking level control Colour subcarrier frequency Variable burst amplitude etc.
digital video encoder encodes digital luminance colour difference signals (CB-Y-CR) digital signals into analog CVBS, S-video and, optionally, CR-Y-CB signals. NTSC sub-standards supported. SAA7108AE; SAA7109AE directly connected video graphics controller with maximum resolution 1280 1024 (progressive) 1920 1080 (interlaced) frame rate. programmable scaler scales computer graphics picture that will into standard screen with adjustable underscan area. Non-interlaced-to-interlaced conversion optimized with adjustable anti-flicker filter flicker-free display very high sharpness. Besides most common 16-bit CB-Y-CR input format (using pins with double edge clocking), other CB-Y-CR formats also supported; Tables complete bytes Look-Up Table (LUT), which used, example, separate gamma corrector, located domain; loaded either through video input port (Pixel Data) I2C-bus. SAA7108AE; SAA7109AE supports 2-bit hardware cursor, pattern which also loaded through video input port I2C-bus. also possible encode interlaced video signals such PC-DVD; that anti-flicker filter, most cases scaler, will simply bypassed. Besides applications video output, SAA7108AE; SAA7109AE also used generating kind auxiliary output, when non-interlaced input signal DACs. This interest example, when graphics controller provides second graphics window video output port. basic encoder function consists subcarrier generation, colour modulation insertion synchronization signals crystal-stable clock rate 13.5 (independent actual pixel clock used input side), corresponding internal bandwidth luminance/colour difference domain. Luminance chrominance signals filtered accordance with standard requirements "RS-170-A" "ITU-R BT.470-3".
2003
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
handbook, full pagewidth
MBE737
(dB)
SCBW SCBW (MHz)
Fig.5 Chrominance transfer characteristic
handbook, halfpage
MBE735
(dB)
(MHz)
SCBW SCBW
Fig.6 Chrominance transfer characteristic
2003
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
handbook, full pagewidth (dB) (MHz)
MGD672
CCRS1 CCRS0 CCRS1 CCRS0 CCRS1 CCRS0 CCRS1 CCRS0
Fig.7 Luminance transfer characteristic (excluding scaler).
handbook, halfpage
MBE736
(dB)
(MHz)
CCRS1 CCRS0
Fig.8 Luminance transfer characteristic (excluding scaler).
2003
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
handbook, full pagewidth
MGB708
(dB)
(MHz)
Fig.9 Luminance transfer characteristic (excluding scaler).
handbook, full pagewidth
MGB706
(dB)
(MHz)
Fig.10 Colour difference transfer characteristic (excluding scaler).
2003
Philips Semiconductors
Product specification
HD-CODEC
Reset conditions
SAA7108AE; SAA7109AE
Y-CB-CR being applied Mbyte/s data stream, output input formatter used directly feed video encoder block. horizontal upscaling supported input formatter. According programming pixel clock dividers (see Section 8.10), will upsample data stream input data rate. optional interpolation filter available. clock domain transition handled entries wide FIFO which gets initialized every field explicitly request. bypass FIFO available, especially high input data rates.
activate reset pulse least crystal clocks duration required. During reset (RESET LOW) plus extra crystal clock periods, FSVGC, VSVGC, CBO, HSVGC TTX_SRES input mode HSM_CSYNC 3-state. reset also forces I2C-bus interface abort running transfer sets into receive condition. After reset, state I/Os other functions defined strapping pins until I2C-bus access redefines corresponding registers; Table Table Strapping pins FSVGC (pin TIED PRESET NTSC encoding, PIXCLK fits graphics input
three 256-byte RAMs this block addressed three 8-bit wide signals, thus used build transformation, e.g. gamma correction signals. event that indexed colour data applied, RAMs addressed parallel. LUTs either loaded I2C-bus write access part pixel data input through port. latter case, bytes expected beginning input video line, lines before line that been defined first active line, until middle line immediately preceding first active line. first bytes represent first data, Cursor insertion
HIGH encoding, PIXCLK fits graphics input VSVGC (pin Y-CB-CR graphics input (format
HIGH graphics input (format (pin input demultiplex phase:
HIGH input demultiplex phase: HIGH HSVGC (pin input demultiplex phase:
HIGH input demultiplex phase: HIGH TTXRQ_XCLKO2 (pin slave (FSVGC, VSVGC HSVGC inputs, internal colour active)
dots cursor overlaid option; cursor uploaded I2C-bus write access specific registers pixel data input through port. latter case, bytes defining cursor bits pixel) expected immediately following last data line preceding first active line. cursor follows: each pixel occupies bits. meaning these bits depends CMODE I2C-bus register described Table Transparent means that input pixels passed through, `cursor colours' programmed separate registers. stored with pixels byte, aligned least significant bit. first pixel bits next pixel bits first index column, followed row; index upper left corner.
HIGH master (FSVGC, VSVGC HSVGC outputs) Input formatter
input formatter converts accepted input data formats, either Y-CB-CR, common internal Y-CB-CR data stream. When double-edge clocking used, data internally split into portions PPD1 PPD2. clock edge assignment must according I2C-bus control bits SLOT EDGE correct operation. 2003
Philips Semiconductors
Product specification
HD-CODEC
Table Layout byte cursor Table
SAA7108AE; SAA7109AE
Cursor modes CURSOR MODE CMODE first cursor colour transparent inverted input CMODE first cursor colour transparent auxiliary cursor colour
pixel
pixel
pixel
pixel
CURSOR PATTERN
second cursor colour second cursor colour
each direction, there registers controlling position cursor, controls position `hot spot', other register controls insertion position. spot `tip' pointer arrow. have position map. actual position registers describe co-ordinates spot. Again upper left corner. While possible move spot beyond left respectively upper screen border this perfectly legal right respectively lower border. should noted that cursor position described relative input resolution. Table BYTE Cursor
Y-CB-CR matrix
input signals encoded NTSC converted Y-CB-CR colour space this block. colour difference signals through low-pass filters formatted ITU-R BT.601 like data stream further processing. gain adjust option corrects level swing graphics world (black-to-white 255) required range 235. matrix formatting blocks bypassed Y-CB-CR graphics input. When auxiliary mode selected, output cursor insertion block immediately directed triple DAC. Horizontal scaler
column column
column column
column column
column column column
column column column
column column column column column column column column column column column column column column column column
high quality horizontal scaler operates data stream. control engines compensate colour phase offset automatically. scaler starts processing after programmable horizontal offset continues with number input pixels. Each input pixel programmable fraction current output pixel (XINC/4096). special case XINC this sets scaling factor SAA7108AE; SAA7109AE input data accordance with "ITU-R BT.656", scaler enters another mode. this event, XINC needs 2048 scaling factor With higher values, upscaling will occur. phase resolution circuit bits, giving maximum offset after input pixels. Small FIFOs rearrange data stream scaler output.
2003
Philips Semiconductors
Product specification
HD-CODEC
Vertical scaler anti-flicker filter 8.10
SAA7108AE; SAA7109AE
Oscillator Discrete Time Oscillator (DTO)
functions scaling Anti-Flicker Filter (AFF) re-interlacing implemented vertical scaler. Besides entire input frame, receives first last lines border allow anti-flicker filtering. circuit generates interlaced output fields scaling down input frames with different offsets even fields. Increasing YSKIP setting reduces anti-flicker function. YSKIP value 4095 switches off; Table 120. additional, programmable vertical filter supports anti-flicker function. This filter available upscaling factors more than programming similar horizontal scaler. re-interlacing, resolutions offset registers sufficient, weighting factors first lines also adjusted. YINC sets scaling factor YIWGTO YIWGTE must re-interlacing, circuit perform upscaling maximum factor maximum factor depends setting anti-flicker function derived from formulae given Section 8.20. additional upscaling mode enables upscaling factor increased maximum required modes like 240. FIFO
master clock generation realized crystal oscillator, which operate with either fundamental wave crystal 3rd-harmonic crystal. crystal clock supplies pixel clock synthesizer, video encoder I2C-bus control block. also usually supplies triple DAC, with exception auxiliary mode, where triple clocked pixel clock (PIXCLK). programmed synthesize relevant pixel clock frequencies between circa MHz. programmable dividers provide actual clock used externally internally. dividers programmed factors internal pixel clock, divider ratio makes sense thus forbidden. internal clock switched completely pixel clock input. this event, input FIFO useless will bypassed. entire pixel clock generation locked vertical frequency. Both pixel clock dividers re-initialized every field. Optionally, cleared with each V-sync. proper programming, this will make pixel clock frequency precise multiple vertical horizontal frequencies. This required some graphic controllers. 8.11 Low-pass Clock Generation Circuit (CGC)
FIFO acts buffer translate from PIXCLK clock domain XTAL clock domain. write clock PIXCLK read clock XTAL. underflow overflow condition detected I2C-bus read access. order avoid underflows overflows, essential that frequency synthesized PIXCLK matches input graphics resolution desired scaling factor. Border generator
This block reduces phase jitter synthesized pixel clock. works tracking filter relevant synthesized pixel clock frequencies. 8.12 8.12.1 Encoder VIDEO PATH
encoder generates luminance colour subcarrier output signals from baseband signals, which suitable CVBS separate signals. Input encoder, clock (e.g. DVD), either originated from computer graphics pixel clock, through FIFO border generator, ITU-R BT.656 style signal. Luminance modified gain offset (the offset programmable certain range enable different black level set-ups). blanking level after insertion fixed synchronization pulse level, accordance with standard composite synchronization schemes.
When graphics picture displayed interlaced PAL, NTSC, S-video screen, desired many cases lose picture information inherent overscanning set. desired amount underscan area, which achieved through appropriate scaling vertical horizontal direction, filled border generator with arbitrary true colour tint.
2003
Philips Semiconductors
Product specification
HD-CODEC
Other manipulations used Macrovision anti-taping process, such additional insertion super-white pulses (programmable height), supported SAA7108AE only. enable easy analog post filtering, luminance interpolated from 13.5 data rate data rate, thereby providing luminance 10-bit resolution. transfer characteristics luminance interpolation filter illustrated Figs Appropriate transients start/end active video synchronization pulses ensured. Chrominance modified gain (programmable separately CR), standard dependent burst inserted, before baseband colour signals interpolated from 6.75 data rate data rate. interpolation stages bypassed, thus providing higher colour bandwidth, which used output. transfer characteristics chrominance interpolation filter illustrated Figs amplitude (beginning ending) inserted burst, programmable certain range that suitable standard signals special effects. After succeeding quadrature modulator, colour provided subcarrier 10-bit resolution. numeric ratio between outputs accordance with standards. 8.12.2 TELETEXT INSERTION ENCODING (NOT SIMULTANEOUSLY WITH REAL-TIME CONTROL) 8.12.3
SAA7108AE; SAA7109AE
VIDEO PROGRAMMING SYSTEM (VPS) ENCODING
Five bytes information loaded I2C-bus will encoded appropriate format into line 8.12.4 CLOSED CAPTION ENCODER
Using this circuit, data accordance with specification Closed Caption extended data service, delivered control interface, encoded (line 21). dedicated pairs bytes (two bytes field), each pair preceded run-in clocks framing code, possible. actual line number which data encoded, modified certain range. data clock frequency accordance with definition NTSC standard times horizontal line frequency. Data output DACs corresponds IRE, data HIGH output DACs corresponds approximately IRE. also possible encode Closed Caption data field frequencies times horizontal line frequency. 8.12.5 ANTI-TAPING (SAA7108AE ONLY)
more information contact your nearest Philips Semiconductors sales office. 8.13 processor
TTX_SRES receives NABTS teletext bitstream sampled crystal clock. each rising edge output signal (TTXRQ) single teletext provided after programmable delay input TTX_SRES. Phase variant interpolation achieved this bitstream internal teletext encoder, providing sufficient small phase jitter output text lines. TTXRQ_XCLKO2 provides fully programmable request signal teletext source, indicating insertion period bitstream lines which selected independently both fields. internal insertion window text (PAL WST), (NTSC WST) (NABTS) teletext bits including clock run-in bits. protocol timing illustrated Fig.51. Alternatively, this provided with buffered crystal clock (XCLK) 13.5 MHz.
This block contains dematrix order produce RED, GREEN BLUE signals SCART plug. Before signals de-matrixed, individual gain adjustment colour difference signals times oversampling luminance times oversampling colour difference signals performed. transfer curves luminance colour difference components illustrated Figs 8.14 Triple
Both signals converted from digital-to-analog 10-bit resolution output video encoder. signals also combined into 10-bit CVBS signal. CVBS output signal occurs with same processing delay optional CR-Y-CB outputs. Absolute amplitude input CVBS reduced 15/16 with respect DACs make maximum conversion ranges.
2003
Philips Semiconductors
Product specification
HD-CODEC
RED, GREEN BLUE signals also converted from digital-to-analog, each providing 10-bit resolution. reference currents three DACs adjusted individually order adapt different output signals. addition, reference currents adjusted commonly compensate small tolerances on-chip band reference voltage. Alternatively, currents switched reduce power dissipation. three outputs used sense external load (usually during pre-defined output. flag I2C-bus status byte reflects whether load applied not. automatic sense mode also activated, which will immediately indicate load three outputs dedicated interrupt TVD. SAA7108AE; SAA7109AE required drive second (auxiliary) monitor HDTV set, DACs receive signal coming from data path. this event, DACs clocked incoming PIXCLKI instead crystal clock used video encoder. 8.15 data path
SAA7108AE; SAA7109AE
Alternatively, device triggered auxiliary codes ITU-R BT.656 data stream PD0. Only vertical frequencies allowed with SAA7108AE; SAA7109AE. slave mode, possible lock encoders colour carrier line frequency with PHRES bits. (more common) master mode, time base circuit continuously free-running. output frame sync FSVGC, vertical sync VSVGC, horizontal sync HSVGC composite blanking signal CBO. these signals defined PIXCLK domain. duration HSVGC VSVGC fixed, they clocks HSVGC line VSVGC. leading slopes phase polarities programmed. input line length programmed. field length always derived from field length encoder pixel clock frequency that being used. acts data request signal. circuit accepts input data programmable number clocks after goes active. This signal programmable possible adjust following (see Figs 50): horizontal offset length active part line distance from active start first expected data vertical offset separately even fields number lines input field. most cases, vertical offsets even fields equal. they not, then even field will start later. SAA7108AE; SAA7109AE will also request first input lines even field, total number requested lines will increase difference offsets. stated above, circuit programmed accept look-up cursor data first lines each field. timing generator provides normal data request pulses these lines; duration same regular lines. additional request pulses will suppressed with LUTL logic Table 143. other vertical timings change this case, first active line number counted from
This data path enables SAA7108AE; SAA7109AE used with HDTV monitors. receives data directly from cursor generator supports Y-PB-PR output formats (RGB with Y-PB-PR input formats). scaling done this mode. gain adjustment either leads full level swing digital-to-analog converters reduces amplitude factor 0.69. This enables sync pulses added signal required display units that require signals with sync pulses, either regular 3-level syncs. 8.16 Timing generator
synchronization SAA7108AE; SAA7109AE able operate modes; slave mode master mode. slave mode, circuit accepts sync pulses bidirectional FSVGC (frame sync), VSVGC (vertical sync) HSVGC (horizontal sync) pins: polarities signals programmed. frame sync signal only necessary when input signal interlaced, other cases omitted. frame sync signal present, possible derive vertical horizontal phase from setting bits. HSVGC VSVGC necessary this case, possible switch pins output mode.
2003
Philips Semiconductors
Product specification
HD-CODEC
8.17 Pattern generator sync pulses
SAA7108AE; SAA7109AE
Each index this table points particular line next table linked list. This table called line pattern array each seven entries stores four pairs duration pixel clock cycles index value table. table entries used define portions line representing certain value certain number clock cycles. value specified this table actually another 3-bit index into value array which hold eight 8-bit values. (MSB) index logic value inserted into signal only; associated value inserted into three signals. additional bits entries value array (LSBs second byte) determine associated events appear digital pulse HSM_CSYNC and/or outputs. ease trigger set-up sync generation module, registers provided screen raster defined width height. trigger position specified co-ordinate within overall dimensions screen raster. counter matches specified co-ordinates, trigger pulse generated which pre-loads tables with their initial values. Table outlines example sync tables 1080i raster. Important note: problem programming interface, writing line pattern array (address might destroy data line type array (address D1). work around write line pattern array data before writing line type array. Reading arrays possible address pointers must initialized before next write operation.
pattern generator provides appropriate synchronization pattern video data path auxiliary monitor HDTV mode, respectively. provides maximum flexibility terms raster generation interlaced non-interlaced computer graphics ATSC formats. sync engine capable providing combination event-value pairs which used insert certain values specified times outgoing data stream. also used generate digital signals associated with time events. They used digital horizontal vertical synchronization signals pins HSM_CSYNC VSM. picture position adjustable through programmable relationship between sync pulses video contents. generation embedded analog sync pulses bound number events which defined line. Several these line timing definitions exist parallel. final sync raster composition certain sequence lines with different sync event properties defined. sequence specifies series line types number occurrences this specific line type. After sequence been completed, restarts from beginning. pulse shapes filtered internally order avoid ringing after analog post filters. sequence generated pulse stream must precisely incoming data stream terms total number pixels line lines frame. sync engines flexibility achieved using sequence linked lists carrying properties image, lines well fractions lines. Figure illustrates context between various tables. first table serves array hold correct sequence lines composing synchronization raster. contain entries. Each entry holds 4-bit index next table 10-bit counter value which specifies often this particular line invoked. necessary line count particular line exceeds bits, table entries. 4-bit index line count array points line type array. holds entries where, index used, index points first entry, index second entry line type array etc. Each entry line type array hold index pointers another table. These indices point portions line pulse pattern: line could split e.g. into sync, blank, active portion followed another blank portion, occupying four entries table line. 2003
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
handbook, full pagewidth
4-bit line type index
10-bit line count LINE COUNT ARRAY entries line count pointer
line type pointer
pattern pointer
LINE TYPE ARRAY entries
event type pointer
10-bit duration
10-bit duration
10-bit duration
10-bit duration
4-bit value index 4-bit value index 4-bit value index 4-bit value index 2-bit value VALUE ARRAY entries line pattern pointer
MBL797
LINE PATTERN ARRAY entries
Fig.11 Context between pattern generator tables sync pulses.
2003
Philips Semiconductors
Product specification
HD-CODEC
Table Example set-up sync tables
SAA7108AE; SAA7109AE
SEQUENCE Write subaddress
COMMENT
points first entry line count array (index generate lines line type index (remember, second entry line type array); will first vertical raster pulse generate line line type index will sync-black-sync-black sequence after first vertical pulse generate lines line type index will following lines with sync-black sequence generate lines line type index will lines with sync active video generate lines line type index will following lines with sync-black sequence generate line line type index will following line (line 563) with sync-black-sync-black-null sequence (null equivalent sync tip) generate lines line type index will second vertical raster pulse generate line line type index will following line with sync-null-sync-black sequence generate lines line type index will following lines with sync-black sequence generate lines line type index will lines with sync active video generate lines line type index will following lines with sync-black sequence; now, 1125 lines defined
Write subaddress (insertion done into three analog output signals) Write subaddress points first entry line type array (index pattern entries this sequence (for sync active video) pattern entries this sequence (for sync-black-null-black) pattern entries this sequence (for sync-black-null-black-null) pattern entries this sequence (for sync-black-sync-black) pattern entries this sequence (for sync-black-sync-black-null) pattern entries this sequence (for sync-black) points first entry line pattern array (index value(3) value(3); (subtract from real duration) value(4) value(3) value(1) value(2) value(3)
value(3) value(0) value(0) value(3) value(3) value(3) value(3) value(3)
2003
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
SEQUENCE
COMMENT
Write subaddress signals directed pins HSM_CSYNC VSM) Write subaddress 8.18 I2C-bus interface insertion active, gain signal adapted accordingly most cases, DOWNA DOWND should logic simultaneously. EIDIV logic should logic before power-down. 8.20 Programming graphics acquisition scaler video encoder points first entry value array (index black level, added during active video sync level (minimum output voltage) sync level HIGH (3-level sync) black level (needed elsewhere) null (identical with sync level LOW)
I2C-bus interface standard slave transceiver, supporting 7-bit slave addresses kbits/s guaranteed transfer rate. uses 8-bit subaddressing with auto-increment function. registers read write, except read only status bytes. register consists Look-Up Table (LUT), cursor control registers. contains three banks bytes, where each triplet assigned address. Thus write access needs address three data bytes following subaddress FFH. further write access auto-incrementing address performed. cursor access similar access contains only single byte address. I2C-bus slave address defined 88H. 8.19 Power-down modes
encoder section needs provide continuous data stream analog outputs well receive continuous stream from data source. fact that there frame memory isolating data streams, restrictions apply input frame timings. Input output processing encoder section only coupled through vertical frequencies. master mode, encoder provides vertical sync odd/even pulse input processing, slave mode, encoder receives them. parameters input field mainly given memory capacity encoder section. rule that scaler thus input processing needs provide video data same time frames encoder reads them. vertical active video times (and vertical frequencies) need same. second rule that there data buffer FIFO when encoder enters active video area. vertical offset input path needs shorter than offset encoder. following gives equations required program most common application: post processor master mode with non-interlaced video input data.
order reduce power consumption, SAA7108AE; SAA7109AE supports power-down modes, accessible I2C-bus. analog power-down mode (DOWNA turns digital-to-analog converters pixel clock synthesizer. digital down mode turns internal clocks sets digital outputs except I2C-bus interface. retains programming still accessed this mode, registers read from written Reading writing look-up tables, cursor sync generator require valid pixel clock. typical supply current full power-down approximately fact that analog power-down mode turns pixel clock synthesizer, there limitations some applications. there pixel clock, able outputs LOW. 2003
Philips Semiconductors
Product specification
HD-CODEC
Some variables defined below: InPix: number active pixels input line InPpl: length entire input line pixel clocks InLin: number active lines input field/frame TPclk: pixel clock period RiePclk: ratio internal external pixel clock OutPix: number active pixels output line OutLin: number active lines output field TXclk: encoder clock period (37.037 ns). 8.20.1 DISPLAY WINDOW
SAA7108AE; SAA7109AE
262.5 1716 TXclk Thus: TPclk InLin 262.5 InPpl integer OutLin 312.5 1728 TXclk TPclk InLin InPpl integer 312.5 OutLin pixel clock generator TXclk PCLE (all frequencies); TPclk Tables 102, 105. divider PCLE should according Table 104. PCLI lower same value. Setting lower value means that internal pixel clock higher data sampled difference pixels resolution resolutions with pixels line rule thumb. This allows horizontal upscaling maximum factor respectively (this parameter RiePclk). RiePclk PCLI PCLE (all frequencies) equations ensure that last line field full number clock cycles. Many graphic controllers require this. Note that PCLSY needs ensure that there even fraction clock left field. 8.20.3 HORIZONTAL SCALER
first visible pixel index 256, pixels encoded; index 284, pixels visible. output lines should centred screen. should noted that encoder clocks pixel; Table ADWHS OutPix Hz); ADWHS OutPix Hz); ADWHE ADWHS OutPix (all frequencies) vertical, procedure same. first line with video information number lines active. numbers 287; Table OutLin Hz); OutLin Hz); OutLin (all frequencies) Most sets overscan, pixels respectively lines visible. There standard factor, highly recommended make number output pixels lines adjustable. reasonable underscan factor 10%, giving approximately output pixels line. 8.20.2 INPUT FRAME PIXEL CLOCK
XOFS chosen arbitrarily, condition being that XOFS XPIX HLEN fulfilled. Values given VESA display timings preferred. HLEN InPpl RiePclk InPix XPIX RiePclk OutPix 4096 XINC -InPix RiePclk XINC needs rounded needs scaling factor 8.20.4 VERTICAL SCALER
total number pixel clocks line input horizontal offset need chosen next. only constraint that horizontal blanking least clock pulses. required pixel clock frequency determined following way: limited internal FIFO size, input path provide pixels same time frame encoders vertical active time. scaler also process first last border lines anti-flicker function. 2003
input vertical offset taken from assumption that scaler should have just finished writing first line when encoder starts reading 1716 TXclk YOFS InPpl TPclk 1728 TXclk YOFS InPpl TPclk
Philips Semiconductors
Product specification
HD-CODEC
most cases vertical offsets will same even fields. results should rounded down. YPIX InLin YSKIP defines anti-flicker function. means maximum flicker reduction minimum vertical bandwidth, 4095 gives flicker reduction maximum bandwidth. Note that maximum value YINC 4095. might necessary reduce value YSKIP fulfil this requirement. OutLin YSKIP YINC 4096 InLin 4095 YINC YIWGTO 2048 YINC YSKIP YIWGTE When YINC sets scaler scaling factor initial weighting factors must this case. YIWGTE negative. this event, YINC should added YOFSE incremented. This repeated often necessary make YIWGTE positive. Note that these equations assume that input non-interlaced while output interlaced. input interlaced, initial weighting factors need adapted proper phase offsets output frame. vertical upscaling beyond upper capabilities required, parameter YUPSC This extends maximum vertical scaling factor factor Only parameter YINC gets affected, needs divided same effect. There restrictions this mode: vertical filter YFILT available this mode; circuit will ignore this value horizontal blanking needs long enough transfer output line between memory locations. This internal pixel clocks upscaling factor needs limited horizontal upscaling factor also limited less than 1.5. this case normal blanking length sufficient. 8.21 Input levels formats
SAA7108AE; SAA7109AE
CVBS outputs, deviating amplitudes colour difference signals compensated independent gain control setting, while gain luminance predefined values, distinguishable set-up without set-up. RGB, respectively CR-Y-CB path features individual gain setting luminance (GY) colour difference signals (GCD). Reference levels measured with colour bar, 100% white, 100% amplitude 100% saturation. encoder section SAA7108AE; SAA7109AE special input cells port. They operate wider supply voltage range have strict input threshold 1/2VDD(DVO). achieve full speed these cells, EIDIV needs logic this case impedance these cells approximately This cause trouble with bootstrapping pins some graphic chips. power-on reset forces logic input impedance regular this mode. Table
"ITU-R BT.601" signal component levels
SIGNALS(1)
COLOUR White Yellow Cyan Green Magenta Blue Black Note Transformation: 1.3707 128) 0.3365 128) 0.6982 128) 1.7324 128).
SAA7108AE; SAA7109AE accepts digital data with levels (digital codes) accordance with "ITU-R BT.601". optional gain adjustment also allows data accepted with full level swing 255.
2003
Philips Semiconductors
Product specification
HD-CODEC
Table Usage bits SLOT EDGE DATA SLOT CONTROL (EXAMPLE FORMAT SLOT EDGE DATA rising edge G3/Y3 falling edge G3/Y3 rising edge R7/CR7 falling edge R7/CR7 DATA falling edge R7/CR7 rising edge R7/CR7 falling edge G3/Y3 rising edge G3/Y3 Table assignment input format 8-BIT NON-INTERLACED RGB/CB-Y-CR PD11 PD10 FALLING CLOCK EDGE G3/Y3 G2/Y2 G1/Y1 G0/Y0 B7/CB7 B6/CB6 B5/CB5 B4/CB4 B3/CB3 B2/CB2 B1/CB1 B0/CB0 RISING CLOCK EDGE R7/CR7 R6/CR6 R5/CR5 R4/CR4 R3/CR3 R2/CR2 R1/CR1 R0/CR0 G7/Y7 G6/Y6 G5/Y5 G4/Y4
SAA7108AE; SAA7109AE
Table assignment input format 5-BIT NON-INTERLACED FALLING CLOCK EDGE RISING CLOCK EDGE
Table assignment input format 5-BIT NON-INTERLACED FALLING CLOCK EDGE RISING CLOCK EDGE
Table assignment input format 8-BIT NON-INTERLACED CB-Y-CR FALLING CLOCK EDGE CB7(0) CB6(0) CB5(0) CB4(0) CB3(0) CB2(0) CB1(0) CB0(0) RISING CLOCK EDGE Y7(0) Y6(0) Y5(0) Y4(0) Y3(0) Y2(0) Y1(0) Y0(0) FALLING CLOCK EDGE CR7(0) CR6(0) CR5(0) CR4(0) CR3(0) CR2(0) CR1(0) CR0(0) RISING CLOCK EDGE Y7(1) Y6(1) Y5(1) Y4(1) Y3(1) Y2(1) Y1(1) Y0(1)
2003
Philips Semiconductors
Product specification
HD-CODEC
Table assignment input format 8-BIT INTERLACED CB-Y-CR (ITU-R BT.656, CLOCK) RISING CLOCK EDGE CB7(0) CB6(0) CB5(0) CB4(0) CB3(0) CB2(0) CB1(0) CB0(0) RISING CLOCK EDGE Y7(0) Y6(0) Y5(0) Y4(0) Y3(0) Y2(0) Y1(0) Y0(0) RISING CLOCK EDGE CR7(0) CR6(0) CR5(0) CR4(0) CR3(0) CR2(0) CR1(0) CR0(0) RISING CLOCK EDGE Y7(1) Y6(1) Y5(1) Y4(1) Y3(1) Y2(1) Y1(1) Y0(1)
SAA7108AE; SAA7109AE
Table assignment input format 8-BIT NON-INTERLACED RGB/CB-Y-CR PD11 PD10 FALLING CLOCK EDGE G4/Y4 G3/Y3 G2/Y2 B7/CB7 B6/CB6 B5/CB5 B4/CB4 B3/CB3 G0/Y0 B2/CB2 B1/CB1 B0/CB0 RISING CLOCK EDGE R7/CR7 R6/CR6 R5/CR5 R4/CR4 R3/CR3 G7/Y7 G6/Y6 G5/Y5 R2/CR2 R1/CR1 R0/CR0 G1/Y1
Table assignment input format note 8-BIT NON-INTERLACED INDEX COLOUR PD11 PD10 Note don't care. FALLING CLOCK EDGE INDEX7 INDEX6 INDEX5 INDEX4 INDEX3 INDEX2 INDEX1 INDEX0 RISING CLOCK EDGE
2003
Philips Semiconductors
Product specification
HD-CODEC
9.1.1 FUNCTIONAL DESCRIPTION DIGITAL VIDEO DECODER PART Decoder ANALOG INPUT PROCESSING 9.1.2
SAA7108AE; SAA7109AE
ANALOG CONTROL CIRCUITS
anti-alias filters adapted line-locked clock frequency filter control circuit. characteristics illustrated Fig.12. During vertical blanking period, gain clamping control frozen.
SAA7108AE; SAA7109AE offers analog signal inputs, analog main channels with source switch, clamp circuit, analog amplifier, anti-alias filter video 9-bit CMOS ADC; Fig.15.
MGD138
(dB)
(MHz)
Fig.12 Anti-alias filter.
2003
Philips Semiconductors
Product specification
HD-CODEC
9.1.2.1 Clamping
SAA7108AE; SAA7109AE
clamping control circuit controls correct clamping analog input signals. coupling capacitor used store filter clamping voltage. internal digital clamp comparator generates information with respect clamp-up clamp-down. clamping levels channels fixed luminance (60) chrominance (128). Clamping time normal with pulse back porch video signal.
analog input level maximum
controlled input level
9.1.2.2
Gain control
range
(p-p) 18/56 minimum
MHB325
gain control circuit receives (via I2C-bus) static gain levels analog amplifiers, controls these amplifiers automatically built-in Automatic Gain Control (AGC) part Analog Input Control (AICO). (automatic gain control luminance) used amplify CVBS signal required signal amplitude, which matched ADCs input voltage range. active time sync bottom video signal. Signal (white) peak control limits gain signal overshoots. influence supply voltage variation within specified range automatically eliminated clamping automatic gain control. flow charts show more details AGC; Figs
Fig.14 Automatic gain range.
line analog line blanking
GAIN
CLAMP
MGL065
Fig.13 Analog line with clamp (HCL) gain range (HSY).
2003
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2003
AI24 AI23 AI2D AI22 AI21 SOURCE SWITCH ANALOG AMPLIFIER DAC9 CLAMP CIRCUIT AI12 AI1D AI11 SOURCE SWITCH CLAMP CIRCUIT ANALOG AMPLIFIER DAC9
Philips Semiconductors
HD-CODEC
TEST SELECTOR BUFFER AOSL [1:0]
AOUT
ANTI-ALIAS FILTER
BYPASS SWITCH
ADC2
FUSE [1:0]
ANTI-ALIAS FILTER
BYPASS SWITCH
ADC1
FUSE [1:0]
MODE CONTROL CLAMP CONTROL GAIN CONTROL ANTI-ALIAS CONTROL VERTICAL BLANKING CONTROL MODE3 MODE2 MODE1 MODE0 GLIMB GLIMT WIPA SLTCA HOLDG GAFIX WPOFF GUDL [1:0] [28:20] [18:10] HLNRS UPTCV VBSL VBLNK SVREF
SAA7108AE; SAA7109AE
ANALOG CONTROL
CROSS MULTIPLEXER CVBS/LUM CVBS/CHR
MHB892
Product specification
AD2BYP AD1BYP
Fig.15 Analog input processing using SAA7108AE; SAA7109AE differential front-end with 9-bit ADC.
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
ANALOG INPUT AMPLIFIER ANTI-ALIAS FILTER LUMA/CHROMA DECODER gain
ACTION
VBLK
HOLDG
+1/F STOP
+1/L
-1/LLC2
+1/LLC2
-1/LLC2
GAIN ACCUMULATOR BITS) ACTUAL GAIN VALUE 9-BIT (AGV) [-3/+6
system variable. (IAGV FGVI) GUDL. VBLK vertical blanking pulse. horizontal sync pulse. actual gain value. frozen gain value.
UPDATE
GAIN VALUE 9-BIT
MHB531
Fig.16 Gain flow chart.
2003
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
ANALOG INPUT
BLANKING ACTIVE
VBLK
CLAMP
GAIN
SBOT
WIPE
CLAMP
CLAMP
CLAMP
GAIN
GAIN
fast GAIN
slow GAIN
MGC647
WIPE white peak level (254). SBOT sync bottom level (1). clamp level (128 C)]. horizontal sync pulse. horizontal clamp pulse.
Fig.17 Clamp gain flow.
2003
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CVBS-IN Y-IN LDEL YCOMB DELAY COMPENSATION QUADRATURE MODULATOR INTERPOLATION LOW-PASS LUFI 3:0] CSTD 2:0] YDEL 2:0] SET_RAW SET_VBI SUBTRACTOR LUMINANCE-PEAKING LOW-PASS, Y-DELAY ADJUSTMENT Y/CVBS DBRI 7:0] DCON 7:0] DSAT 7:0] RAWG 7:0] RAWO 7:0] COLO LUBW CVBS-IN CHR-IN QUADRATURE DEMODULATOR LOW-PASS DOWNSAMPLING ADAPTIVE COMB FILTER LOW-PASS BRIGHTNESS CONTRAST SATURATION CONTROL DATA GAIN OFFSET CONTROL Y-OUT/ CVBS-OUT UV-OUT SUBCARRIER GENERATION LCBW 2:0] SET_RAW CCOMB SET_VBI YCOMB LDEL BYPS CHBW HREF-OUT CHROMINANCE INCREMENT DELAY LDEL YCOMB SECAM PROCESSING
9.1.3 CHROMINANCE LUMINANCE PROCESSING
Philips Semiconductors
HD-CODEC HD-CODEC
Fig.18 Chrominance luminance processing.
handbook, full pagewidth
SUBCARRIER GENERATION HUEC
CHROMINANCE INCREMENT DTO-RESET SUBCARRIER INCREMENT GENERATION DIVIDER PHASE DEMODULATOR AMPLITUDE DETECTOR BURST GATE ACCUMULATOR LOOP FILTER
SET_RAW SET_VBI
CHROMA GAIN CONTROL DELAY LINE UVADJUSTMENT SECAM RECOMBINATION
SAA7108AE; SAA7109AE SAA7108AE; SAA7109AE
CDTO INCS CSTD 2:0] RTCO
FCTC ACGC CGAIN 6:0] IDEL 3:0]
CODE
SECS
SET_RAW SET_VBI
DCVF
MHB532
Product specification
switch signal
Philips Semiconductors
Product specification
HD-CODEC
9.1.3.1 Chrominance path
SAA7108AE; SAA7109AE
Baseband `bell' filters reconstruct amplitude phase equalized signals Phase demodulator differentiator demodulation) De-emphasis filter compensate pre-emphasized input signal, including frequency offset compensation white carrier values subtracted from signal, controlled SECAM switch signal). succeeding chrominance gain control block amplifies attenuates CB-CR signal according required 601/656 levels. controlled output signal from amplitude detection circuit within burst processing block. burst processing block provides feedback loop chrominance contains following: Burst gate accumulator Colour identification killer Comparison nominal/actual burst amplitude (PAL/NTSC standards only) Loop filter chrominance gain control (PAL/NTSC standards only) Loop filter chrominance (only active PAL/NTSC standards) PAL/SECAM sequence detection, H/2-switch generation. increment generation circuit produces Discrete Time Oscillator (DTO) increment both subcarrier generation blocks. contains division increment line-locked clock generator create stable phase-locked sine signal under conditions (e.g. non-standard signals). delay line block eliminates crosstalk between chrominance channels accordance with standard requirements. NTSC colour standards, delay line used additional vertical filter. desired, switched DCVF always disabled during data lines programmable LCRn registers (subaddresses 57H); Section 9.2. embedded line delay also used SECAM recombination (cross-over switches).
9-bit CVBS chrominance input signal input quadrature demodulator, where multiplied time-multiplexed subcarrier signals from subcarrier generation block phase relationship demodulator axis). frequency dependent chosen colour standard. time-multiplexed output signals multipliers low-pass filtered (low-pass Eight characteristics programmable LCBW3 LCBW0 achieve desired bandwidth colour difference signals (PAL, NTSC) signals (SECAM). chrominance low-pass characteristic also influences grade cross-luminance reduction during horizontal colour transients (large chrominance bandwidth means strong suppression cross-luminance). comb filter disabled when YCOMB filter directly influences width chrominance notch within luminance path (large chrominance bandwidth means wide chrominance notch resulting lower luminance bandwidth). low-pass filtered signals adaptive comb filter block. chrominance components separated from luminance two-line vertical stage (four lines standards) decision logic circuit between filtered non-filtered output signals: this block bypassed SECAM signals. comb filter logic enabled independently succeeding luminance chrominance processing YCOMB (subaddress 09H, and/or CCOMB (subaddress 0EH, always bypassed during data lines, programmable LCRn registers (subaddresses 57H); Section 9.2. separated CB-CR components further processed second filter stage (low-pass modify chrominance bandwidth without influencing luminance path. It's characteristic controlled CHBW (subaddress 10H, complete transfer characteristic low-pass filters Figs SECAM processing (bypassed standards) contains following blocks:
2003
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
(dB) LCBW[2:0] 000. LCBW[2:0] 010. LCBW[2:0] 100. LCBW[2:0] 110.
MHB533
(MHz)
(dB) LCBW[2:0] 001. LCBW[2:0] 011. LCBW[2:0] 101. LCBW[2:0] 111. (MHz)
Fig.19 Transfer characteristics chrominance low-pass CHBW
2003
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
(dB) LCBW[2:0] 000. LCBW[2:0] 010. LCBW[2:0] 100. LCBW[2:0] 110.
MHB534
(MHz)
(dB) LCBW[2:0] 001. LCBW[2:0] 011. LCBW[2:0] 101. LCBW[2:0] 111. (MHz)
Fig.20 Transfer characteristics chrominance low-pass CHBW
2003
Philips Semiconductors
Product specification
HD-CODEC
9.1.3.2 Luminance path
SAA7108AE; SAA7109AE
frequency characteristic separated luminance signal further modified succeeding luminance filter block. configured peaking (resolution enhancement) low-pass block LUFI3 LUFI0 (subaddress 09H, bits resulting frequency characteristics seen Fig.25. LUFI3 LUFI0 settings used user programmable sharpness control. luminance filter block also contains adjustable delay part; programmable YDEL2 YDEL0 (subaddress 11H, bits
rejection chrominance components within 9-bit CVBS input signal done subtracting re-modulated chrominance signal from CVBS input. comb filtered CB-CR components interpolated (upsampled) low-pass block. It's characteristic controlled LUBW (subaddress 09H, modify width chrominance `notch' without influencing chrominance path. programmable frequency characteristics available, conjunction with LCBW2 LCBW0 settings, seen Figs should noted that these frequency curves only valid comb disabled filter mode (YCOMB comb filter mode frequency response flat. centre frequency notch automatically adapted chosen colour standard. interpolated CB-CR samples multiplied time-multiplexed subcarrier signals from subcarrier generation block This second locked first subcarrier generator increment delay circuit matched processing delay, which different NTSC standards according chosen comb filter algorithm. modulated signals finally added create re-modulated chrominance signal.
2003
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
(dB) LCBW[2:0] 000. LCBW[2:0] 010. LCBW[2:0] 100. LCBW[2:0] 110.
MHB535
(MHz)
(dB) LCBW[2:0] 001. LCBW[2:0] 011. LCBW[2:0] 101. LCBW[2:0] 111. (MHz)
Fig.21 Transfer characteristics luminance notch filter 3.58 mode (Y-comb filter disabled) LUBW
2003
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
(dB) LCBW[2:0] LCBW[2:0] LCBW[2:0] LCBW[2:0]
MHB536
(MHz)
(dB) LCBW[2:0] LCBW[2:0] LCBW[2:0] LCBW[2:0] (MHz)
Fig.22 Transfer characteristics luminance notch filter 3.58 mode (Y-comb filter disabled) LUBW
2003
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
(dB) LCBW[2:0] 000. LCBW[2:0] 010. LCBW[2:0] 100. LCBW[2:0] 110.
MHB537
(MHz)
(dB) LCBW[2:0] 001. LCBW[2:0] 011. LCBW[2:0] 101. LCBW[2:0] 111. (MHz)
Fig.23 Transfer characteristics luminance notch filter 4.43 mode (Y-comb filter disabled) LUBW
2003
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
(dB) LCBW[2:0] 000. LCBW[2:0] 010. LCBW[2:0] 100. LCBW[2:0] 110.
MHB538
(MHz)
(dB) LCBW[2:0] 001. LCBW[2:0] 011. LCBW[2:0] 101. LCBW[2:0] 111. (MHz)
Fig.24 Transfer characteristics luminance notch filter 4.43 mode (Y-comb filter disabled) LUBW
2003
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
MHB539
(dB)
(dB) LUFI[3:0] 1000. (10) LUFI[3:0] 1001. (11) LUFI[3:0] 1010. (12) LUFI[3:0] 1011. (13) LUFI[3:0] 1100. (14) LUFI[3:0] 1101. (15) LUFI[3:0] 1110. (16) LUFI[3:0] 1111.
LUFI[3:0] 0001. LUFI[3:0] 0010. LUFI[3:0] 0011. LUFI[3:0] 0100. LUFI[3:0] 0101. LUFI[3:0] 0110. LUFI[3:0] 0111. LUFI[3:0] 0000.
(MHz)
(10) (11) (12) (13) (14) (15) (16)
(MHz)
Fig.25 Transfer characteristics luminance peaking/low-pass filter (sharpness).
2003
Philips Semiconductors
Product specification
HD-CODEC
9.1.3.3
SAA7108AE; SAA7109AE
Brightness Contrast Saturation (BCS) control decoder output levels
resulting (CVBS) CB-CR signals block, which contains following functions: Chrominance saturation control DSAT7 DSAT0 Luminance contrast brightness control DCON7 DCON0 DBRI7 DBRI0 data (CVBS) gain offset adjustment RAWG7 RAWG0 RAWO7 RAWO0 Limiting Y-CB-CR CVBS values (minimum) (maximum) fulfil "ITU Recommendation 601/656".
+255 handbook, full pagewidth +235 white
+255 +240 +212
blue 100% blue
+255 +240 +212
100%
+128
LUMINANCE 100%
+128
colourless CB-COMPONENT
+128
colourless CR-COMPONENT
black
yellow yellow 100%
cyan cyan 100%
MHB730
output range.
output range.
output range.
"ITU Recommendation 601/656" digital levels with default (decoder) settings DCON[7:0] 44H, DBRI[7:0] DSAT[7:0] 40H. Equations modification Y-CB-CR levels control I2C-bus bytes DBRI, DCON DSAT.
Luminance: DCON DBRI
DSAT Chrominance: should noted that resulting levels limited accordance with "ITU Recommendation 601/656".
Fig.26 Y-CB-CR range scaler input port output.
2003
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
+255 +209 white
+255 +199 white
LUMINANCE
LUMINANCE
SYNC
black black shoulder
SYNC
black shoulder black
sync bottom
sync bottom
MGD700
Sources containing black level offset (e.g. NTSC
Sources containing black level offset.
CVBS levels with default settings RAWG[7:0] RAWO[7:0] 128. Equation modification data levels bytes RAWG RAWO: RAWG CVBS CVBS RAWO should noted that resulting levels limited accordance with "ITU Recommendation 601/656".
Fig.27 CVBS (raw data) range scaler input, data slicer port output.
2003
Philips Semiconductors
Product specification
HD-CODEC
9.1.4 SYNCHRONIZATION
SAA7108AE; SAA7109AE
internal signal LFCO digital-to-analog converted signal provided horizontal PLL. multiple line frequency: 6.75 Hz), 6.75 Hz). LFCO signal multiplied internally factor circuit (including phase detector, loop filtering, frequency divider) obtain output clock signals. rectangular output clocks have duty cycle. Table Decoder clock frequencies CLOCK XTAL LLC2 LLC4 (internal) LLC8 (virtual) FREQUENCY (MHz) 24.576 32.110 13.5 6.75 3.375
prefiltered luminance signal synchronization stage. bandwidth further reduced low-pass filter. sync pulses sliced phase detectors where they compared with sub-divided clock frequency. resulting output signal applied loop filter accumulate phase deviations. Internal signals (e.g. HSY) generated accordance with analog front-end requirements. loop filter signal drives oscillator generate line frequency control signal (LFCO); Fig.28. detection `pseudo syncs' part Macrovision copy protection standard also done within synchronization circuit. result reported flag COPRO within decoder status byte subaddress 1FH. 9.1.5 CLOCK GENERATION CIRCUIT
internal generates clock signals required video input processor.
LFCO
BAND PASS LLC/4
ZERO CROSS DETECTION
PHASE DETECTION
LOOP FILTER
OSCILLATOR
DIVIDER
DIVIDER
MHB330
LLC2
Fig.28 Block diagram clock generation circuit.
9.1.6
POWER-ON RESET INPUT
missing clock, insufficient digital analog VDDAd supply voltages (below will start reset sequence; outputs forced 3-state (see Fig.29). indicator output RESd approximately after internal reset applied reset other circuits digital system. possible force reset pulling Chip Enable (CE) ground. After rising edge sufficient power supply voltage, outputs LLC, LLC2 SDAd return from 3-state active, while other signals have activated programming.
2003
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
VDDA ANALOG
VDDD DIGITAL
CLOCK LOGIC RESINT CLK0 DELAY
XTALO
LLCINT
RESINT
(internal reset)
some
PLL-delay
digital delay
MHB331
Power-on Control. chip enable input. XTALO crystal oscillator output. LLCINT internal system clock. RESINT internal reset. line-locked clock output. reset output.
Fig.29 Power-on control circuit.
2003
Philips Semiconductors
Product specification
HD-CODEC
Decoder output formatter
SAA7108AE; SAA7109AE
each value, from data type programmed individually. LCR2 LCR23 refer line numbers. selection LCR24 values valid rest corresponding field. upper nibble contains value field (odd), lower nibble field (even). relationship between values line numbers adjusted VOFF8 VOFF0, located subaddresses (bit (bits FOFF subaddress (bit recommended values VOFF[8:0] sources (with FOFF VOFF[8:0] sources (with FOFF accommodate line number conventions used PAL, SECAM NTSC standards; Tables
output interface block decoder part contains formatter expansion port data output XPD7 XPD0 (see Section 10.4.1) control circuit signals needed internal paths scaler data slicer part. also controls selection reference signals port (RTCO, RTS0 RTS1) expansion port (XRH, XDQ). generation decoder data type control signals SET_RAW also done within this block. These signals decoded from requested data type scaler input and/or data slicer, selectable control registers LCR2 LCR24; Section 18.2.4.2. Table Data formats decoder output DATA TYPE NUMBER DATA TYPE teletext EuroWST, CCST European Closed Caption
DECODER OUTPUT DATA FORMAT Y-CB-CR Y-CB-CR
Video Programming Service (VPS) Wide screen signalling bits teletext (WST) Closed Caption (line video component signal, region CVBS data teletext VITC/EBU time codes (Europe) VITC/SMPTE time codes (USA) reserved NABTS MOJI (Japanese) Japanese format switch (L20/22) video component signal, active video region
2003
This text here white force landscape pages rotated correctly when browsing through Acrobat reader.This text here _white force landscape pages rotated correctly when browsing through Acrobat reader.This text here inThis text here white force landscape pages rotated correctly when browsing through Acrobat reader. white force landscape pages Table Relationship line numbers lines/60 systems (part Vertical line offset, VOFF[8:0] (subaddresses 5BH[4] 5AH[7:0]); horizontal pixel offset, HOFF[10:0] 347H (subaddresses 5BH[2:0] 59H[7:0]); FOFF (subaddress 5BH[7]) Line number (1st field) Line number (2nd field) active video active video serration pulses serration pulses equalization pulses equalization pulses equalization pulses equalization pulses 2003 Philips Semiconductors
HD-CODEC
Table Relationship line numbers lines/60 systems (part Vertical line offset, VOFF[8:0] (subaddresses 5BH[4] 5AH[7:0]); horizontal pixel offset, HOFF[10:0] 347H (subaddresses 5BH[2:0] 59H[7:0]); FOFF (subaddress 5BH[7]) Line number (1st field) Line number (2nd field) nominal VBI-lines nominal VBI-lines active video active video
Table Relationship line numbers lines/50 systems (part Vertical line offset, VOFF[8:0] (subaddresses 5BH[4] 5AH[7:0]); horizontal pixel offset, HOFF[10:0] 347H (subaddresses 5BH[2:0] 59H[7:0]); FOFF (subaddress 5BH[7]) Line number (1st field) Line number (2nd field) active video active video serration pulses serration pulses equalization pulses equalization pulses equalization pulses
SAA7108AE; SAA7109AE
equalization pulses
Table Relationship line numbers lines/50 systems (part Vertical line offset, VOFF[8:0] (subaddresses 5BH[4] 5AH[7:0]); horizontal pixel offset, HOFF[10:0] 347H (subaddresses 5BH[2:0] 59H[7:0]); FOFF (subaddress 5BH[7]) Line number (1st field) Line number (2nd field) nominal VBI-lines nominal VBI-lines active video active video
Product specification
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
counting single field counting CVBS
HREF
F_ITU656
V123 VSTO [8:0] 134H VGATE
field
VSTA [8:0]
counting single field counting CVBS
HREF
F_ITU656 V123 VSTO [8:0] 134H VGATE
field
VSTA [8:0]
MHB540
inactive going edge V123 signal indicates whether field even. HREF active during falling edge V123, field (field HREF inactive during falling edge V123, field EVEN. specific position slope dependent internal processing delay change clock cycles from version version. control signals listed above available pins RTS0, RTS1, according following table:
NAME HREF F_ITU656 V123 VGATE
RTS0 (PIN K13)
RTS1 (PIN L10)
(PIN
(PIN
further information programming section, Tables 171, 173.
Fig.30 Vertical timing diagram Hz/625 line systems.
2003
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
counting single field counting CVBS
HREF
F_ITU656 V123 VSTO [8:0] 101H VGATE
field
VSTA [8:0] 011H
counting single field counting CVBS
HREF
F_ITU656 V123 VSTO [8:0] 101H VGATE
field
VSTA [8:0] 011H
MHB541
inactive going edge V123 signal indicates whether field even. HREF active during falling edge V123, field (field HREF inactive during falling edge V123, field EVEN. specific position slope dependent internal processing delay change clock cycles from version version. control signals listed above available pins RTS0, RTS1, according following table:
NAME HREF F_ITU656 V123 VGATE
RTS0 (PIN
RTS1 (PIN L10)
(PIN
(PIN
further information programming section, Tables 171, 173.
Fig.31 Vertical timing diagram Hz/525 line systems.
2003
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
CVBS input
burst processing delay expansion port: 1/LLC
expansion port data output
sync clipped
HREF 2/LLC CREF CREF2 2/LLC programming range (step size: 8/LLC) 2/LLC -107 2/LLC 2/LLC
HREF 2/LLC 2/LLC CREF CREF2 programming range (step size: 8/LLC) 2/LLC
2/LLC 2/LLC -106
MHB542
signals HREF, CREF2 CREF available pins RTS0 and/or RTS1 (see Section 18.2.2.19 Tables 172); their polarity inverted RTP0 and/or RTP1. signals HREF available (see Section 18.2.2.20 Table 173).
Fig.32 Horizontal timing diagram (50/60 Hz).
2003
Philips Semiconductors
Product specification
HD-CODEC
Scaler
SAA7108AE; SAA7109AE
overall zooming (HV_zoom) restricted input/output data rate relationships. With safety margin running running out, maximum HV_zoom equal T_input_field T_v_blanking 0.98 -in_pixel in_lines out_cycle_per_pix T_out_clk example: Input from decoder: pixel, lines, 16-bit data 13.5 data rate, cycle pixel; output: 8-bit data MHz, cycles pixel; maximum HV_zoom equal 0.98 1.18 Input from port: pixel, lines, 8-bit data data rate (ITU 656), cycles pixel; output port: 16-bit data clock, cycle pixel; maximum HV_zoom equal 16.666 0.98 2.34 video scaler receives input signal from video decoder from expansion port port). gets 16-bit Y-CB-CR input data continuous rate 13.5 from decoder. discontinuous data stream accepted from expansion port, normally 8-bit wide like Y-CB-CR data, accompanied pixel qualifier XDQ. input data stream sorted into data paths, luminance samples), time multiplexed chrominance samples. Y-CB-CR input format converted horizontal prescaling vertical filter scaling operation. scaler operation defined programming pages representing different tasks that applied field alternating define regions field (e.g. with different scaling range, factors, signal source during even fields). Each programming page contains control for: Signal source selection formats Task handling trigger conditions Input output acquisition window definition prescaler, scaler phase scaling.
High Performance video Scaler (HPS) based system implemented SAA7140, enhanced some aspects. Vertical upsampling supported processing pipeline buffer capacity enhanced, allow more flexible video stream timing image port, discontinuous transfers handshake. internal data flow from block block discontinuous dynamically, scaling process. flow controlled internal data valid data request flags (internal handshake signalling) between sub-blocks. Therefore entire scaler acts pipeline buffer. Depending actually programmed scaling parameters effective buffer exceed entire line. access/bandwidth requirements frame buffer reduced significantly. high performance video scaler SAA7108AE; SAA7109AE following major blocks. Acquisition control (horizontal vertical timer) task handling (the region/field/frame based processing) Prescaler, horizontal downscaling integer factor, combined with appropriate band limiting filters, especially anti-aliasing format Brightness, saturation contrast control scaled output data Line buffer, with asynchronous read write, support vertical upscaling (e.g. videophone application, converting into lines, Y-CB-CR Vertical scaling, with phase accurate Linear Phase Interpolation (LPI) zoom downscaling, phase accurate Accumulation Mode (ACM) large downscaling ratios better anti-alias suppression Variable Phase Delay (VPD), operates horizontal phase accurate interpolation arbitrary non-integer scaling ratios, supporting conversion between square rectangular pixel sampling Output formatter scaled Y-CB-CR Y-CB-CR only (format also data) FIFO, 32-bit wide, with pixel capacity Y-CB-CR formats Output interface, 16-bit (only extended port) data pins wide, synchronous asynchronous operation, with stream events discrete pins, coded data stream.
2003
Philips Semiconductors
Product specification
HD-CODEC
data will handled specific input format need programming page (equals task). pass through operation processing prescaler vertical scaling disabled, however horizontal fine scaling activated. Upscaling (oversampling, zooming), free frequency folding, factor achieved, required some software data slicing algorithms. These samples transported through image port valid data output only format. lines framed codes. 9.3.1 ACQUISITION CONTROL TASK HANDLING (SUBADDRESSES 80H, 90H, 91H, CFH)
SAA7108AE; SAA7109AE
task handling controlled subaddress 90H; Section 9.3.1.2.
9.3.1.1
Input field processing
trigger event field sequence detection from external signals port) defined subaddress 92H. state scalers horizontal reference signal time vertical reference edge taken from port field sequence identifier (FID). example, falling edge input signal reference state input logic that time, detected field logic bits XFDV[92H[7]] XFDH[92H[6]] define detection event state flag from port. default setting XFDV XFDH `00' taken from state horizontal input falling edge vertical input. scaler gets corresponding field information directly from SAA7108AE; SAA7109AE decoder path. flag used determine whether first second field frame going processed within scaler, also used trigger conditions task handling (see bits STRC[1:0] 90H[1:0]). According 656, logic means first field frame. ease application, polarities detection results port signals internal decoder changed XFDH. sync from decoder path half line timing (due interlaced video signal), scaler processing only recognises full lines, during fields from decoder line count scaler possibly shift line, compared field. This compensated switching vertical trigger event, defined XDV0, opposite sync edge using vertical scalers phase offsets. vertical timing decoder seen Figs horizontal vertical reference events inside data stream (from port) real-time reference signals from decoder path processed differently, trigger events input acquisition also have programmed differently.
acquisition control receives horizontal vertical synchronization signals from decoder section from port. acquisition window generated pixel line counters appropriate places data path. Only qualified pixels lines (lines with qualified pixel) counted from port. acquisition window parameters follows: Signal source selection: input video stream formats from decoder, from port (programming bits SCSRC[1:0] 91H[5:4] FSC[2:0] 91H[2:0]) Remark: input data from internal decoder should controlled decoder output formatter registers (see Section 9.2) Vertical offset: defined lines video source, parameter YO[11:0] 99H[3:0] 98H[7:0] Vertical length: defined lines video source, parameter YS[11:0] 9BH[3:0] 9AH[7:0] Vertical length: defined number target lines, result vertical scaling, parameter YD[11:0] 9FH[3:0] 9EH[7:0] Horizontal offset: defined number pixels video source, parameter XO[11:0] 95H[3:0] 94H[7:0] Horizontal length: defined number pixels video source, parameter XS[11:0] 97H[3:0] 96H[7:0] Horizontal destination size: defined target pixels after fine scaling, parameter XD[11:0] 9DH[3:0] 9CH[7:0]. source start offset XO(11:0) YO(11:0) opens acquisition window, target size (XD11 XD0, YD11 YD0) closes window, however window vertically there less output lines than required. trigger events pixel line counts horizontal vertical reference edges defined subaddress 92H. 2003
Philips Semiconductors
Product specification
HD-CODEC
Table Processing trigger start XDV1 92H[5] XDV0 92H[4] 92H[2]
SAA7108AE; SAA7109AE
DESCRIPTION Internal decoder: processing triggers falling edge V123 pulse (see Figs Hz)), starts earliest with rising edge decoder HREF line number:
(50/60 field), respectively (50/60 field) (decoder count) (50/60 field), respectively (50/60 field) (decoder count) External stream: processing starts earliest with line number system), respectively line system) (according count) Remarks: activate task, start condition must fulfilled acquisition window offsets must reached. example, case `start immediately', regions defined field, offset lower region must greater than (offset length) upper region, not, actual counted position upper task beyond programmed offsets processing will `wait next Basically, trigger conditions checked when task activated. important know that they checked while task inactive. possible trigger next logic logic with overlapping offset active video ranges between tasks (e.g. task STRC[2:0] YO[11:0] task STRC[2:0] YO[11:0] results output field rate 50/3 Hz). After power-on software reset (via SWRST[88H[5]]) task gets priority over task
9.3.1.2
Task handling
task handler controls switching between programming register sets. controlled subaddresses C0H. task enabled global control bits TEA[80H[4]] TEB[80H[5]]. handler then triggered events which defined each register set. event programming error task handling complete scaler reset initial states software reset SWRST[88H[5]] being logic software reset must done after programming especially programming registers, related acquisition window scaler reprogrammed while task active. difference disabling/enabling task, which evaluated running task (when SWRST logic that sets internal state machines directly their idle states. start condition handler defined bits STRC[1:0] 90H[1:0] means: start immediately, wait next sync, next logic next logic evaluated vertical horizontal offsets reached. With RPTSK[90H[2]] logic actual running task repeated (under defined trigger conditions) before handing control over alternate task. support field rate reduction, handler also enabled skip fields (bits FSKP[2:0] 90H[5:3]) before executing task. TOGGLE flag generated (used correct output field processing), which changes state beginning task every time task activated; examples given Section 9.3.1.3.
2003
Philips Semiconductors
Product specification
HD-CODEC
9.3.1.3 Output field processing
SAA7108AE; SAA7109AE
When OFIDC scalers input field available output field EAV, respectively IGP0 (IGP1), output selected. When OFIDC[90H[6]] TOGGLE information available output field EAV, respectively IGP0 (IGP1) output selected. Additionally defined CONLH[90H[7]]. When CONLH[90H[7]] (default) sets logic logic inverts SAV/EAV possible mark output both tasks different SAV/EAV codes. This also seen `task flag' pins IGP0 (IGP1), TASK output selected.
reference output field processing, signals available back-end hardware. These signals input field from scaler source TOGGLE flag, which shows that active task used even number times. Using single both tasks reducing field frame rate with task handling functionality, TOGGLE information used reconstruct interlaced scaled picture reduced frame rate. TOGGLE flag synchronized input field detection, only dependent interpretation this information external hardware i.e. whether output scaler processed correctly; Section 9.3.3.
2003
This text here white force landscape pages rotated correctly when browsing through Acrobat reader.This text here _white force landscape pages rotated correctly when browsing through Acrobat reader.This text here inThis text here white force landscape pages rotated correctly when browsing through Acrobat reader. white force landscape pages Table Example field processing 2003 Philips Semiconductors
HD-CODEC
FIELD SEQUENCE FRAME/FIELD SUBJECT EXAMPLE 1(1) Processed task State detected TOGGLE flag SAV/EAV byte Required sequence conversion vertical scaler(8) Output(9) Notes Single task every field; OFIDC subaddress 40H; TEB[80H[5]] Tasks used scale different output windows, priority task after SWRST. Both tasks frame rate; OFIDC subaddresses 42H. examples association between input tasks flipped, dependent which time SWRST de-asserted. Task frame rate constructed from neighbouring motion phases; task frame rate equidistant motion phases; OFIDC subaddresses 45H. Task frame rate equidistant motion phases; OFIDC subaddresses 49H. State prior field. assumed that input/output (upper lines); upper lines; lower lines. data output; output. EXAMPLE 2(2)(3) EXAMPLE 3(2)(4)(5) 0(7) 0(7) EXAMPLE 4(2)(4)(6) 1(7) 1(7)
SAA7108AE; SAA7109AE
Product specification
Philips Semiconductors
Product specification
HD-CODEC
9.3.2 HORIZONTAL SCALING
SAA7108AE; SAA7109AE
XC2_1[A2H[3]], which defines weighting incoming pixels during averaging process XC2_1 XC2_1 prescaler creates prescale dependent low-pass, with filter taps. parameter XACL[5:0] used vary low-pass characteristic given integer prescale 1/XPSC[5:0]. user therewith decide between signal bandwidth (sharpness impression) alias. equation XPSC[5:0] calculation Npix_in XPSC[5:0] lower integer -Npix_out where, range from (value allowed); Npix_in number input pixel, Npix_out number desired output pixel over complete horizontal scaler. prescaler results XACL[5:0] XC2_1 dependent gain amplification. amplification calculated according equation: gain [(XACL[5:0] XC2_1) (XC2_1 recommended sequence lengths weights, which results gain amplification, these amplitudes renormalized XDCG[2:0] controlled shifter prescaler. renormalization range XDCG[2:0] 1/2. down 1/128. Other amplifications have normalized using following control circuitry. these cases prescaler overall gain e.g. accumulation sequence (XACL[5:0] XC2_1 XDCG[2:0] must `010', which equals amplify signal (SATN[7:0] CONT[7:0] value lower integer 64). XACL[5:0] XPSC[5:0] dependent. XACL[5:0] must XPSC[5:0]. XACL[5:0] used find compromise between bandwidth (sharpness) alias effects.
overall horizontal scaling factor split into binary rational value according following output pixel equation: scale ratio -input pixel 1024 scale ratio -XPSC[5:0] XSCY[12:0] where, parameter prescaler XPSC[5:0] parameter phase interpolation XSCY[12:0] 8191 only theoretical values). example, 1/3.5 split into 1.14286. binary factor processed prescaler, arbitrary non-integer ratio achieved variable phase delay circuitry, called horizontal fine scaling. latter calculates horizontally interpolated samples with 6-bit phase accuracy, which relates less than jitter regular sampling schemes. Together, prescaler fine scaler form horizontal scaler SAA7108AE; SAA7109AE. Using accumulation length function prescaler (XACL[5:0] A1H[5:0]), application destination dependent (e.g. scale display compression machine), compromise between visible bandwidth alias suppression found.
9.3.2.1
Horizontal prescaler (subaddresses D7H)
prescaling function consists anti-alias filter stage integer prescaler, which together form adaptive prescale dependent low-pass filter balance sharpness aliasing effects. pre-filter stage implements different low-pass characteristics reduce anti-alias downscales range 1/2. optimized filter built-in, which reduces artefacts output formats used combination with prescaler scale); Table function prescaler defined integer prescaling ratio XPSC[5:0] A0H[5:0] (equals 63), which covers integer downscale range from 1/63 averaging sequence length XACL[5:0] A1H[5:0] (equals 63); range from gain renormalization XDCG[2:0] A2H[2:0]; from 1/128)
2003
Philips Semiconductors
Product specification
HD-CODEC
Remark: bandwidth considerations XPSC[5:0] XACL[5:0] chosen differently previously mentioned equations Table horizontal phase scaling able scale range from zooming factor downscaling factor 1024/8191. Figs show some frequency characteristics prescaler. Table shows recommended prescaler programming. Other programming, than given Table result better alias suppression, resulting gain amplification needs compensated control, according equation: CONT[7:0] SATN[7:0] lower integer gain Where: 2XDCG[2:0] gain gain (XC2_1 XACL[5:0] XC2_1). Table prefilter functions PFUV[1:0] A2H[7:6] PFY[1:0] A2H[5:4] LUMINANCE FILTER COEFFICIENTS bypassed 1.75 1.75 12221
XDCG[2:0]
SAA7108AE; SAA7109AE
example, XACL[5:0] XC2_1 then gain required XDCG[2:0] horizontal source acquisition timing prescaling ratio identical both luminance chrominance path, filter settings defined differently channels. Fade-in fade-out filters achieved copying original source sample each first last pixel after prescaling. Figs show frequency characteristics selectable filters.
CHROMINANCE COEFFICIENTS bypassed 12221
2003
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
(dB) PFY[1:0] PFY[1:0] PFY[1:0] 0.05 0.15 0.25 0.35
MHB543
0.45 f_sig/f_clock
Fig.33 Luminance prefilter characteristic.
(dB) PFUV[1:0] PFUV[1:0] PFUV[1:0] 0.025 0.05 0.075 0.125 0.15 0.175
MHB544
0.225 0.25 f_sig/f_clock
Fig.34 Chrominance prefilter characteristic.
2003
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
(dB) XC2_1 Zero's -XACL with XACL (1), (2), (3), 0.05 0.15 0.25 0.35
MHB545
0.45 f_sig/f_clock
Fig.35 Examples prescaler filter characteristics: effect increasing XACL[5:0].
(dB) XC2_1 XACL[5:0] XC2_1 XACL[5:0] XC2_1 XACL[5:0] XC2_1 XACL[5:0] XC2_1 XACL[5:0] XC2_1 XACL[5:0] 0.05 0.15 0.25 0.35
MHB546
0.25 0.33
0.45 f_sig/f_clock
Fig.36 Examples prescaler filter characteristics: setting XC2_1
2003
Philips Semiconductors
Product specification
HD-CODEC
Table Example XACL[5:0] usage RECOMMENDED VALUES PRESCALE XPSC RATIO [5:0] LOWER BANDWIDTH REQUIREMENTS XACL[5:0]
SAA7108AE; SAA7109AE
HIGHER BANDWIDTH REQUIREMENTS XACL[5:0]
XC2_1
XDCG[2:0]
XC2_1
XDCG[2:0]
PREFILTER PFY[1:0]/ PFUV[1:0]
1/8(1) 1/16(1)
1/8(1) 1/8(1)
1/16(1)
1/16(1)
Note Resulting function.
2003
Philips Semiconductors
Product specification
HD-CODEC
9.3.2.2 Horizontal fine scaling (variable phase delay filter; subaddresses DFH) 9.3.3.1
SAA7108AE; SAA7109AE
Line FIFO buffer (subaddresses 91H, C1H, E4H)
horizontal fine scaling (VPD) should operate scaling ratios between (0.8 1.6), also used direct scaling range from 1/7.999 (theoretical) zoom (restriction internal data path architecture), without prescaler. combination with prescaler compromise between sharpness impression alias found, which signal source application dependent. luminance channel filter structure with taps implemented, chrominance filter with taps. Luminance chrominance scale increments (XSCY[12:0] A9H[4:0] A8H[7:0] XSCC[12:0] ADH[4:0] ACH[7:0]) defined independently, must relationship actual data path implementation. phase offsets XPHY[7:0] AAH[7:0] XPHC[7:0] AEH[7:0] used shift sample phases slightly. XPHY[7:0] XPHC[7:0] covers phase offset range 7.999T 1/32T. phase offsets should also programmed ratio. underlying phase controlling 13-bit resolution. According equations Npix_in XSCY[12:0] 1024 XPSC[5:0] Npix_out XSCY[12:0] XSCC[12:0] covers scale range from 0.125 zoom 3.5. acts equivalent polyphase filter with possible phases. combination with prescaler, possible high accurate samples from highly anti-aliased integer downscaled input picture. 9.3.3 VERTICAL SCALING
line FIFO buffer dual ported structure pixels, with asynchronous write read access. line buffer used various functions, functions available simultaneously. line buffer buffer complete unscaled active video line more than shorter lines (only non-mirror mode), selective repetition vertical zoom-up. zooming from lines lines e.g., every fourth line requested (read) twice from vertical scaling circuitry calculation. conversion input sampling scheme (MPEG, video phone, Indeo YUV-9) like sampling scheme chrominance line buffer read twice four times, before being refilled again source. means input acquisition window definition preserved, that processing starts with line containing luminance chrominance information input. bits FSC[2:1] 91H[2:1] define distance between lines. case FSC2 FSC1 have `00'. line buffer also used mirroring, i.e. flipping image left right, vanity picture video phone application (bit YMIR[B4H[4]]). mirror mode only active prescaled line held FIFO time. line buffer utilized excessive pipeline buffer discontinuous variable rate transfer conditions expansion port image port.
9.3.3.2
Vertical scaler (subaddresses EFH)
Vertical scaling ratio from (theoretical zoom) 1/63 (icon) applied. vertical scaling block consists another line delay, vertical filter structure, that operate different modes. These Linear Phase Interpolation (LPI) Accumulation (ACM) modes, controlled YMODE[B4H[0]].
vertical scaler SAA7108AE; SAA7109AE decoder part consists line FIFO buffer line repetition vertical scaler block, which implements vertical scaling input data stream different operational modes from theoretical zoom down icon size 1/64. vertical scaler located between horizontal fine scaler, that used compensate gain amplification mode (see Section 9.3.3.2) internal RAMs only 8-bit wide.
2003
Philips Semiconductors
Product specification
HD-CODEC
mode: linear phase interpolation mode (YMODE neighbouring lines source video stream added together, weighted factors corresponding vertical position (phase) target output line relative source lines. This linear interpolation 6-bit phase resolution, which equals intra line phases. interpolates between consecutive input lines only. mode should applied scaling ratios around (down 1/2), must applied vertical zooming. mode: vertical Accumulation (ACM) mode (YMODE represents vertical averaging window over multiple lines, sliding over field. This mode also generates phase correct output lines. averaging window length corresponds scaling ratio, resulting adaptive vertical low-pass effect, greatly reduce aliasing artefacts. applied downscales only from ratio down 1/64. results scale dependent gain amplification, which precorrected control scaler part. phase scale controlling calculates 16-bit resolution, controlled parameters YSCY[15:0] B1H[7:0] B0H[7:0] YSCC[15:0] B3H[7:0] B2H[7:0], continuously over entire filed. start offset applied phase processing means parameters YPY3[7:0] YPY0[7:0] BFH[7:0] BCH[7:0] YPC3[7:0] YPC0[7:0] BBH[7:0] B8H[7:0]. start phase covers range 255/32 1/32 lines offset. programming appropriate, opposite, vertical start phase values (subaddresses EFH) depending odd/even field source video stream page cycle, frame conversion field rate conversion supported (i.e. de-interlacing, re-interlacing). Figs Tables describe offsets. Remark: vertical start phase, well scaling ratio defined independently luminance chrominance channels, must same values actual implementation accurate output processing. vertical processing communicates input side with line FIFO buffer. scale related equations are: Scaling increment calculation mode, downscale zoom: YSCY[15:0] YSCC[15:0] Nline_in lower integer 1024 Nline_out value compensate gain mode (contrast saturation have set): CONT[7:0] 2003
SAA7108AE; SAA7109AE
A5H[7:0] respectively SATN[7:0] A6H[7:0] Nline_out lower integer Nline_in 1024 lower integer YSCY[15:0]
9.3.3.3
vertical phase offsets
shown Section 9.3.1.3, scaler processing randomly over interlaced input sequence. Additionally interpretation timing between field real-time detection means state sync falling edge sync result different field interpretation. vertically scaled interlaced output also gets larger vertical sampling phase error, interlaced input fields processed, without regard actual scale starting point operation (see Fig.37). four events considered illustrated Fig.38. Tables usable common phase offset. should noted that equations Fig.38 also produce interpolated output unscaled case, geometrical reference position conversions position first line lower field; Table there need UP-LO LO-UP conversion input field reference back-end operation, then UP-LO UP-UP LO-UP LO-LO line phase shift (PHO that skipped; this case given Table SAA7108AE; SAA7109AE supports phase offset registers task component (luminance chrominance). value represents phase shift line. registers assigned following events; e.g. subaddresses BBH: B8H: input field task status (toggle status, Section 9.3.1.3) B9H: input field task status BAH: input field task status BBH: input field task status Depending input signal (interlaced non-interlaced) task processing field reduced processing with tasks, examples Section 9.3.1.3), other combinations also possible, basic equations same.
Philips Semiconductors
Product specification
HD-CODEC
SAA7108AE; SAA7109AE
unscaled input field field
scaled output, phase offset field field
scaled output, with phase offset field field
correct scale dependent position
scale dependent start offset
mismatched vertical line distances
MHB547
Fig.37 Basic problem interlaced vertical scaling (example: downscale 3/5).
handbook, full pagewidth
field upper
field lower
field case UP-UP
field case LO-LO
field case UP-LO
field case LO-UP
MHB548
1024 Offset line shift input line shift
YSCY[15:0] input line shift scale increment YSCY[15:0] scale increment offset
Fig.38 Derivation phase related equations (example: interlace vertical scaling down 3/5, with field conversion).
2003
Philips Semiconductors
Product specification
HD-CODEC
Table Examples vertical phase offset usage: global equations INPUT FIELD UNDER PROCESSING Upper input lines Upper input lines Lower input lines Lower input lines OUTPUT FIELD INTERPRETED upper output lines lower output lines upper output lines lower output lines USED ABBREVIATION UP-UP UP-LO LO-UP LO-LO
SAA7108AE; SAA7109AE
EQUATION PHASE OFFSET CALCULATION (DECIMAL VALUES) YSCY[15:0] YSCY[15:0]
Table Vertical phase offset usage; assignment phase offsets DETECTED INPUT FIELD upper lines TASK STATUS VERTICAL PHASE OFFSET YPY0[7:0] YPC0[7:0] CASE EQUATION USED
case 1(1) UP-UP (PHO) case 2(2) UP-UP case 3(3) UP-LO case case case case UP-UP (PHO) UP-LO UP-UP YSCY[15:0] LO-LO LO-UP LO-LO YSCY[15:0] LO-LO LO-LO LO-UP
upper lines
YPY1[7:0] YPC1[7:0]
lower lines
YPY2[7:0] YPC2[7:0]
case case lower lines YPY3[7:0] YPC3[7:0] case
case case Notes
Case OFIDC[90H[6]] scaler input field output back-end interprets output field logic upper output lines. Case OFIDC[90H[6]] task status output back-end interprets output field logic upper output lines. Case OFIDC[90H[6]] task status output back-end interprets output field logic upper output lines.
2003
Philips Semiconductors
Product specification
HD-CODEC
data decoder capture (subaddresses 7FH)
SAA7108AE; SAA7109AE
adjust slicers processing input signal source, there offsets horizontal vertical direction available (parameters HOFF[5B,59[2:0,7:0]], VOFF[5B,5A[4,7:0]] FOFF[5B[7]]). difference scalers counting, slicers offsets define position horizontal vertical trigger events related processed video field. trigger events falling edge HREF falling edge V123 from decoder processing part. relationship these programming values input signal recommended values seen Tables
SAA7108AE; SAA7109AE contains versatile data decoder. implementation programming model accords data slicer built-in multimedia video data acquisition circuit SAA5284. circuitry recovers actual clock phase during clock run-in period, slices data bits with selected data rate, groups them into bytes. result buffered into dedicated data FIFO with capacity bytes Dwords). clock frequency, signal source, field frequency accepted error count must defined subaddress 40H. data standards that supported given Table lines field, line, standards selected (LCRxxx[41:57[7:0]]: 4-bit programming bits). definition line valid rest corresponding field, normally text data (video data) should selected there (LCR24 FFH) stop activity data slicer during active video. Table Data types supported data slicer block DATA TYPE NUMBER 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 11

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