Speech Synthesizer Linear Products SPSS011D IMPORTANT N
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TSP50C0x/1x Family
Speech Synthesizer
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SPSS011D
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Copyright 2000, Texas Instruments Incorporated
Preface
Read This First
About This Manual
This manual describes TSP50C0x/1x family speech synthesizing devices. When necessary, differences between family members shown separate consecutive sections. object this user's guide provide information needed implement speech synthesizer design using TSP50C0x/1x device.
This Manual
This document contains following chapters: Chapter Introduction TSP50C0x/1x Family This chapter describes TSP50C0x/1x family features, options, assignments descriptions, gives brief introduction linear predictive coding. TSP50C0x/1x Family Architecture This chapter describes architecture TSP50C0x/1x family with separate section driver, reference voltage contrast adjustment, clock options TSP50C12. TSP50C0x/1x Electrical Specifications This chapter provides electrical specifications TSP50C0x/1x family. TSP50C0x/1x Assembler This chapter contains detailed description TSP50C0x/1x assembler. TSP50C0x/1x Instruction This chapter provides instruction TSP50C0x/1x. TSP50C0x/1x Applications This chapter describes various hints useful advice designing applications TSP50C0x/1x.
Chapter
Chapter
Chapter
Chapter Chapter
Running Title-Attribute Reference
Chapter
Customer Information This chapter describes customer information including development cycles structure, speech development/production sequence, mechanical information, ordering information. Script Preparation Speech Development Tools This appendix describes script preparation development tools TSP50C0x/1x. TSP50C0x/1x Sample Synthesis Program This appendix contains sample synthesis program that counts numbers from five. External Initialization This appendix contains sample program initialize external ROM. DTMF Program This appendix contains sample program that generates dual-tone multifrequency (DTMF) signal. Sample Music Program This appendix contains sample program that produces Mozart's Minuet TSP50P11 (OTP) Version This appendix contains advance information TSP50P11, which one-time-programmable (OTP) version TSP50C11.
Appendix
Appendix
Appendix
Appendix
Appendix
Appendix
Notational Conventions
Notational Conventions
This document uses following conventions.
Program listings, program examples, interactive displays shown special typeface similar typewriter's. Here sample program listing:
0349 0059 0350 005A 005B SPEAK2 LUAA ANEC StopWord -Get word -End phase?
syntax descriptions following notational conventions used this guide:
reserved keyword instruction, command directive) shown bold capital letters should entered shown. optional field indicated brackets italics describes type information that should entered: [label User-supplied contents indicated angle brackets italics describe type information that should entered: <num required blank indicated caret (^).
following syntax example demonstrates notational conventions used this guide. [<label >]^ABAAC^.[<comment lower case numeric value indicates that value hexadecimal (e.g., 01FAh, 032Bh, 0FFh). addresses this manual hexadecimal format unless otherwise noted. other numbers decimal format unless otherwise noted. Abbreviations:
'04: TSP50C04 '06: TSP50C06 '10: TSP50C10 '11: TSP50C11 '12: TSP50C12 '13: TSP50C13 '14: TSP50C14 '19: TSP50C19 LSB, MSB: Least significant most significant bits LSbyte, MSbyte: Least significant most significant bytes
Read This First
Notational Conventions
Port refers pins operating together. Port refers pins operating together. Individual bits register indicated with register abbreviation followed decimal point number (e.g., register mode register MR.2). contents location pointed address stored register. indicates contents register
Information About Cautions
Information About Cautions
This book contain cautions.
This example caution statement. caution statement describes situation that could potentially damage your software equipment.
information caution provided your protection. Please read each caution carefully.
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Trademarks
IBM, PC/XT, PC/AT trademarks Corporation. trademark Texas Instrument Incorporated.
Read This First
viii
Contents
Contents
Introduction TSP50C0x/1x Family Introduction Description 1.2.1 TSP50C0x/1x Family Features 1.2.2 TSP50C04/06/13/14/19 Additional Features 1.2.3 TSP50C10/11 Additional Features 1.2.4 TSP50C12 Additional Features Options 1.3.1 Two-Pin Push Pull (Option Accurate Bits LSB) 1.3.2 Single-Pin Single Ended (Option Accurate Only Bits LSB) 1.3.3 Single-Pin Double Ended (Option Accurate Bits LSB) 1-11 TSP50C10/11 Assignments Descriptions 1-13 TSP50C12 Assignments Descriptions 1-16 TSP50C04/06/13/14/19 Assignments Descriptions 1-18 Introduction (Linear Predictive Coding) 1-19 1.7.1 Vocal Tract 1-19 1.7.2 Model 1-20 1.7.3 Data Compression 1-20 TSP50C0x/1x Family Architecture TSP50C0x/1x Functional Description 2.1.1 Read-Only Memory (ROM) 2.1.2 Program Counter 2.1.3 Program Counter Stack 2.1.4 TSP50C10/11 Random-Access Memory (RAM) 2.1.5 TSP50C12 Random-Access Memory (RAM) 2.1.6 TSP50C04/06/13/14/19 Random-Access Memory (RAM) 2.1.7 Arithmetic Logic Unit (ALU) 2.1.8 Register 2.1.9 Register 2.1.10 Register 2.1.11 Status Flag 2.1.12 Integer Mode Flag 2-10 2.1.13 Timer Register 2-10 2.1.14 Timer Prescale Register 2-11 2.1.15 Pitch Register Pitch-Period Counter (PPC) 2-11
Contents
Contents
2.1.16 Speech Address Register 2.1.17 Parallel-to-Serial Register 2.1.18 Input/Output Ports 2.1.19 Mode Register Speech Synthesizer 2.2.1 Synthesizer Mode 2.2.2 Synthesizer Mode 2.2.3 Synthesizer Mode 2.2.4 Synthesizer Mode 2.2.5 Synthesizer 2.2.6 Frame-Length Control 2.2.7 Digital-to-Analog Converter Interrupts TSP50C12 Functional Description 2.4.1 TSP50C12 Driver 2.4.2 TSP50C12 Drive Type 2.4.3 TSP50C12 Drive Type TSP50C12 Reference Voltage Contrast Adjustment TSP50C12 Clock Options
2-12 2-13 2-13 2-15 2-17 2-17 2-17 2-17 2-17 2-18 2-18 2-19 2-20 2-22 2-22 2-24 2-26 2-28 2-29
TSP50C0x/1x Electrical Specifications Absolute Maximum Ratings Over Operating Free-Air TemperatureRange Recommended Operating Conditions Timing Requirements TSP50C10/11 Electrical Characteristics TSP50C12 Electrical Characteristics TSP50C04/06/13/14/19 Electrical Characteristics 3-10 TSP50C0x/1x Assembler Description Notation Used Invoking Assembler Command-Line Options 4.3.1 BYTE Unlist Option 4.3.2 DATA Unlist Option 4.3.3 XREF Unlist Option 4.3.4 TEXT Unlist Option 4.3.5 WARNING Unlist Option 4.3.6 Complete XREF Switch 4.3.7 Object Module Switch 4.3.8 Listing File Switch 4.3.9 Page-Eject Disable Switch 4.3.10 Error-to-Screen Switch 4.3.11 Instruction Count Switch 4.3.12 Binary-Code File-Disable Switch
Contents
Assembler Input Output Files 4.4.1 Assembly Source File 4.4.2 Assembly Binary Object File 4.4.3 Assembly Tagged Object File 4.4.4 Assembly Listing File Source-Statement Format 4.5.1 Label Field 4.5.2 Command Field 4.5.3 Operand Field 4-10 4.5.4 Comment Field 4-10 4.5.5 Constants 4-10 4.5.6 Decimal Integer Constants 4-10 4.5.7 Binary Integer Constants 4-10 4.5.8 Hexadecimal Integer Constants 4-11 4.5.9 Character Constants 4-11 4.5.10 Assembly-Time Constants 4-11 Symbols 4-12 Character Strings 4-13 Expressions 4-14 4.8.1 Arithmetic Operators Expressions 4-14 4.8.2 Parentheses Expressions 4-14 Assembler Directives 4-15 4.9.1 AORG Directive 4-16 4.9.2 BYTE Directive 4-16 4.9.3 COPY Directive 4-16 4.9.4 DATA Directive 4-17 4.9.5 Directive 4-17 4.9.6 Directive 4-18 4.9.7 Directive 4-18 4.9.8 LIST Directive 4-19 4.9.9 NARROW Directive 4-19 4.9.10 OPTION Directive 4-19 4.9.11 PAGE Directive 4-22 4.9.12 RBYTE Directive 4-22 4.9.13 RDATA Directive 4-23 4.9.14 RTEXT Directive 4-23 4.9.15 TEXT Directive 4-24 4.9.16 TITL Directive 4-24 4.9.17 Directive 4-25 4.9.18 WIDE Directive 4-25
TSP50C0x/1x Instruction Instruction Syntax TSP50C0x/1x Assembly Instructions
Contents
Contents
TSP50C0x/1x Applications Synthesizer Control 6.1.1 Speech Coding Decoding 6.1.2 Usage 6.1.3 Usage Program Overview 6.2.1 Initialization 6.2.2 Phrase Selection 6.2.3 Speech Initialization 6.2.4 Level-1- Interrupt Service Routine 6-10 6.2.5 Frame-Update Routine 6-10 Synthesis Program Walk-Through 6-11 Arithmetic Modes 6-39 Operation Multiply Instruction 6-42 Standby Mode 6-43 Slave Mode 6-44 6.7.1 Slave-Mode Write Operation 6-45 6.7.2 Slave-Mode Read Operation 6-47 TSP60C18/81 Interface 6-48 6.8.1 External Mode 6-48 6.8.2 TSP60C18/81 Signals 6-48 6.8.3 TSP60C18 Addressing 6-50 6.8.4 TSP60C81 Addressing 6-50 6.8.5 TSP60C18/81 Addressing Modes 6-51 6.8.6 TSP60C18/81 Control 6-53 6.8.7 Initialization TSP60C18/81 6-54 6.8.8 Direct-Address Initialization TSP60C18/81 6-55 6.8.9 8-Bit Indirect-Address Initialization TSP60C18/81 6-56 6.8.10 16-Bit Indirect-Address Initialization TSP60C18/81 6-57 6.8.11 Placing TSP60C18/81 Low-Power Standby Condition 6-58 Instruction 6-60 6.9.1 From Internal 6-62 6.9.2 From External 6-62 6.9.3 From Internal 6-63 6.10 Generating Tones Using 6-66 6.10.1 Operation TASYN Instruction Mode 6-66 6.10.2 Timing Considerations Mode 6-67 6.10.3 DTMF Program Walk-Through 6-67 6.11 TSP50C19 Programming 6-75 6.11.1 Memory Block Selection 6-75 6.11.2 Data Block Selection 6-76 6.11.3 Preparing Source Code 6-76 6.11.4 Program Location 6-77 Customer Information Development Cycle
Running Title-Attribute Reference
Summary Speech Development /Production Sequence Mechanical Information 7.3.1 N016 300-Mil Plastic Dual-In-Line Package 7.3.2 DW020 Plastic Small-Outline Wide-Body (SOWB) Package 7.3.3 FN068 68-Lead Plastic Leaded Chip Carrier (PLCC) Package 7.3.4 TSP50C12 (PLCC) Reflow Soldering Precautions 7-10 Ordering Information 7-11 Product Release Forms (TSP50C0x/1x) 7-11 7.5.1 Product Release Form TSP50C04 7-12 7.5.2 Product Release Form TSP50C06 7-14 7.5.3 Product Release Form TSP50C10A 7-16 7.5.4 Product Release Form TSP50C11A 7-18 7.5.5 Product Release Form TSP50C12 7-20 7.5.6 Product Release Form TSP50C13 7-22 7.5.7 Product Release Form TSP50C14 7-24 7.5.8 Product Release Form TSP50C19 7-26
Script Preparation Speech Development Tools Script Generation A.1.1 Speaker Selection A.1.2 Speech Collection A.1.3 Editing A.1.4 Pitfalls Speech Development Tools
TSP50C0x/1x Sample Synthesis Program External Initialization DTMF Program Sample Music Program TSP50P11 (OTP Version) Introduction Programming Mode Special Functions Testing Absolute Maximum Ratings Over Operating Free-Air Temperature Range Recommended Operating Conditions TSP50P11 Electrical Characteristics Protection Programming Interface Timing F-11 Differences Between TSP50P11 TSP50C11 F-13 Glossary
Chapter Title-Attribute Reference
xiii
Illustrations
Illustrations
1-10 1-11 1-12 1-13. 1-14 1-15 1-16 1-17
TSP50C10/11 Functional Block Diagram TSP50C12 Functional Block Diagram TSP50C04/06/13/14/19 Functional Block Diagram Output Waveform Two-Pin Push Pull (Option Four-Transistor Amplifier Circuit Operational Amplifier Interface Circuit Power Amplifier Interface Circuit Output Waveform Single Ended (Option 1-10 One-Transistor Amplifier Circuit 1-11 Output Waveform Single-Pin Double Ended (Option 1-12 Operational Amplifier Interface Circuit 1-12 TSP50C10/11 Assignments 1-13 Power-Up Initialization Circuit 1-15 Oscillator Circuit 1-15 TSP50C12 Assignments 1-16 TSP50C04/06/13/14/19 Assignments 1-18 LPC-12 Vocal Tract Model 1-20 TSP50C0x/1x System Block Diagram TSP50C10/11 TSP50C12 TSP50C04/06/13/14/19 During Speech Generation 2-18 TSP50C12 Driver Type Timing Diagram 2-25 TSP50C12 Driver Type Timing Diagram 2-27 TSP50C12 Voltage Doubler 2-28 Option Circuit 2-29 Initialization Timing Diagram Write Timing Diagram (Slave Mode) Read Timing Diagram (Slave Mode) External Interrupt Timing Diagram Typical Input Leakage Current INIT Frame Decoding Speech Parameter Unpacking Decoding ACAAC Extended-Sign Mode 6-41 ACAAC Integer Mode 6-41 Slave-Mode Write Operation 6-46
Illustrations
6-10 6-11
Slave-Mode Read-Then-Write Operation 6-47 TSP60C18/81-to-TSP50C0x/1x Hookup 6-53 Register Connections Instruction 6-60 Parallel-to-Serial Operation Instruction 6-61 Operation TASYN Mode 6-66 Format Data Register Before TASYN 6-66 Speech Development Cycle TSP50C04/06/10/11/13/14/19 16-Pin Package TSP50C04/06/10/11/13/14/19 20-Pin Package TSP50C12 68-Lead PLCC Package SDS5000 EVM50C1X SEB50C1X SEB60CXX ADP50C12 FAB50C1x TSP50P11 Assignments Simplified Timing Waveforms Normal Programming Timing Waveforms Programming with Protection Timing Waveforms F-10 Initialization Write Sequence Timing Waveforms F-11 Programming Read Sequence Timing Waveforms F-12
Contents
Tables
Tables
6-10
TSP50C10/11 Terminal Functions 1-14 TSP50C10/11 Configurations 1-15 TSP50C12 Terminal Functions 1-17 TSP50C04/06/13/14/19 Terminal Functions 1-18 Reserved Locations TSP50C19 Block Addressing Registers 2-14 Mode Register 2-16 Interrupt-1 Vectors 2-20 Interrupt-2 Vectors 2-21 TSP50C12 Display 2-23 Recommended Operating Conditions Options Timing Requirements Initialization Timing Requirements Write Timing Requirements (Slave Mode) Read Timing Requirements (Slave Mode) External Interrupt Timing Requirements TSP50C10/11 Electrical Characteristics Over Recommended Ranges Supply Voltage Operating Free-Air Temperature (unless otherwise noted) TSP50C12 Electrical Characteristics Over Recommended Ranges Supply Voltage Operating Free-Air Temperature (unless otherwise noted) TSP50C04/06/13/14/19 Electrical Characteristics Over Recommended Ranges Supply Voltage Operating Free-Air Temperature (unless otherwise noted) 3-10 Switches Options Summary Assembler Directives 4-15 TSP50C0x/1x Instruction TSP50C0x/1x Instruction Table Parameter Size Hardware-Fixed Locations Other Locations Used Sample Program FLAGS Descriptions Sample Program Usage Operation 6-40 TSP60C18/81 Functional Descriptions 6-49 TSP60C18/81 Pinout 6-50 TSP60C18/81 Addressing Modes 6-51 Indirect Address Example 6-52
Tables
6-11 6-12 6-13 6-14 6-15 6-16
Mode Register Control Data Source 6-61 Relative Weights Magnitude Bits 6-67 Sample Rates 6-69 TSP50C14 Memory Blocks 6-75 TSP50C19 Block Selection 6-75 ASM50C1x Assembler Relative Address Block Selected 6-76 TSP50P11 Terminal Functions Special Testing Functions Recommended Operating Conditions TSP50P11 Electrical Characteristics Over Recommended Ranges Supply Voltage Operating Free-Air Temperature (unless otherwise noted) Timing Characteristics Initialization Write Sequences F-11 Timing Characteristics Initialization Write Sequences F-12 TSP50P11 Excitation Function Differences F-13
Contents
xvii
xviii
Running Title-Attribute Reference
Chapter
Introduction TSP50C0x/1x Family
TSP50C0x/1x family speech synthesizers offer cost-effective solutions high-volume applications. Each incorporates built microprocessor that allows music well speech capability. Texas Instruments offers five sizes internal three minutes speech. addition, devices interfaced external speech memory.
Topic
Page
Introduction Description Options TSP50C10/11 Assignments Descriptions 1-13 TSP50C12 Assignments Description 1-16 TSP50C04/06/13/14/19 Assignments Descriptions 1-18 Introduction (Linear Predictive Coding) 1-19
Chapter Title-Attribute Reference
Introduction
Introduction
TSP50C0x/1x uses revolutionary architecture combine 8-bit microprocessor, speech synthesizer, ROM, RAM, low-cost single-chip system. architecture uses same (Arithmetic Logic Unit) synthesizer microprocessor, thus reducing chip area cost enabling microprocessor multiply operation Linear Predictive Coding (LPC) used synthesize high-quality speech data rate. TSP50C0x/1x highly flexible programmable, making suitable wide variety applications. system cost opens applications solid-state speech. They include:
Talking Clocks Toys Telephone Answering Machines Home Monitors Navigation Aids Laboratory Instruments Personal Computers Inspection Controls Inventory Controls Machine Controls Warehouse Systems Warning Systems Appliances Mailboxes Equipment Handicapped Learning Aids Computer-Aided Instruction Magazine Direct-Mail Advertisements Point-of-Sale Displays
Description
Description
TSP50C0x/1x divided into several functional blocks (Figure 1-1, Figure 1-2, Figure 1-3). shared speech synthesizer microcomputer. TSP50C0x/1x implements LPC-12 speech synthesis algorithm using 12-pole lattice filter. internal microprocessor fetches speech data from internal external (TSP60C18 TSP60C81), decodes speech data, sends decoded data synthesizer. microprocessor also interpolates (smooths) speech data between fetches. output synthesizer used drive transistor integrated-circuit amplifiers. Some digital low-pass filtering provided inside TSP50C0x/1x. general-purpose microprocessor TSP50C0x/1x also capable variety logical, arithmetic, control functions. often used nonsynthesis tasks customer's application well.
Figure 1-1. TSP50C10/11 Functional Block Diagram
Microcomputer Port Port
Speech Synthesizer
Microprocessor
Output
Timing Oscillator
OSC1 OSC2
Introduction TSP50C0x/1x Family
Description
Figure 1-2. TSP50C12 Functional Block Diagram
Common Outputs 24-Segment Outputs
Microcomputer Port Port
Driver
Speech Synthesizer
Microprocessor Output Timing Oscillator
OSC1 OSC2
Figure 1-3. TSP50C04/06/13/14/19 Functional Block Diagram
Microcomputer Port Port
Speech Synthesizer
Microprocessor
Output
Timing Oscillator
Description
1.2.1
TSP50C0x/1x Family Features
features entire TSP50C0x/1x family following list.
1.2.2
Programmable LPC-12 Speech Synthesizer 8-Bit Microprocessor With Instructions CMOS Technology Power Dissipation Configurations Mask Selectable 10-kHz 8-kHz Speech Sample Rate Software Controllable Lines Lines With Two-Pin Output) Internal Timer External Interrupt Single-Cycle Multiply Instruction Executes 600,000 Instructions Second Built-in Interface TSP60C18 TSP60C81 Speech Built-In Slave Mode Microprocessor Peripheral
TSP50C04/06/13/14/19 Additional Features
features TSP50C04/06/13/14/19 following list.
Direct Speaker Drive Capability speaker) Internal Clock Generator That Requires External Components Two-Pin Output Pins Simultaneously Possible Configurations Mask Selectable Optional Doubling Output Twelve-Bit Words Bytes Bytes ROM:
TSP50C04 bytes ROM. TSP50C06 bytes ROM. TSP50C13 bytes ROM. TSP50C14 bytes ROM. TSP50C19 bytes paged ROM.
1.2.3
TSP50C10/11 Additional Features
features TSP50C10/11 following list.
Three Configurations Mask Selectable Twelve-Bit Words Bytes Bytes ROM:
TSP50C10 bytes ROM. TSP50C11 bytes ROM.
Introduction TSP50C0x/1x Family
Description
1.2.4
TSP50C12 Additional Features
features TSP50C12 following list.
Direct Drive Capability (192-Segment) Display Duty Cycle Bias Drive With On-Chip Voltage Reference Internal Contrast Adjustment Bytes Display Limited Direct Speaker Drive Capability Oscillator Option bytes Twelve-bit Words Bytes
Options
Options
TSP50C0x/1x offers three (digital-to-analog) output options match different applications. (digital-to-analog converter) pulse-width-modulated type with bits bits resolution 16-kHz 20-kHz sampling rate. Each option range segments sample period, with options having resolution third having resolution LSB. produces samples twice rate that data received from filter. example, filter running approximately kHz, then running approximately kHz. TSP50C04/06/13/14/19 used with normal-sized pulse width with option. option causes processor produce double-sized pulse width. This results higher volume output, which includes some risk clipping output.
1.3.1
Two-Pin Push Pull (Option Accurate Bits (±1/2 LSB)
Option works well with very efficient inexpensive four-transistor amplifier. requires pins, used second pin, meaning that only bits available. When idle, output value both pins high. When output value positive, goes with duty cycle proportional output value, while stays high. When output value negative, goes with duty cycle proportional output value, while stays high. This option offers resolution bits. Figure shows examples output waveforms with different output values. Each pulse divided into segments sample period. positive output value 480, goes segments while stays high. When idle output value both high. negative value 480, goes segments while stays high. This option used with TSP50C04/06/13/14/19 directly drive speaker applications where anti-aliasing low-pass filter needed. When device placed power state, this option places both lines high.
Introduction TSP50C0x/1x Family
Options
Figure 1-4. Output Waveform Two-Pin Push Pull (Option
High High
Output Value where shown 360)
Output Value
Output Value
Output Value
High High
Output Value where shown -120)
Output Value -240
Output Value
Output Value
Figure 1-5, Figure 1-6, Figure show examples circuits that used with this option.
Figure 1-5. Four-Transistor Amplifier Circuit
Speaker
Options
Figure 1-6. Operational Amplifier Interface Circuit
VDD/
Figure 1-7. Power Amplifier Interface Circuit
TSP50C0x/1x
LM386
Speaker
OUTPUT
2N2222
NOTES: 0.022 low-pass cutoff frequency: 1/(2R2 values given above, Gain control added connecting 10-µF capacitor series with 10-k pot. This series combination connected between pins When this done, should increased approximately
1.3.2
Single-Pin Single Ended (Option Accurate Only Bits LSB)
Option designed with single-transistor amplifier, offering lowest-cost solution still retaining pins. only bits resolution amplifier power consumption higher than four-transistor amplifier mentioned above. available TSP50C10,
Introduction TSP50C0x/1x Family
Options
TSP50C11, TSP50C04/06/13/14/19. duty cycle output proportional output value. output value duty cycle 50%. output value increases from maximum, duty cycle goes from being high time 100% high. value goes from most negative value, duty cycle decreases from high Each pulse divided into segments sample period. shown Figure 1-8, when output value 480, goes 2-240| segments. When output value goes segments. When devices placed low-power state, this option places output into state. Note: Using Option causes click beginning speech (under certain conditions) during synthesis. Software available minimize these clicks.
Figure 1-8. Output Waveform Single Ended (Option
|x/2 240|
High
|x/2-240|
Output Value Output Value where shown 240)
Output Value
Output Value
High
Output Value
Output Value
Output Value
Output Value
Figure shows example circuit that used with option
1-10
Running Title-Attribute Reference
Figure 1-9. One-Transistor Amplifier Circuit
Speaker
0.1-µF Disc
2N3904
1.3.3
Single-Pin Double Ended (Option Accurate Bits (±1/2 LSB)
Option provided with operational power amplifiers. offers both bits resolution pins available TSP50C10, TSP50C11, TSP50C12. When output value zero, output biased approximately VDD. When output value positive, output pulses about duty cycle proportional output value. When output value negative, output pulses with duty cycle proportional output value. Figure 1-10 shows examples output waveforms with different output values. Each pulse divided into segments sample period. positive output value 480, goes segments. When idle, output value goes VDD. negative value 480, goes high segments. When devices placed low-power state, this option places output into state.
Chapter Title-Attribute Reference
1-11
Options
Figure 1-10. Output Waveform Single-Pin Double Ended (Option
Output Value where shown 360)
Output Value
Output Value
Output Value
Output Value where shown -360)
Output Value -240
Output Value
Output Value
Figure 1-11 shows example circuit that used with option
Figure 1-11. Operational Amplifier Interface Circuit
1-12
TSP50C10/11 Assignments Descriptions
TSP50C10/11 Assignments Descriptions
Figure 1-12 shows assignments TSP50C10/11. Table provides terminal functional descriptions. Table shows possible TSP50C10/11 configurations. Figure 1-13 illustrates recommended power-up initialization circuit. Note that pullup resistor required lower than Figure 1-14 illustrates recommended clock circuit. Refer subsection 2.1.18, Input/Output Ports, more information configuration.
Figure 1-12. TSP50C10/11 Assignments
PACKAGE (TOP VIEW) PACKAGE (TOP VIEW)
INIT OSC1 OSC2
PB1/DA2
INIT OSC1 OSC2
PB1/
internal connection
Introduction TSP50C0x/1x Family
1-13
TSP50C10/11 Assignments Descriptions
Table 1-1. TSP50C10/11 Terminal Functions
Terminal Name INIT Terminal Number Package Package Description output. Three mask options available. output. Three mask options available. Initialize input. When INIT goes low, clock stops, TSP50C10/11 goes into low-power mode, program counter zero, contents retained. INIT pulse sufficient reset processor. Clock input. Crystal ceramic resonator between OSC1 OSC2, signal into OSC1. 10-kHz sampling rate 7.68 8-kHz sampling rate. Clock return 8-bit bidirectional port
OSC1
OSC2
2-bit bidirectional port supply voltage Ground terminal
operation this depends option selected.
1-14
TSP50C10/11 Assignments Descriptions
Table 1-2. TSP50C10/11 Configurations
16-Pin Package Number
With external interrupt
20-Pin Package Number
Master 1-Pin 1-Pin PB1/ 2-Pin
Slave 1-Pin BUSY/D7
Master 1-Pin TSP60C18 SRCK
Figure 1-13. Power-Up Initialization Circuit
Optional Reset Switch
INIT
Figure 1-14. Oscillator Circuit
TSP50C0x/1x
INIT
OSC1
OSC2
-MHz 7.68 -MHz Crystal Ceramic Resonator
Introduction TSP50C0x/1x Family
1-15
TSP50C12 Assignments Descriptions
TSP50C12 Assignments Descriptions
Figure 1-15 shows assignments TSP50C12. Table provides terminal functional descriptions. configurations Table also applies TSP50C12, numbers given different. Figure 1-13 illustrates recommended power-up initialization circuit, Figure 1-14 illustrates recommended clock circuit. TSP50C12 available only form. Refer subsection 2.1.18, Input/Output Ports, more information configuration.
Figure 1-15. TSP50C12 Assignments
PLCC PACKAGE (TOP VIEW)
PB1/DA2 OSC2 OSC1
INIT VLCD
internal connection
1-16
TSP50C12 Assignments Descriptions
Table 1-3. TSP50C12 Terminal Functions
Terminal Name INIT Terminal Number Description output. options available. output. options available. Bidirectional Bidirectional Initialize input. When INIT goes low, clock stops, TSP50C12 goes into low-power mode, program counter zero, contents retained. INIT pulse sufficient reset processor. Clock input. Crystal ceramic resonator between OSC1 OSC2, signal into OSC1. 10-kHz sampling rate 7.68 8-kHz sampling rate. Clock return 8-bit bidirectional port common lines (rows) segment lines (columns)
OSC1
OSC2 SEG1 SEG24
VLCD
supply voltage supply voltage Ground terminals Voltage doubler capacitor connection
operation this depends option selected. Ceramic resonator requires pins. oscillator requires timing buffered clock output trim monitoring.
Introduction TSP50C0x/1x Family
1-17
TSP50C04/06/13/14/19 Assignments Descriptions
TSP50C04/06/13/14/19 Assignments Descriptions
Figure 1-16 shows assignments TSP50C04/06/13/14/19. Table provides terminal functional descriptions. configurations Table apply TSP50C04/06/13/14/19 with exception numbering assignment. Figure 1-13 illustrates recommended power-up initialization circuit TSP50C04/06/13/14/19. OSC1 should tied either VDD. Refer subsection 2.1.18, Input/Output Ports, more information configurations.
Figure 1-16. TSP50C04/06/13/14/19 Assignments
PACKAGE (TOP VIEW) PACKAGE (TOP VIEW)
INIT OSC1
INIT OSC1
internal connection
Table 1-4. TSP50C04/06/13/14/19 Terminal Functions
Terminal Name INIT Terminal Number Package Package Description output. options available. output. options available. Initialize input. When INIT goes low, clock stops, TSP50C04/06/13/14/19 goes into low-power mode, program counter zero, contents retained. INIT pulse sufficient reset processor. OSC1 should tied VDD. 8-bit bidirectional port 2-bit bidirectional port supply voltage
OSC1
Ground terminal Both driven with same levels when option selected. 1-18
Introduction (Linear Predictive Coding)
Introduction (Linear Predictive Coding)
LPC-12 system uses mathematical model human vocal tract enable efficient digital storage re-creation realistic speech. understand LPC, essential understand vocal tract works. This introduction, therefore, begins with short description vocal tract, after which model data compression techniques addressed. short discussion techniques pitfalls collecting, analyzing, editing speech synthesis included Appendix Script Preparation Speech Development Tools. more information, contact your Field Sales Representative Regional Technology Center.
1.7.1
Vocal Tract
Speech result interaction three elements vocal-tract from lungs, restriction that converts flow sound, vocal cavities that positioned resonate properly. from lungs expelled through vocal tract when muscles chest diaphragm compressed. Pressure used volume control with higher pressure louder speech. flows through vocal tract, makes little sound there restriction. vocal cords type restriction. They tightened across vocal tract stop flow air. Pressure builds behind them forces them open. This happens over over, generating series pulses. tension vocal cords varied change frequency pulses. Many speech sounds, such sound, produced this type restriction, which called voiced speech. different type restriction mouth causes hissing sound called white noise. sound good example. White noise occurs when tongue some part mouth close contact when lips pursed. This restriction causes high flow velocities then creating turbulence that, turn, produces white noise, which called unvoiced speech. pulses from vocal cords noise from turbulence have fairly broad, flat spectral characteristics. other words, they noise, speech. shape oral cavity changes noise into recognizable speech. positions tongue, lips, jaws change resonance vocal tract, shaping noise restricted airflow into understandable sounds.
Introduction TSP50C0x/1x Family
1-19
Introduction (Linear Predictive Coding)
1.7.2
Model
model incorporates elements analogous each elements vocal tract previously described. excitation function generator that models both types restriction, gain-multiplication stage model possible levels pressure from lungs, digital filter model resonance oral nasal cavities. Figure 1-17 shows model schematic form. excitation function generator accepts coded pitch information input generate series pulses similar vocal cord pulses. also generate white noise. waveform then multiplied energy factor that corresponds pressure from lungs. Finally, signal passed through digital filter that models shape oral cavity. TSP50C0x/1x, this filter twelve poles, synthesis referred LPC-12.
Figure 1-17. LPC-12 Vocal Tract Model
Pitch
Periodic
LPC-12 Digital Filter
White Noise Energy Filter Coefficients
1.7.3
Data Compression
data compression LPC-12 takes advantage other characteristics speech. Speech changes fairly slowly, oral nasal cavities tend fall into certain areas resonance more than others. speech analyzed frames generally from long. inputs model calculated average entire frame. synthesizer smooths interpolates data during frame that there abrupt transition each frame. Often speech changes even more slowly than frame.
1-20
Introduction (Linear Predictive Coding)
Texas Instruments model allows repeat frame which only values changed pitch energy. filter coefficients kept constant from previous frame. take advantage recurrent nature resonance oral cavity, coefficients encoded with anywhere from seven three bits each coefficient. coding table designed that more coverage given coefficient values that occur frequently.
Introduction TSP50C0x/1x Family
1-21
1-22
Running Title-Attribute Reference
Chapter
TSP50C0x/1x Family Architecture
This chapter describes architecture function TSP50C0x/1x family speech synthesizers including RAM, ROM, registers, flags, DAC.
Topic
Page
TSP50C0x/1x Functional Description Speech Synthesizer 2-17 Interrupts 2-20 TSP50C12 Functional Description 2-22 TSP50C12 Reference Voltage Contrast Adjustment 2-28 TSP50C12 Clock Options 2-29
Chapter Title-Attribute Reference
TSP50C0x/1x Functional Description
TSP50C0x/1x Functional Description
shown block diagram Figure 2-1, major components TSP50C0x/1x speech synthesizer, 8-bit microprocessor, internal 4K-byte (TSP50C04), 6K-byte (TSP50C06), 8K-byte (TSP50C10/13),16K-byte (TSP50C11/12/14), 32K-byte (TSP50C19), input/output ports. When synthesis disabled, instructions fetched microprocessor from 600,000 (10-kHz speech sample rate) 480,000 (8-kHz speech sample rate) times second. These instructions control actions TSP50C0x/1x. placing different instruction patterns ROM, TSP50C0x/1x programmed accomplish wide variety tasks. generate speech, processor accesses speech data from either internal external source such TSP60C18 speech ROM, EPROM, host processor. Once data been read, processor must unpack decode individual speech parameters store results dedicated section RAM. synthesizer shares access addresses individual parameter locations needed when generating speech. instruction execution rate slows 280,000 224,000 instruction cycles second during synthesis because synthesizer also shares (Arithmetic Logic Unit) data paths with microprocessor. microprocessor must perform interpolation during each frame well fetch data next frame. consists 8-bit bidirectional port (port 2-bit bidirectional port (port Each software configured input output push pull open drain pullup driver). There specialized modes specific functions. Slave mode configures TSP50C0x/1x peripheral host microprocessor. External mode allows TSP50C0x/1x interface with TSP60C18 TSP60C81 speech ROM.
TSP50C0x/1x Functional Description
Figure 2-1. TSP50C0x/1x System Block Diagram
Integer Flag Integer Flag' Status Flag Status Flag'
Timer Prescale Mode Buffer Random Number
Register
12-Bit 8-Bit (TSP50C04/06/13/14/19) 8-Bit (TSP50C10/11/12) 8-Bit Display (TSP50C12 Only) 14-Bit Data 4-Bit Contrast Adjust (TSP50C12 Only) 8-Bit 2-Bit Program Counter Port Port
3-Level Stack Speech Address
4096-Byte (TSP50C04) 6144-Byte (TSP50C06) 8192-Byte (TSP50C10/13) 16384-Byte (TSP50C11/12/14) 32768-Byte (TSP50C19) 384-Byte Excitation
Pitch Counter
Pitch Register Excitation Synthesizer Stack Output
TSP50C0x/1x Family Architecture
TSP50C0x/1x Functional Description
2.1.1
Read-Only Memory (ROM)
TSP50C04 4K-byte ROM. TSP50C06 6K-byte ROM. TSP50C10 TSP50C13 each have 8K-byte ROM. TSP50C11/12/14 each have 16K-byte ROM. TSP50C19 32K-byte ROM. used program instructions speech data required application. Certain locations ROM, described Table 2-1, reserved specific purposes.
Table 2-1. Reserved Locations
Address 0000h 0010h 001Fh 0FE0h 0FFFh 17E0h 17FFh 1FE0h-1FFFh 3FE0h 3FFFh 5FFDh 5FFFh 7FFDh 7FFFh Function Execution start location after INIT rising edge Interrupt start locations (see Section 2.3, Interrupts) Texas Instruments test code (TSP50C04 only) Texas Instruments test code (TSP50C06 only) Texas Instruments test code (TSP50C10/13 only) Texas Instruments test code (TSP50C11/12/14/19 only) Texas Instruments test code (TSP50C19 only) Texas Instruments test code (TSP50C19 only)
TSP50C19 paged shown Table 2-2. lower 8K-bytes available time. upper 8K-byte block address space switched between three separate blocks depending upon value loaded output ports. Section 6.11, TSP50C19 Programming, more information.
Table 2-2. TSP50C19 Block Addressing
Address 0000h 1FFFh 2000h 3FFFh 2000h-3FFFh 2000h 3FFFh Port Port Block Block Block Block Block Listing Address Accessed 0000h 1FFFh 2000h 3FFFh 4000h 5FFFh 6000h 7FFFh
TSP50C0x/1x Functional Description
accessed following four ways:
2.1.2
program counter used address processor instructions. instruction used transfer bits from register. counter initialized LUAPS instruction. (speech address register) points location used. LUAA instruction used transfer byte from into register. value register when LUAA executed points address used. LUAB instruction used transfer byte from into register. value register when LUAB executed points address used.
Program Counter
TSP50C0x/1x 14-bit program counter that points next instruction executed. After instruction executed, program counter normally incremented point next instruction. following instructions modify program counter: CALL branch branch address register call subroutine
RETN return from subroutine RETI return from interrupt short branch
2.1.3
Program Counter Stack
program counter stack three levels. When subroutine called interrupt occurs, contents program counter pushed onto stack. When RETN RETI executed, contents stack location popped into program counter.
TSP50C0x/1x Family Architecture
TSP50C0x/1x Functional Description
2.1.4
TSP50C10/11 Random-Access Memory (RAM)
TSP50C10/11 locations (Figure 2-2). first locations used synthesizer bits long. remaining locations bits long. When synthesizing speech, entire used algorithm data storage. control registers also mapped into address space from 080h 087h. more information, subsection 2.1.18, Input/Output Ports.
Figure 2-2. TSP50C10/11
Address 000h 001h (Synthesis RAM)
00Eh 00Fh 010h (General-Purpose RAM) 011h
07Eh 07Fh 080h (I/O) 081h
086h 087h
2.1.5
TSP50C12 Random-Access Memory (RAM)
TSP50C12 12-bit synthesizer locations 8-bit general purpose locations (Figure 2-3). also 8-bit display locations 4-bit contrast adjustment register. ports mapped into address space from 0F0h-0F7h.
TSP50C0x/1x Functional Description
Figure 2-3. TSP50C12
Address 000h 001h (Synthesis RAM)
00Eh 00Fh 010h (General-Purpose RAM) 011h
07Eh 07Fh 080h (Display) 081h
096h 097h 098h (Contrast)
0F0h (I/O) 0F1h
0F6h 0F7h
2.1.6
TSP50C04/06/13/14/19 Random-Access Memory (RAM)
TSP50C04/06/13/14/19 same basic layout TSP50C10/11 (see Figure 2-4) with exception. general-purpose location range from 010h 03Fh.
TSP50C0x/1x Family Architecture
TSP50C0x/1x Functional Description
Figure 2-4. TSP50C04/06/13/14/19
Address 000h 001h (Synthesis RAM)
00Eh 00Fh 010h (General-Purpose RAM) 011h
03Fh
080h (I/O) 081h
086h 087h
2.1.7
Arithmetic Logic Unit (ALU)
performs arithmetic logic functions microprocessor synthesizer. bits length, providing resolution needed speech synthesis. When 8-bit data transferred ALU, they right justified. input upper bits either zeros (integer mode) equal 8-bit data (extended-sign mode) depending arithmetic mode selected using EXTSG INTGR instructions. description each instruction specific information. comparison operations performed lower bits. capable doing 8-bit 14-bit multiply with 14-bit scaled result single instruction cycle.
2.1.8
Register
register, accumulator, primary 14-bit register used arithmetic logical operations. contents transferred
TSP50C0x/1x Functional Description
most other registers. loaded from RAM, ROM, most other registers. contents saved dedicated storage register during level-1 interrupts restored RETI instruction.
Register
2.1.9
Register
register 8-bit register used index register. access instructions (except direct-addressing instructions TAMD, TMAD, TMXD) register point specific location. register also used general-purpose counter. contents register saved during level-1 interrupts restored RETI instruction. location with illegal address loaded register, board with chip accepts problem appears chip.
Register
2.1.10 Register
14-bit register used temporary storage. helpful storing address because exchanged with register using instruction. register added subtracted from, exchanged with register, making useful data storage after calculations. contents register saved during level-1 interrupts restored RETI instruction.
Register
2.1.11 Status Flag
status flag cleared various instructions depending result instruction. Refer individual description instructions Chapter TSP50C0x/1x Instruction Set, determine effect instruction
TSP50C0x/1x Family Architecture
TSP50C0x/1x Functional Description
value status flag. SBR, CALL instructions conditional, modifying program counter only when status flag set. value status flag unknown power Therefore, first instruction after power these conditional instructions, execution instruction cannot predicted. value status flag saved during interrupts restored RETI instruction.
Status Flag
2.1.12 Integer Mode Flag
integer mode flag INTGR instruction cleared EXTSG instruction. When integer mode flag (integer mode), upper bits data less than bits length zero filled when being transferred added subtracted from registers. When integer mode flag cleared (extended-sign mode), upper bits data less than bits length sign extended when being transferred added subtracted from registers. value integer mode flag saved during interrupts restored RETI instruction.
Integer Mode Flag
2.1.13 Timer Register
8-bit timer register used generating interrupts counting events. decrements once each time timer prescale register goes from 000h 0FFh. loaded using TAinstruction examined with TTMA instruction. When decrements from 000h 0FFh, level-2 interrupt request generated. interrupts enabled interrupt being processed already, immediate interrupt occurs; not, interrupt request remains pending until interrupts enabled. timer continues count whether reloaded.
Timer Register
Note: timer does decrement before initialized. However, EVM, timer decrements after STOP/RUN.
2-10
TSP50C0x/1x Functional Description
2.1.14 Timer Prescale Register
8-bit timer prescale register programmable divider between processor clock timer register. When decrements from 000h 0FFh, timer register also decremented. timer prescale register then reloaded with value preset latch, counting starts again. timer prescale register clock comes from internal clock. internal clock runs 1/16 clock frequency chip; thus, timer prescale register decrements once every instruction cycle when mode. TAPSC instruction loads timer prescale register's preset latch. timer been initialized with TAinstruction, TAPSC instruction also loads timer prescale register.
Timer Prescale Register
2.1.15 Pitch Register Pitch-Period Counter (PPC)
Although 14-bit pitch register pitch-period counter part synthesizer, they affect microprocessor many ways. pitch-period counter controls timing periodic impulse (excitation function) that simulates vocal cords. TSP50C0x/1x, pitch-period counter also used synchronize interpolation speech parameters during each frame. This pitch-synchronous interpolation helps minimize inevitable noise from interpolation making occur lowest energy part speech making harmonic speech fundamental frequency. pitch register used when speech being synthesized. following discussion presumes that mode active. pitch register loaded with TASYN instruction. When speech starts, pitch-period counter cleared. pitch-period counter decremented 020h each speech sample, with speech samples occurring 8-kHz 10-kHz rate. When pitch-period counter decrements past zero, pitch register added When pitch-period counter goes below 200h when pitch register added with result less than 200h, level-1 interrupt occurs. This interrupt used synchronize interpolation algorithm. excitation function when pitch-period counter between 140h 000h. further information, Chapter TSP50C0x/1x Applications, this book.
TSP50C0x/1x Family Architecture
2-11
TSP50C0x/1x Functional Description
Pitch Register
voiced unvoiced frames, register must zero when data transferred from register pitch register with TASYN instruction (see following illustration). this done, problems with TSP50C0x/1x chip occur that apparent when using TSE50C1x chip.
Register
Pitch Register
voiced frames, pitch register must loaded with value higher than 1FFEh. addition, there three recommendations minimum pitch-register value voiced frames. First, required that pitch-register value 042h higher. this done, problems with chip occur that apparent with chip. Second, strongly recommended that pitch register loaded with value 142h higher. This permits complete excitation pulse used synthesis. Third, best results with recommended software algorithms, pitch-register value 202h higher recommended. requirement that pitch register value less than equal 1FFEh recommendation value greater than equal 142h result pitch range when operating with 10-kHz sample rate. unvoiced frames, pitch register required loaded with value between 042h 3FEh. this done, problems with chip occur that apparent with chip.
2.1.16 Speech Address Register
speech address register (SAR) 14-bit register that used point data internal ROM. LUAPS instruction transfers value speech address register loads parallel-to-serial register (see subsection 2.1.17, Parallel-to-Serial Register) with internal value pointed SAR. instruction then used bring
2-12
TSP50C0x/1x Functional Description
bits time from parallel-to-serial register into accumulator. Whenever parallel-to-serial register becomes empty, loaded with internal value pointed SAR, incremented.
Speech Address Register
2.1.17 Parallel-to-Serial Register
8-bit parallel-to-serial register used primarily unpack speech data. loaded with bits data from internal pointed speech address register, internal pointed register, external TSP60C18 TSP60C81 speech pointed TSP60C18 TSP60C81. LUAPS instruction used initialize parallel-to-serial register zero counter. instructions then used transfer eight bits from parallel-to-serial register accumulator. When parallel-to-serial register empty, automatically reloaded. When from RAM, however, register automatically incremented. EXTROM RAMROM bits mode register control source parallel-to-serial register. speech address register description subsection 2.1.16, Speech Address Register, more information.
Parallel-to-Serial Register
2.1.18 Input/Output Ports
bidirectional lines 8-bit port 2-bit port available interfacing with external devices. Each individually programmable input output under control respective data-direction register. addition, each output individually programmed using pullup-enable register output modes push pull open drain pullup). Each input programmed same register resistive pullup high impedance. four registers associated with each ports memory mapped. Only bits port available outside chip. states upper bits port undetermined TSP50C04/06/10/11/12/13/14. states upper four bits port undetermined TSP50C19. Transfers from port registers register leave bits register
TSP50C0x/1x Family Architecture
2-13
TSP50C0x/1x Functional Description
corresponding upper bits port TSP50C04/06/10/11/12/13/14 upper four bits TSP50C19 undetermined. Details registers shown Table 2-3. TSP50C19 uses bits port Only four available outside chip. remaining used page select ROM. Section 6.11, TSP50C19 Programming, more information.
Table 2-3. Registers
register type location
Location Register Data Input Register (DIR) Pullup Enable Register (PER) Data Direction Register (DDR) Data Output Register (DOR) Type Read Only Read/Write Read/Write Read/Write Port 080h 081h 082h 083h Port 084h 085h 086h 087h
TSP50C12, register locations
register function state
Desired Function Input, High Impedance Input, Internal Pullup Output, Active Pullup Output, Active Pullup Output, Open Drain Output, Open Drain State High Impedance Passive Pullup High Impedance
read DDR, PER, registers indicates last value written them. read always indicates actual level I/O, which true even when output. This allows true bidirectional data flow without having switch port between input output. avoid high-current conditions, this should only attempted pins open drain with written data register.
2-14
TSP50C0x/1x Functional Description
Leaving high-impedance unconnected could cause power consumption rise while processor mode. power consumption between with increase current through input. This should cause problem with device functionality. When part standby mode, unconnected high-impedance pins have effect either power consumption device functionality. also slave mode making TSP50C0x/1x usable peripheral host microprocessor. Port connected 8-bit data controlled (PB1) strobe (PB0). read (R/W high strobe low) puts port output latch values port write (R/W strobe low) latches value data into port input latch. addition, output latch (pin PA7) cleared. This makes possible write-handshake line. lines that used data this mode should configured inputs. external mode, TSP50C0x/1x interfaced easily TSP60C18 TSP60C81 speech ROM. used chip enable strobe output TSP60C18 TSP60C81, used clock. used address data transfer, other must used read/write control TSP60C18 TSP60C81. When two-pin push-pull option selected output TSP50C10/11/12, used second pin, making unavailable I/O. this case, attempt should made interrupt. mode register bits both cleared, high-to-low transition causes level-1 interrupt. This used generate interrupt with external event.
2.1.19 Mode Register
mode register (Table 2-4) 8-bit write-only register that controls operating mode TSP50C0x/1x. When INIT goes low, mode register bits cleared. mode register saved during subroutine call interrupt.
TSP50C0x/1x Family Architecture
2-15
TSP50C0x/1x Functional Description
Table 2-4. Mode Register
Mode register bits
Mode Register Bits MASTER RAMROM EXTROM ENA2 ENA1
Mode register descriptions
Name ENA1 Disables level-1 interrupt High Enables level-1 interrupt
Disables processor instruction cycles Enables processor instruction used microprocessor. cycles dedicated synthesis when instruction cycles dedicated synthesis when high. Disables mode. Level-1 interrupt either Enables mode. high causes interrupt 200h mode otherwise. rate fosc microprocessor control excitation value. causes interrupt rate fosc microprocessor control register.50% instruction cycles dedicated synthesis when high. Disables level-2 interrupt Enables level-2 interrupt
ENA2 EXTROM
Disables operation external hardware Enables operation external hardware interface. interface.
RAMROM Enables data source instructions Enables data source instructions either internal external ROM. internal RAM. MASTER Enables master operation. available Enables slave operation. becomes pins controlled internal microprocessor. hardware chip enable strobe, becomes R/W. Port controlled PB1. Enables pitch-controlled excitation sequence Enables random excitation sequence when when mode (PCM low, voiced). mode (PCM low, unvoiced).
2-16
Speech Synthesizer
Speech Synthesizer
task generating synthetic speech divided between programmable microprocessor dedicated speech synthesizer. four speech synthesizer modes, which bits mode register, discussed following paragraphs.
2.2.1
Synthesizer Mode
When bits both cleared, synthesizer disabled. instruction cycles devoted microprocessor.The TASYN instruction transfers register pitch register, making easy load pitch register before starting synthesizer. this mode, level-1 interrupt triggered high-to-low transition PB1.
2.2.2
Synthesizer Mode
This normal speaking mode. TASYN instruction loads pitch register, level-1 interrupt triggered pitch-period counter going below 200h. Fifty-three percent instruction cycles used synthesizer. microprocessor controls speech synthesis unpacking decoding parameters, setting update interval (frame rate), interpolating parameters during frame. speech synthesizer acts 12-pole digital lattice filter, pitch-controlled white-noise excitation generator, 2-pole digital low-pass filter, digital-to-analog converter. Speech parameter input received from dedicated space microprocessor RAM, speech samples generated kHz. Communication between microprocessor speech synthesizer takes place shared memory space microprocessor RAM. Refer Chapter TSP50C0x/1x Applications, this book more information.
2.2.3
Synthesizer Mode
This mode used tone music generation very-high-bit-rate speech. microprocessor uses instruction cycles, TASYN instruction transfers register directly register. level-1 interrupt occurs rate twice speech sample rate kHz), giving access unfiltered output.
2.2.4
Synthesizer Mode
When both bits set, synthesizer runs normally with excitation function provided software. level-1 interrupt occurs
TSP50C0x/1x Family Architecture
2-17
Speech Synthesizer
speech sample rate, TASYN instruction transfers register excitation function input synthesizer. This mode included with RELPS (Residual Encoded Linear Predictive Synthesis) similar techniques. synthesizer takes instruction cycles this mode.
2.2.5
Synthesizer
synthesizer uses locations 001h 00Fh RAM. When synthesis taking place, parameters synthesizer come directly from these locations. addresses shown Figure 2-5.
Figure 2-5. During Speech Generation
Address 000h 001h 002h 003h 004h 005h 006h 007h 008h 009h 00Ah 00Bh 00Ch 00Dh 00Eh 00Fh Comments Used Synthesis Energy (LPC-12 Values) (Low-Pass Filter)
2.2.6
Frame-Length Control
frame length controlled value into prescale register range over which timer allowed vary. Typical synthesis interpolation routines timer decrement through range fixed size, prescale value should selected give proper frame duration based timer's range.
2-18
Speech Synthesizer
2.2.7
Digital-to-Analog Converter
TSP50C0x/1x contains internal digital-to-analog converter (DAC) connected output synthesizer. available three pulse-width-modulated forms TSP50C10/11 pulse-width-modulated forms TSP50C04/06/12/13/14/19. Section 1.3, Options, more information. outputs samples rate given fosc 480. 9.6-MHz oscillator, this results output sample rate kHz. 7.68-MHz oscillator, this results output sample rate kHz. output rate twice speech sample rate, with digital low-pass filter modes except mode. When device initialized, placed state. This state same zero state two-pin single-pin double-ended modes, single-pin single-ended mode, goes maximum negative value. This fact must taken into account minimize clicks during speech. Once synthesis generation turned following speech other sound output (return mode maintains whatever value last loaded filter mode) TASYN instruction.
TSP50C0x/1x Family Architecture
2-19
Interrupts
Interrupts
TSP50C0x/1x interrupts: interrupt-1 interrupt-2. Both enabled disabled bits mode register. Interrupt-1 synthesis interrupt higher priority. also more hardware support. When interrupt-1 occurs, program counter placed program counter stack, status flag, integer mode flag, register, register, register saved dedicated storage registers. mode register saved restored during interrupts. Then program counter loaded with interrupt start location execution interrupt routine begins. When interrupt routine returns, these registers restored, program counter popped from stack. Interrupt-1 caused conditions depending state mode-register bits LPC. These conditions, well interrupt routine start address each case, shown Table 2-5.
Table 2-5. Interrupt-1 Vectors
Address 0018h 001Ah 001Ch 001Eh Interrupt Trigger Pitch-period counter less than 200h (see subsection 2.1.15) goes from high (see subsection 2.1.18) fosc clock (see subsection 2.2.4) fosc clock (see subsection 2.2.3)
Interrupt-2 lower priority cannot interrupt interrupt-1 routine. interrupted interrupt-1. During level-2 interrupt, program counter, status bit, integer mode flag only registers saved. register, register, register must saved program they used both routine being interrupted. mode register saved. Interrupt-2 always caused timer underflow timer going from 000h 0FFh starts different addresses depending state mode-register bits. Table shows interrupt-2 vectors.
2-20
Interrupts
Table 2-6. Interrupt-2 Vectors
Address 0010h 0012h 0014h 0016h level-2 interru caused timer underflow interrupts Interrupt Trigger
interrupting conditions interrupt-1 interrupt-2 interrupt-pending latches. interrupt enabled (and interrupt-2 case, overridden interrupt-1-pending condition), interrupt taken immediately. however, interrupt enabled, pending-interrupt latch causes interrupt occur soon respective interrupt enabled mode register. Interrupts taken middle double-byte instructions, during branch call instructions, during subroutine interrupt returns (RETN RETI). single instruction software loop (instruction BRA, CALL, itself) should avoided since interrupt never taken. Consecutively executed branches calls delay interrupts until after execution instruction eventual destination string branches calls). consecutive branches calls) avoided, worst-case interrupt delay main level four instruction cycles. worst-case delay occurs when interrupt occurs during first execution cycle branch first instruction branch destination address double-cycle instruction. When interrupt occurs, execution begins interrupt address. state status known when interrupt occurs, CALL instruction should used first instruction. SBRs used, since them always taken, possible some other instruction that sets status bit, followed SBR. mode register saved restored during interrupts. changes made mode register during interrupts remains effect after return, including enabling disabling interrupts. Note: level-1 interrupt followed immediately RETI, potential exists with some single byte instructions corrupt register upon return. avoid this problem, place RETI immediately interrupt vector. Instead, precede RETI with some other instruction.
TSP50C0x/1x Family Architecture
2-21
TSP50C12 Functional Description
TSP50C12 Functional Description
functionality TSP50C12 included without adding instructions instruction set. additional bits added serve display RAM. display physically placed addresses 080h 097h. result, port registers mapped from 0F0h 0F3h port registers mapped from 0F4h 0F7h. This mapping consistent with SE50C10 emulator device used extended mode (pin controllable). When data stored into display locations, immediately affect voltage levels segment outputs. Because microprocessor access time multiplexed with access, there asynchronous ambiguities segment outputs. display update routines slow, necessary buffer display data another area then transfer display more time efficient block move. voltage reference generator also included TSP50C12. This circuit eliminates need external voltage reference generator.
2.4.1
TSP50C12 Driver
TSP50C12 drive (192-segment) display with duty cycle. driver function controlled internal timing hardware. Display data stored dedicated section RAM. This data stored pixel form with consecutive 8-bit words. Table shows memory locations each pixel.
2-22
TSP50C12 Functional Description
Table 2-7. TSP50C12 Display
Address 080h 081h 082h 083h 084h 085h 086h 087h 088h 089h 08Ah 08Bh 08Ch 08Dh 08Eh 08Fh 090h 091h 092h 093h 094h 095h 096h 097h
NOTE:
S24c1 S16c1 S8c1 S24c2 S16c2 S8c2 S24c3 S16c3 S8c3 S24c4 S16c4 S8c4 S24c5 S16c5 S8c5 S24c6 S16c6 S8c6 S24c7 S16c7 S8c7 S24c8 S16c8 S8c8 S23c1 S15c1 S7c1 S23c2 S15c2 S7c2 S23c3 S15c3 S7c3 S23c4 S15c4 S7c4 S23c5 S15c5 S7c5 S23c6 S15c6 S7c6 S23c7 S15c7 S7c7 S23c8 S15c8 S7c8 S22c1 S14c1 S6c1 S22c2 S14c2 S6c2 S22c3 S14c3 S6c3 S22c4 S14c4 S6c4 S22c5 S14c5 S6c5 S22c6 S14c6 S6c6 S22c7 S14c7 S6c7 S22c8 S14c8 S6c8 S21c1 S13c1 S5c1 S21c2 S13c2 S5c2 S21c3 S13c3 S5c3 S21c4 S13c4 S5c4 S21c5 S13c5 S5c5 S21c6 S13c6 S5c6 S21c7 S13c7 S5c7 S21c8 S13c8 S5c8 S20c1 S12c1 S4c1 S20c2 S12c2 S4c2 S20c3 S12c3 S4c3 S20c4 S12c4 S4c4 S20c5 S12c5 S4c5 S20c6 S12c6 S4c6 S20c7 S12c7 S4c7 S20c8 S12c8 S4c8 S19c1 S11c1 S3c1 S19c2 S11c2 S3c2 S19c3 S11c3 S3c3 S19c4 S11c4 S3c4 S19c5 S11c5 S3c5 S19c6 S11c6 S3c6 S19c7 S11c7 S3c7 S19c8 S11c8 S3c8 S18c1 S10c1 S2c1 S18c2 S10c2 S2c2 S18c3 S10c3 S2c3 S18c4 S10c4 S2c4 S18c5 S10c5 S2c5 S18c6 S10c6 S2c6 S18c7 S10c7 S2c7 S18c8 S10c8 S2c8
S17c1 S9c1 S1c1 S17c2 S9c2 S1c2 S17c3 S9c3 S1c3 S17c4 S9c4 S1c4 S17c5 S9c5 S1c5 S17c6 S9c6 S1c6 S17c7 S9c7 S1c7 S17c8 S9c8 S1c8
Segment pixel given (common time) (common time)
TSP50C0x/1x Family Architecture
2-23
TSP50C12 Functional Description
2.4.2
TSP50C12 Drive Type
Type drive method places limitations series resistance pixel capacitance display. This drive type requires more complex display. Type option must selected customer given before releasing device mask tooling. Figure shows timing waveforms type option.
2-24
TSP50C12 Functional Description
Figure 2-6. TSP50C12 Driver Type Timing Diagram
-Vr' Frame Period -Vr' -Vr' -Vr' -Vr' -Vr'
(c1/c3/c8
(c1/c2/c6
Differential Voltage Across Pixel S1c1 (Vcommon Vsegment)
S1c1 "on"
S1c2 "off"
TSP50C0x/1x Family Architecture
2-25
TSP50C12 Functional Description
2.4.3
TSP50C12 Drive Type
Type drive method operates lower frequency, allowing common signal high first frame next frame. This option preferred applications that have large capacitance pixel loads high series trace resistances. This method also might used microprocessor operated higher frequencies. Type option must selected customer given before releasing device mask tooling. Figure shows timing waveforms type option.
2-26
TSP50C12 Functional Description
Figure 2-7. TSP50C12 Driver Type Timing Diagram
-Vr'
Frame Period
-Vr' -Vr' -Vr' -Vr' -Vr'
(c1/c3/c8
(c1/c2/c6
Differential Voltage Across Pixel S1c1 (Vcommon Vsegment)
S1c1 "on"
S1c2 "off"
TSP50C0x/1x Family Architecture
2-27
TSP50C12 Reference Voltage Contrast Adjustment
TSP50C12 Reference Voltage Contrast Adjustment
TSP50C12 contains internal voltage-reference generator regulate adjust reference voltages. voltage generator comprised voltage doubler, bandgap reference, voltage regulator, final trim DAC. VLCD provides isolated voltage supply voltage doubler. VLCD connected example, connected 4.5-V 4-cell battery supply improve power efficiency circuit. external capacitor should connected between VC2. external capacitor should connected between VLCD. bandgap provides reference voltage voltage regulator. voltage regulator nominal output mV). reference voltage trimmed writing (memory-mapped lower four bits location 098h). trim control ranges from steps (0000) steps (1111) from nominal with each step being approximately value this location initialized must initialization software routine. Figure shows diagram voltage doubler circuitry.
Figure 2-8. TSP50C12 Voltage Doubler
TSP50C12 Cpump 0.01 Cstore 0.047 VLCD
2-28
TSP50C12 Clock Options
TSP50C12 Clock Options
oscillator requires single external resistor between OSC1 with OSC2 left unconnected operating frequency. frequency shift, changes, limited over operating range center frequency function resistance requires trimming. applications requiring greater clock precision, ceramic resonator option also available. oscillator/ceramic resonator selection must made customer given before releasing device mask tooling.
Figure 2-9. Option Circuit
OSC1 OSC2
TSP50C0x/1x Family Architecture
2-29
2-30
Running Title-Attribute Reference
Chapter
TSP50C0x/1x Electrical Specifications
This chapter contains electrical timing information TSP50C0x/1x family devices, organized according device category.
Topic
Page
Absolute Maximum Ratings Over Operating Free-Air Temperature Range TSP50C0x/1x Recommended Operating Conditions TSP50C0x/1x Timing Requirements TSP50C10/11 Electrical Characteristics TSP50C12 Electrical Characteristics TSP50C04/06/13/14/19 Electrical Characteristics 3-10
Chapter Title-Attribute Reference
Absolute Maximum Ratings Over Operating Free-Air Temperature Range
Absolute Maximum Ratings Over Operating Free-Air Temperature Range
Supply voltage range, (see Note -0.3 Input voltage range, (see Note Output voltage range, (see Note Maximum Supply Current (IDD ISS) Operating free-air temperature range, 70°C Storage temperature range (TSP50C04/06/10/11/12/13/14) 30°C 125°C Storage temperature range (TSP50C19 only) 125°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage
device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTE voltages with respect ground.
Stresses beyond those listed here cause permanent damage device. This stress rating only.
Recommended Operating Conditions
Recommended Operating Conditions
following table contains recommended operating characteristics TSP50C0x/1x family.
Table 3-1. Recommended Operating Conditions
Supply voltage High-level input voltage Low-level input voltage Device functionality reference spec (TSP50C12 only) 10-kHz speech sample rate 8-kHz speech sample rate External mode interface TSP60C18 speech ROMs TSP50C04/06/13/14/19 direct speaker drive using push-pull option fosc 7.68 UNIT
fosc fclock Rspeaker
Operating free temperature free-air
Clock frequency clock frequency Minimum speaker impedance
Unless otherwise noted, voltages with respect VSS. Speech sample rate fosc 960.
TSP50C0x/1x Electrical Specifications
Timing Requirements
Timing Requirements
following tables give timing requirements following figures give timing waveforms TSP50C0x/1x family.
Table 3-2. Options Timing Requirements
Rise time, PAx, PBx, options Fall time, PAx, PBx, options Unit
Table 3-3. Initialization Timing Requirements
tINIT tsu(INIT) INIT pulsed while TSP50C0x/1x power applied Minimum delay INIT UNIT
Figure 3-1. Initialization Timing Diagram
INIT
tINIT
Table 3-4. Write Timing Requirements (Slave Mode)
tsu(PB1) tsu(d) th(PB1) th(d) Setup time, before goes Setup time, data valid before goes high Hold time, after goes high Hold time, data valid after goes high Pulse duration, Rise time, Fall time, UNIT
Figure 3-2. Write Timing Diagram (Slave Mode)
tsu(PB1) tsu(d) th(d) Data Valid th(PB1)
Timing Requirements
Table 3-5. Read Timing Requirements (Slave Mode)
tsu(PB1) th(PB1) tdis Setup time, before goes Hold time, after goes high Output disable time, data valid after goes high Pulse duration, Rise time, Fall time, Delay time data valid UNIT
Figure 3-3. Read Timing Diagram (Slave Mode)
tsu(PB1) Data Valid tdis th(PB1)
Table 3-6. External Interrupt Timing Requirements
tw(PB1) (PB1) Pulse duration before goes duration, fclock fclock UNIT
Figure 3-4. External Interrupt Timing Diagram
tw(PB1)
TSP50C0x/1x Electrical Specifications
TSP50C10/11 Electrical Characteristics
TSP50C10/11 Electrical Characteristics
Table gives specifications Figure gives input leakage current that applies TSP50C10 TSP50C11.
Table 3-7. TSP50C10/11 Electrical Characteristics Over Recommended Ranges Supply Voltage Operating Free-Air Temperature (unless otherwise noted)
PARAMETER IIkg Istandby Positive-going threshold voltage (INIT) Negative-going threshold voltage (INIT) Hysteresis (INIT) Input leakage current (except OSC1, INIT Figure 3-5) Standby current (INIT low) Supply current option High-level output current (PAx, PBx, options Low-level output current (PAx, PBx, options Pullup resistance 2.67 3.33 1.33 1.67 -7.5 TEST CONDITIONS 3.65 3.15 UNIT
Resistors selected with software connected between
Operating current assumes inputs tied either with input currents programmed pullup resistors. output other outputs open circuited.
TSP50C10/11 Electrical Characteristics
Figure 3-5. Typical Input Leakage Current INIT
Typical Input Leakage Current Init Input Voltage
Input Leakage Current (INIT)
Input Voltage (INIT)
TSP50C0x/1x Electrical Specifications
TSP50C12 Electrical Characteristics
TSP50C12 Electrical Characteristics
Table gives specifications that apply TSP50C12.
Table 3-8. TSP50C12 Electrical Characteristics Over Recommended Ranges Supply Voltage Operating Free-Air Temperature (unless otherwise noted)
PARAMETER Positive-going threshold voltage (INIT) Negative-going threshold voltage (INIT) Hysteresis (INIT) reference voltages temperature coefficient step IIkg Istandby Input leakage current (except OSC1, INIT Figure 3-5) Standby current (INIT low) Supply current option High-level output current (PAx, PBx, options Low-level output current (PAx, PBx, options 2.67 3.33 1.33 1.67 -7.5 40°C step control with respect -Vr, 25°C TEST CONDITIONS 3.717 register 1000 25°C, 25°C 1000, Figures 2.734 1.751 0.767 3.65 3.15 3.875 2.85 1.825 -2.5 4.033 2.966 1.899 0.833 mV/°C UNIT
This negative temperature coefficient normally advantageous because tracks temperature variation most materials. Operating current assumes inputs tied either with input currents programmed pullup resistors. output other outputs open circuited.
TSP50C12 Electrical Characteristics
Table 3-8. TSP50C12 Electrical Characteristics Over Recommended Ranges Supply Voltage Operating Free-Air Temperature(unless otherwise noted) (Continued)
PARAMETER Pullup resistance buffer drive (D/A option frame rate TEST CONDITIONS Resistors selected with software connected between load connected across DA2, fOSC UNIT
TSP50C0x/1x Electrical Specifications
TSP50C04/06/13/14/19 Electrical Characteristics
TSP50C04/06/13/14/19 Electrical Characteristics
Table gives specifications that apply TSP50C04, TSP50C06, TSP50C13, TSP50C14, TSP50C19.
Table 3-9. TSP50C04/06/13/14/19 Electrical Characteristics Over Recommended Ranges Supply Voltage Operating Free-Air Temperature (unless otherwise noted)
PARAMETER IIkg Istandby Positive-going Positive going threshold voltage (INIT) Negative-going Negative going threshold voltage (INIT) Hysteresis (INIT) Input leakage current (except OSC1, INIT Figure 3-5) Standby current (INIT low) Supply current option High-level output current options High-level High level output current (PAx, PBx) (PAx 2.67 3.33 2.67 3.33 -136 -136 -197 -7.5 TEST CONDITIONS 3.65 3.15 UNIT
Operating current assumes inputs tied either with input currents programmed pullup resistors. output other outputs open circuited.
3-10
TSP50C04/06/13/14/19 Electrical Characteristics
Table TSP50C04/06/13/14/19 Electrical Characteristics Over Recommended Ranges Supply Voltage Operating Free-Air Temperature (unless otherwise noted) (Continued)
PARAMETER TEST CONDITIONS Low-level output current options Low-level level output current (PAx, PBx) (PAx Pullup resistance 1.33 1.67 1.33 1.67 7.21 9.02 7.68 8.15 10.2 UNIT
Resistors selected with software connected between 7.68-MHz target frequency, 25°C 9.6-MHz target frequency, 25°C
fosc
Oscillator frequency
frequency internal clock temperature coefficient approximately coefficient typical 3%/V maximum =5.4%
TSP50C0x/1x Electrical Specifications
3-11
3-12
Running Title-Attribute Reference
Chapter
TSP50C0x/1x Assembler
TSP50C0x/1x assembler chapter describes invoke assembler, assembler command-line options, source-statement format, assembler symbols characters, assembler directives.
Topic
Page
Description Notation Used Invoking Assembler Command-Line Options Assembler Input Output Files Source-Statement Format Symbols 4-12 Character Strings 4-13 Expressions 4-14 Assembler Directives 4-15
Chapter Title-Attribute Reference
Description Notation Used
Description Notation Used
notation used this document follows:
optional field indicated brackets; example, [LABEL] User-supplied contents indicated braces; example, reserved keyword shown capital letters. required blank indicated caret (^).
following syntax example demonstrates notational conventions used this guide. name number comment
Invoking Assembler
Invoking Assembler
assembler invoked typing: ASM10 [<options>] <source[.ext]> where:
Options represents list assembler options (see Section 4.3, Command-Line Options). Source name source file with extension optional. extension given, then default extension .asm assumed. example:
ASM10 PROGRAM
runs assembler using source file program.asm generates output object file program.bin. list file generated.
TSP50C0x/1x Assembler
Command-Line Options
Command-Line Options
Several options invoked from command line (Table 4-1). They invoked listing their abbreviation prefixed minus sign. following example:
ASM10 PROGRAM.ASM
assembles program file program.asm does generate either listing file object file; however, errors written console. available options detailed Table 4-1. subsection 4.9.10, OPTION Directive, information invoking options from within source code.
Table 4-1. Switches Options
Character Number Action Lists only first data byte BYTE RBYTE Lists only first data byte DATA RDATA Counts number times valid instruction been used Displays error messages without generating list Disables object file output Prints listing without page breaks Produces reduced cross-reference list Writes errors screen unless listing file generated Lists only first data byte TEXT RTEXT Suppresses warning message Adds cross-reference list Generates object file TI-990 tagged object format
4.3.1
BYTE Unlist Option
Placing command-line option field causes assembler list only first opcode BYTE RBYTE statement. Normally, BYTE RBYTE statement arguments, they listed column running down page opcode column listing, taking lines completely list resulting opcodes. BYTE unlist switch set, then only first line (which also contains source line listing) written listing file.
Command-Line Options
4.3.2
DATA Unlist Option
Placing command-line option field causes assembler list only first opcode DATA RDATA statement. Normally, DATA RDATA statement arguments, they listed column running down page opcode column listing, taking lines completely list resulting opcodes. DATA unlist switch set, then only first line (which also contains source line listing) written listing file.
4.3.3
XREF Unlist Option
Placing command-line option field causes assembler cross-reference listing listing file.
4.3.4
TEXT Unlist Option
Placing command-line option field causes assembler list only first opcode TEXT RTEXT statement listing file. Normally, TEXT RTEXT statement argument string containing characters, ASCII representation these characters written column opcode column listing. TEXT unlist switch set, only first line (also containing source line listing) written list file.
4.3.5
WARNING Unlist Option
Placing command-line option field causes assembler suppress WARNING messages. Warnings still counted error messages still generated.
4.3.6
Complete XREF Switch
Placing command-line option field causes assembler produce reduced XREF listing produced. Normally, symbols (whether used not) listed XREF listing. option causes assembler omit from XREF listing symbols from copy files that were never used.
4.3.7
Object Module Switch
Placing command-line option field causes assembler generate object output modules.
4.3.8
Listing File Switch
Placing command-line option field causes assembler generate listing file display error messages screen.
TSP50C0x/1x Assembler
Command-Line Options
4.3.9
Page-Eject Disable Switch
Placing command-line option field causes assembler print listing continual manner without division into separate pages. When desired, form feed still forced using PAGE command.
4.3.10 Error-to-Screen Switch
Placing command-line option field causes assembler write errors screen unless listing file being generated.
4.3.11 Instruction Count Switch
Placing command-line option field causes assembler generate table containing number times each valid instruction used program.
4.3.12 Binary-Code File-Disable Switch
Placing command-line option field causes assembler generate object module tagged-object format file with .mpo extension instead normal binary formatted object module file with .bin extension.
Assembler Input Output Files
Assembler Input Output Files
assembler takes input file containing assembly source produces output listing file object file either binary format tagged object format.
4.4.1
Assembly Source File
assembly source file specified command line. filename command line extension, then file name used given. extension specified, then extension .asm assumed. example:
ASM10 PROGRAM.SRC
uses file program.src assembly source file.
ASM10 PROGRAM
uses file program.asm assembly source file.
4.4.2
Assembly Binary Object File
assembly process produces object file binary format default. object output placed file with same file name assembly source except that extension .bin. binary file desired, disabled either command-line option with OPTION statement. example:
ASM10 PROGRAM.SRC
uses file program.src assembly source file file program.bin binary object output file.
ASM10 PROGRAM.SRC
uses file program.src assembly source file produces object output.
TSP50C0x/1x Assembler
Assembler Input Output Files
4.4.3
Assembly Tagged Object File
desired, assembler substitute object file tagged object format instead object file binary format. produced, object output placed file with same file name assembly source except that extension .mpo. example:
ASM10 PROGRAM.SRC
uses file program.src assembly source file file program.mpo tagged object output file. binary-formatted object file produced.
4.4.4
Assembly Listing File
assembly process produces listing file that contains source instructions, assembled code, (optionally) cross-reference table. listing file placed file with same file name assembly source except that extension .lst. example:
ASM10 PROGRAM.SRC
uses file program.src assembly source file file program.lst assembly listing file.
Source-Statement Format
Source-Statement Format
assembly-language source program consists source statements contained assembly source file(s) that contain assembler directives, machine instructions, comments. Source statements contain four ordered fields separated more blanks. These fields (label, command, operand, comment) discussed following paragraphs. source statement long characters. form width characters (the default), assembler truncates source line characters. user should ensure that nothing other than comments extend past column source line starting with asterisk first character position treated comment entirety. ignored assembler effect assembly process. syntax source statements [<label>] COMMAND <operand> [<comment>] source statement have optional label that defined user. more blanks separate label from COMMAND mnemonic. more blanks separate mnemonic from operand required command). more blanks separate operand from comment field. Comments ignored assembler.
4.5.1
Label Field
label field begins character position source line. position character other than blank asterisk, assembler assumes that symbol label. label omitted, then first character position must blank. label contain characters consisting alphabetic characters numbers some other characters (@,$,_ first character should alphabetic character, remaining nine character positions legal characters listed above.
4.5.2
Command Field
command field begins after blank that terminates label field first nonblank character past first character position (which must blank when label omitted). command field terminated more blanks extend past sixtieth character position.
TSP50C0x/1x Assembler
Source-Statement Format
command field contain either assembler mnemonic (e.g., TAX) assembler directive (e.g., OPTION). assembler does distinguish between capital small letters command name; example, TAX, Tax, identical names assembler.
4.5.3
Operand Field
operand field begins following blank that terminates command field extend past sixtieth column position. operand contain more constants expressions described subsection 4.5.5, Constants, through subsection 4.5.10, Assembly-Time Constants. Terms operand field separated commas. operand field terminated first blank encountered.
4.5.4
Comment Field
comment field begins after blank that terminates operand field blank that terminates command field operand required. comment field extend source record contain ASCII character including blanks.
4.5.5
Constants
assembler recognizes following five types constants: Decimal integer constants Binary integer constants Hexadecimal integer constants Character constants Assembly-time constants
4.5.6
Decimal Integer Constants
decimal integer constant written string decimal digits. range values decimal integers -32,768 65,535. Positive decimal integer constants greater than 32,767 considered negative when interpreted two's complement values. following valid decimal constants: 1000 -32768 Constant equal 1000 03E8h Constant equal -32768 8000h Constant equal 0019h
4.5.7
Binary Integer Constants
binary integer constant written string binary digits (0/1) preceded question mark (?). less than digits specified, assembler right-justifies given bits resulting constant.
4-10
Source-Statement Format
following valid binary constants: ?0000000000010011 ?0111111111111111 ?11110 Constant equal 0013h Constant equal 32767 7FFFh Constant equal 001Eh
4.5.8
Hexadecimal Integer Constants
hexadecimal integer constant written string four hexadecimal digits preceded number sign greater than sign (>). less than four hexadecimal digits specified, assembler right-justifies bits that specified resulting constant. Hexadecimal digits include decimal values through letters through following valid hexadecimal constants: #07F >#07f #307A Constant equal 007Fh) Constant equal 007Fh) Constant equal 12410 307Ah)
4.5.9
Character Constants
character constant written string alphabetic characters enclosed single quotes. single quote represented within character constant successive quotes. less than characters specified, assembler right-justifies given bits resulting constant. characters represented internally 8-bit ASCII characters. character constant consisting only single quotes character) valid assigned value 0000h. following valid character constants: 'AB' '"D' Constant equal 4142h Constant equal 0043h Constant equal 2744h
4.5.10 Assembly-Time Constants
assembly-time constant symbol given value directive (see subsection 4.9.5, Directive value symbol determined assembly time assigned values with expressions using constant types.
TSP50C0x/1x Assembler
4-11
Symbols
Symbols
Symbols used label field operand field. symbol string fewer alphanumeric characters characters Uppercase lowercase characters distinguished from another; example, treated identically assembler. character blank. When more than characters used symbol, assembler prints characters issues warning message that symbol been truncated uses only first characters processing. Symbols used label field become symbolic addresses. They associated with locations program must used label field other statements. Mnemonic operation codes assembler directives also used valid user-defined symbols when placed label field. Symbols used operand field must defined assembly, usually appearing label field statement operand field directive. following examples valid symbols:
START Start strt_1
Predefined Symbol
dollar sign predefined symbol given value current location within program. used operand field indicate relative program offsets. example:
results branch address bytes beyond current location.
4-12
Character Strings
Character Strings
Several assembler directives require character strings operand field. character string written string characters enclosed single quotes. quote represented string successive quotes. maximum length string defined each directive that requires character string. characters represented internally 8-bit ASCII. following valid character strings:
'SAMPLE PROGRAM' 'Plan ''C'''
TSP50C0x/1x Assembler
4-13
Expressions
Expressions
Expressions used operand fields assembler instructions directives. expression constant symbol, series constants symbols, series constants symbols separated arithmetic operators. Each constant symbol preceded minus sign (unary minus) plus sign (unary plus). Unary minus same taking two's complement value. expression must contain embedded blanks. valid range values expression 32,768 65,535. value terms expression must known assembly time.
4.8.1
Arithmetic Operators Expressions
following arithmetic operators used expression: inversion addition subtraction multiplication division (remainder truncated) modulo (remainder after division) bitwise bitwise bitwise EXCLUSIVE-OR
evaluating expression, assembler first negates constant symbol preceded unary minus then performs arithmetic operations from left right. assembler does assign arithmetic operation precedence operation other than unary plus unary minus that expression evaluated 14).
4.8.2
Parentheses Expressions
assembler supports parentheses expressions alter order evaluating expression. Nesting parentheses within expressions also supported. When parentheses used, portion expression within innermost parentheses evaluated first, then portion expression within next innermost pair evaluated. When evaluation portions expression within parentheses been completed, evaluation completed from left right. Evaluation portions expression within parentheses same nesting level considered simultaneous. Parenthetical expressions nested more than eight deep.
4-14
Assembler Directives
Assembler Directives
Assembler directives (Table 4-2) instructions that modify assembler operation. They invoked placing directive mnemonic command field modifying operands operand field. valid directives described following paragraphs.
Table 4-2. Summary Assembler Directives
Directives That Affect Location Counter Mnemonic AORG Directive Absolute origin Syntax Directives That Affect Assembler Output LIST NARROW OPTION PAGE TITL WIDE Program identifier Restart source listing 80-column form width Output options Page eject Page title Stop source listing 130-column form width [<label>]^LIST^[<comment>] [<label>]^NARROW^[<comment>] [<label>]^OPTION^<option list>^[<comment>] [<label>]^PAGE^[<comment>] [<label>]^UNL^[<comment>] [<label>]^WIDE^[<comment>] Directives That Initialize Constants BYTE RBYTE DATA RDATA TEXT RTEXT Initialize byte Reverse initialization byte Initialize word Reverse initialization word Define assembly time Initialize text <expr-n>]^[<comment>] <expr-n>]^[<comment>] <expr-n>]^[<comment>] <expr-n>]^[<comment>]
Reverse byte initialization text Miscellaneous Directives
COPY
Copy source file Program
[<label>]^END^[<comment>]
TSP50C0x/1x Assembler
4-15
Assembler Directives
4.9.1
AORG Directive
AORG directive places value found expression operand field into location counter. Subsequent instructions have addresses starting this value. label field optional, when label used, assigned value found operand field. syntax AORG directive follows: [<label>] AORG <expression> [<comment>] following statement:
AORG #1000+Offset
Offset value sets location counter #1008. label included, also assigned value #1008. symbol Offset must previously defined.
4.9.2
BYTE Directive
BYTE directive places value more expressions into successive bytes program memory. range each term 255. command field contains BYTE. operand field contains series more terms separated commas terminated blank that represents values placed successive bytes program memory. syntax BYTE directive follows: [<label>] BYTE <expr_1>[,<expr_2>,.,<expr_n>] [<comment>] following statement:
BYTE #E0,5,data+5
places numbers 224, result arithmetic operation data into next three bytes program memory. value symbol data must defined assembly process.
4.9.3
COPY Directive
COPY directive causes assembler read source statements from different file. assembler gets subsequent statements from copy file until either end-of-file marker found directive found copy file. copy file cannot contain another COPY directive. command field contains COPY. operand field contains name file from which source files read.
4-16
Assembler Directives
syntax COPY directive follows: [<label>] COPY <filename> [<comment>] directive following example:
COPY copy.fil
causes assembler take source statements from file called copy.fil. end-of-file copy.fil when directive found copy.fil, assembler resumes processing source statements from original source file.
4.9.4
DATA Directive
DATA directive places value more expressions into successive words program memory. range each term 65,535. command field contains DATA. operand field contains series more terms separated commas terminated blank that represents values placed successive bytes program memory. syntax DATA directive follows: [<label>] DATA <expr_1>[,<expr_2>,.,<expr_n>]^ [<comment>] following example:
DATA #E000,'AB'
places following bytes into successive locations program memory: E0h, 00h, 41h, 42h.
4.9.5
Directive
directive assigns value symbol. label field contains name symbol which value assigned. command field contains EQU. operand field contains value assigned symbol. syntax directive follows: [<label>] <expression> [<comment>] following example:
Offset #100
assigns numeric value (100h) symbol Offset.
TSP50C0x/1x Assembler
4-17
Assembler Directives
4.9.6
Directive
directive signals source copy file. treated program end-of-file marker. found copy file, copy file closed subsequent statements taken from source file. found source file, assembly process terminates that point file. syntax directive follows: [<label>] [<comment>] following example:
ACAAC
ACAAC instruction assembled, subsequent instructions ignored.
4.9.7
Directive
directive assigns name object module produced. label field optional. When used, label assumes current value location counter. command field contains IDT. operand field contains module name <string>, character string eight characters within single quotes. When character string more than eight characters entered, assembler prints truncation warning message retains first eight characters program name. syntax directive follows: [<label>] '<string>' [<comment>] following example:
AORG 'Example'
assigns value symbol assigns name 'Example' module being assembled. module name then printed source listing operand directive appears page heading source listing. module name also placed object code tagged object format code being produced).
4-18
Assembler Directives
4.9.8
LIST Directive
LIST directive restores printing source listing. This directive required only when no-source-listing (UNL) directive effect causes assembler resume listing. This directive printed source listing, line counter increments. syntax LIST directive follows: [<label>] LIST [<comment>] following example:
AORG LIST Turn source listing
label assigned value listing resumed. line printed that although label entered into symbol table appears cross-reference listing, line which assigned value does appear listing file.
4.9.9
NARROW Directive
NARROW directive causes assembler assume 80-column form width listing file. default columns. (See subsection 4.9.18, WIDE Directive) syntax NARROW directive follows: [<label>] NARROW [<comment>] following example uses NARROW directive:
AORG NARROW Switch 80-column listing format
4.9.10 OPTION Directive
OPTION directive selects several options that affect assembler operation. <option-list> operand list keywords separated commas; each keyword selects assembly feature. Only first character keyword significant. label field optional. When used, label assumes current value location counter.
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Assembler Directives
syntax OPTION directive follows: [<label>] OPTION <option-list> [<comment>] following examples OPTION directive:
OPTION OPTION OPTION 990,XREF,SCRNOF 990,XREF,SCREEN 9,X,S
three examples above have identical effect. binary object file replaced object file tagged object format. cross-reference listing produced, error messages sent screen (unless source listing file being produced). Section 4.3, Command-Line Options, information invoking options from command line. available options listed following paragraphs.
BUNLST Byte Unlist Option
Placing valid symbol starting with option list enables byte unlist option. This option limits listing BYTE RBYTE directives line. Normally, BYTE RBYTE directive more than operand, resulting object code listed column opcode column source listing. directive operands, lines required source listing. BUNLST used avoid this.
DUNLST Data Unlist Option
Placing valid symbol starting with option list enables data unlist option. This option limits listing DATA RDATA directives line. Normally, DATA RDATA directive more than operand, resulting object code listed column opcode column source listing. directive operands, lines required source listing. DUNLST used avoid this.
FUNLST Byte, Data, Text Unlist Option
Placing valid symbol starting with option list limits listing BYTE, RBYTE, DATA, RDATA, TEXT, RTEXT directives line. effect, equivalent calling DUNLST, BUNLST, TUNLST directives same time.
COUNT Instruction Count List Option
Placing valid symbol starting with option list causes program generate table containing number times each valid instruction used program. used, should placed start program.
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Assembler Directives
LSTUNL Listing Unlist Option
Placing valid symbol starting with option list inhibits listing file from being produced. takes precedence over LIST directive.
OBJUNL Object File Unlist Option
Placing valid symbol starting with option list enables object file unlist option. This option inhibits either object output files from being produced.
PAGEOF Page Break Inhibit Option
Placing valid symbol starting with option list enables page break inhibit option. This option causes listing file printed continuous stream without page breaks.
RXREF Reduced XREF Option
Placing valid symbol starting with option list enables reduced XREF option. This option causes symbols that were found copy files never used omitted from cross-reference listing produced).
SCRNOF Screen Error Message Unlist Option
Placing valid symbol starting with option list enables screen error message unlist option. This option causes error messages listed screen unless listing file being produced.
TUNLST Text Unlist Option
Placing valid symbol starting with option list enables text unlist option. This option limits listing TEXT RTEXT directives line. TEXT RTEXT directive normally takes many lines list there characters operand. TUNLST causes only first line directive listing produced.
WARNOFF Warning Message Unlist Option
Placing valid symbol starting with option list inhibits listing warning diagnostics. Warnings still counted total still printed source listing.
XREF Cross-Reference Listing Enable
Placing valid symbol starting with option list causes cross-reference listing produced source listing. used, should placed start program.
TSP50C0x/1x Assembler
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Assembler Directives
Tagged Object Output Switch
Placing valid symbol starting with option list causes assembler omit binary coded object module (normally produced .bin file) produce tagged object module .mpo file) instead.
4.9.11 PAGE Directive
PAGE directive forces assembler continue source program listing page. PAGE directive printed source listing, line counter increments. label field optional. When used, label assumes current value location counter. command field contains PAGE. operand field used. syntax PAGE directive follows: [<label>] PAGE [<comment>] following example:
AORG PAGE Force Page Eject
label assigned value listing resumed next page. line printed out, that although label entered into symbol table appears cross-reference listing, line which assigned value does appear listing file.
4.9.12 RBYTE Directive
RBYTE directive places value more expressions into successive bytes program memory bit-reversed form. range each term 255. command field contains RBYTE. operand field contains series more terms separated commas terminated blank that represents values placed successive bytes program memory. syntax RBYTE directive follows: [<label>] RBYTE <expr_1>[,<expr_2>,.,<expr_n>] [<comment>] following example:
RBYTE #E0,5,data+5
Places numbers (07h), (A0h), bit-reversed result arithmetic operation (data successive bytes program memory. value symbol data must defined assembly process.
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Assembler Directives
4.9.13 RDATA Directive
RDATA directive places value more expressions into successive words program memory bit-reversed form. range each term 65,535. command field contains RDATA. operand field contains series more terms separated commas terminated blank that represents values placed successive words program memory. syntax RDATA directive follows: [<label>] RDATA <expr_1>[,<expr_2>,.,<expr_n>] [<comment>] following example:
RDATA #E000,'AB'
places following bytes into successive locations program memory: 00h, 07h, 42h, 82h.
4.9.14 RTEXT Directive
RTEXT directive writes ASCII string object file reverse order. string preceded minus sign, last character string written (which first character string given) written with most significant high. label field optional. When used, label assumes current value location counter. command field contains RTEXT. operand field contains character string characters long enclosed single quotes (optionally preceded minus sign). syntax RTEXT directive follows: [<label>] RTEXT [-]'<string>' [<comment>] following examples:
RTEXT -'This test' RTEXT 'This test'
both write string "tset sihT" output file. first example writes first word "This", which last character written with most significant high (that instead #54).
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Assembler Directives
4.9.15 TEXT Directive
TEXT directive writes ASCII string object file. string preceded minus sign, last character string written with most significant high. label field optional. When used, label assumes current value location counter. command field contains TEXT. operand field contains character string characters length enclosed single quotes (optionally preceded minus sign). syntax TEXT directive follows: [<label>] TEXT [-]'<string>' [<comment>] following examples:
TEXT -'This test' TEXT 'This test'
both write string "This test" output file. first example writes final word "test" with most significant high (that instead #74).
4.9.16 TITL Directive
TITL directive inserts title printed heading each page source listing. When title desired heading listing's page, TITL directive must first source statement submitted assembler. Unlike directive, TITL directive printed source listing. assembler does print comment because TITL directive printed, line counter does increment. label field optional. When used, label field assumes current value location counter. command field contains TITL. operand field contains title (string) character string characters length enclosed single quotes. When more that characters entered, assembler retains first characters title prints syntax error message. comment field optional. syntax TITL directive follows: [<label>] TITL '<string>' [<comment>] following example:
TITL 'Sample Program' This sample line
causes title, Sample Program, printed page heading source listing. When TITL directive first source statement program,
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Assembler Directives
title printed pages until another TITL directive processed. Otherwise, title printed next page after directive processed subsequent pages until another TITL directive processed. None this line printed listing file.
4.9.17 Directive
directive inhibits printing source listing output until occurrence LIST directive. printed source listing, source line counter incremented. label field optional. When used, label assumes value location counter. command field contains symbol UNL. operand field used. syntax directive follows: [<label>] [<comment>] following example:
AORG Turn source listing
assigns value label listing inhibited.
4.9.18 WIDE Directive
WIDE directive causes assembler assume 130-column form width listing file. default columns. (See subsection 4.9.9, NARROW Directive) syntax WIDE directive follows: [<label>] WIDE [<comment>] following example WIDE directive:
AORG WIDE Switch 130-column listing format
TSP50C0x/1x Assembler
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4-26
Running Title-Attribute Reference
Chapter
TSP50C0x/1x Instruction
This chapter describes different TSP50C0x/1x instructions (Table Table 5-2). Each instruction requires either instruction cycles execute. Each instruction cycle consists clock cycles; therefore, clock speed translates 600,000 instruction cycles second. When synthesis enabled, every other instruction cycle taken synthesis calculations, additional cycles used excitation function look This causes instruction cycle rate program drop 280,000 instruction cycles second.
Topic
Page
Instruction Syntax TSP50C0x/1x Assembly Instructions
Chapter Title-Attribute Reference
Instruction Syntax
Instruction Syntax
syntax source code instructions
[<label>]^<opcode mnemonic>^[<operand>]^ [<comment>]
fields are:
10-character optional label field 6-character opcode mnemonic field opcode-dependent operand field optional comment field
Each fields separated more tabs spaces.
TSP50C0x/1x Assembly Instructions
TSP50C0x/1x Assembly Instructions
following section contains descriptions, opcodes, source code (syntax), object code, execution results, status flag information, examples assembly instructions used program TSP50C0x/1x family. Table lists assembly instructions alphabetical order with operand size bits, instruction cycles requires, status conditions, number bytes required, opcode, description.
Table 5-1. TSP50C0x/1x Instruction
Operand Size (Bits) Instruction Cycles Required Status Always Set, Conditional, Does Apply) Number Bytes Required Opcode (Hex) Mnemonic ABAAC ACAAC AGEC AMAAC ANDCM ANEC AXCA AXMA AXBR CALL DECMN DECXN EXTSG Description register register constant register greater than equal constant memory register constant memory register equal constant register times constant register times memory register times timer Branch status Branch always address register Call status Clear register Clear register Clear register Decrement memory Decrement register Extended-sign mode bits
TSP50C0x/1x Instruction
TSP50C0x/1x Assembly Instructions
Table 5-1. TSP50C0x/1x Instruction (Continued)
Operand Size (Bits) Instruction Cycles Required Status Always Set, Conditional, Does Apply) Number Bytes Required Opcode (Hex) Mnemonic INCMC INTGR LUAA LUAB LUAPS ORCM RETI RETN SALA SALA4 SARA SBAAN SETOFF SMAAN TAMD TAMIX TAMODE TAPSC TASYN Description Increment register Increment register Increment memory integer mode Increment register Look register, result register Look register, result register Start parallel-to-serial transfer constant with memory Return from interrupt Return from subroutine Shift register left Shift register left bits Shift register right Subtract register from register Short branch status Turn processor Subtract memory from register Transfer register register Transfer register memory Transfer register memory direct Transfer register memory, increment register Transfer register mode register Transfer register prescale register Transfer register synthesizer register
TSP50C0x/1x Assembly Instructions
Table 5-1. TSP50C0x/1x Instruction (Continued)
Operand Size (Bits) Instruction Cycles Required Status Always Set, Conditional, Does Apply) Number Bytes Required Opcode (Hex) Mnemonic TATAX TMAD TMAIX TMXD TRNDA TSTCA TSTCM TTMA XGEC Description Transfer register timer register Transfer register register Transfer register memory Transfer constant register Transfer constant register Transfer memory register Transfer memory register direct Transfer memory register, increment register Transfer memory direct register Transfer random number register Test constant register Test constant memory Transfer timer register Transfer register register Exchange register register Exchange register register register greater than equal constant
TSP50C0x/1x Instruction
TSP50C0x/1x Assembly Instructions
Table lists instructions opcode.
Table 5-2. TSP50C0x/1x Instruction Table
CALL CALL CALL CALL CALL CALL CALL CALL CALL CALL CALL CALL CALL CALL CALL CALL TAMIX TMAIX SARA TTMA TAPSC SALA4 TASYN TAMODE TABRA DECXN INCMC DECMN AMAAC SMAAN TRNDA ABAAC SBAAN SALA AXAXMA INTGR EXTSG RETN RETI SETOFF ANEC XGEC AGEC ORCM ANDCM TSTCM TSTCA AXCA TMAD TAMD LUAA LUAPS LUAB TMXD ACAAC ACAAC ACAAC ACAAC ACAAC ACAAC ACAAC
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