Gsps 8-bit Converter JTS8388B Description JTS8388B monolithi

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Gsps 8-bit Converter JTS8388B Description JTS8388B monolithi

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8-bit Resolution Gsps (Min.) Sampling Rate Gain Adjust Full Power Input Bandwidth Gsps, MHz: SINAD (7.4 Effective Bits) SFDR Gsps, MHz: SINAD (7.2 Effective Bits) SFDR Gsps, 1000 Fs): SINAD (7.0 Effective Bits) SFDR Tone IMD: (489 MHz) Gsps Error Rate (10-13) Gsps Very Input Capacitance: (Die Form) mVpp Differential Single-ended Analog Inputs Differential Single-ended Compatible Clock Inputs LVDS/HSTL Output Compatibility Data Ready Output with Asynchronous Reset Gray Binary Selectable Output Data; Output Mode Power Consumption: Dual Power Supply: Radiation Tolerance Oriented Design (150 Krad (Si) Measured)
Gsps 8-bit Converter JTS8388B
Description
JTS8388B monolithic 8-bit analog-to-digital converter, designed digitizing wide bandwidth analog signals very high sampling rates Gsps. JTS8388B uses innovative architecture, including on-chip Sample Hold (S/H), manufactured with advanced high-speed bipolar process. on-chip features full power input bandwidth, providing excellent dynamic performance undersampling applications (High digitizing).
Applications
Digital Sampling Oscilloscopes Satellite Receiver Electronic Countermeasures/Electronic Warfare Direct Down-conversion
Screening
Standard Flow Mil-PRF-38535, Level Package Version Space Screening According ESA/SCC 9000
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Simplified Block Diagram
Figure Simplified Block Diagram
GAIN
Master/Slave Track Hold VIN, VINB Resistor Chain Analog Encoding Block Interpolation Stages
Regeneration Latches Error Correction Decode Logic CLKB Clock Buffer Output Latches Buffers DRRB GORB DATA, DATAB
Functional Description
JTS8388B 8-bit Gsps based advanced high-speed bipolar technology featuring cutoff frequency GHz. JTS8388B includes front-end master/slave Track Hold stage (Sample Hold), followed analog encoding stage interpolation circuitry. Successive banks latches regenerate analog residues into logical data before entering error correction circuitry resynchronisation stage followed differential output buffers. JTS8388B works fully differential mode from analog inputs digital outputs. JTS8388B features full power input bandwidth GHz. control GORB provided select either gray binary data output format. gain control provided order adjust gain. JTS8388B uses only vertical isolated transistors together with oxide-isolated polysilicon resistors, providing enhanced radiation tolerance (more than kRad total dose expected radiation).
JTS8388B
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JTS8388B
Specifications
Absolute Maximum Ratings
Parameter Positive supply voltage Digital negative supply voltage Digital positive supply voltage Negative supply voltage Maximum difference between negative supply voltages Analog input voltages Maximum difference between VINB Digital input voltage Digital output current Digital input voltage Digital output voltage Clock input voltage Maximum difference between VCLK VCLKB Maximum junction temperature Storage temperature Lead temperature (soldering Note: Symbol DVEE VPLUSD DVEE VINB VINB VCLK VCLKB VCLK VCLKB Tstg Tleads GORB Conditions: VOUT DRRB Comments Value -5.7 -0.3 -0.3 VPLUSD VPLUSD -0.5 Unit
Absolute maximum ratings limiting values, applied individually, while other parameters within specified operating conditions. Long exposure maximum ratings affect device reliability. thermal heat sink mandatory (MCM fixture).
Recommended Conditions
Parameter Positive supply voltage Symbol VPLUSD Positive digital supply voltage VPLUSD Negative supply voltages VEE, DVEE LVDS output compatibility -5.25 -5.0 -4.75 output compatibility Comments Min. 4.75 Typ. Max. 5.25 Unit
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Recommended Conditions (Continued)
Parameter Differential analog input voltage (full-scale) Clock input power level Symbol VIN, VINB VINB PCLK PCLKB Comments differential single-ended single-ended clock input Civil: grade Industrial: grade Military: grade Min. ±113 Typ. ±125 Max. ±137 Unit mVpp
Operating temperature range
Electrical Operating Characteristics
DVEE VINB mVpp full-scale differential input Digital outputs differentially terminated; (typical) 70°C. Full temperature range: -55°C 125°C
Parameter Resolution Analog Inputs Full-scale input voltage range (differential mode) common mode voltage) Full-scale input voltage range (single-ended input option) Analog input capacitance (die) Input bias current Input resistance Full power input bandwidth Small signal input bandwidth (10% full-scale) Clock Inputs Logic compatibility clock inputs clock inputs voltages (VCLK VCLKB) Logic voltage Logic voltage Logic current Logic current Clock input power level into termination Clock input power level Clock input capacitance (die) CCLK specified clock input power level Full Full Full Full -1.5 -1.1 into VINB VINB FPBW SSBW Full Full -125 -125 -250 Symbol Temp Test Level Min. Typ. Max. Unit bits
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Electrical Operating Characteristics (Continued)
DVEE VINB mVpp full-scale differential input Digital outputs differentially terminated; (typical) 70°C. Full temperature range: -55°C 125°C
Parameter Digital Outputs Logic compatibility digital outputs (depending value VPLUSD) Differential output voltage swings open transmission lines (ECL Levels) differentially terminated differentially terminated Output levels (assuming VPLUSD open transmission lines logic voltage logic voltage Output levels (assuming VPLUSD differentially terminated Logic voltage Logic voltage Output levels (assuming VPLUSD differentially terminated Logic voltage Logic voltage Power Requirements Positive supply voltage analog digital (ECL) digital (LVDS) analog digital VPLUSD IPLUSD analog digital AIEE DIEE PSRR Full Full -5.25 4.75 ±0.5 5.25 -4.75 mV/V 0.54 LVDS 1.620 0.825 0.660 Symbol Temp Test Level Min. Typ. Max. Unit
Full
25°C
-0.88
-1.62 -0.8
-1.54
25°C
-1.07
-1.41
-1.34
25°C
-1.2
-1.45 -1.15
-1.32
Positive supply current Negative supply voltage Negative supply current
Nominal power dissipation Power supply rejection ratio
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Electrical Operating Characteristics (Continued)
DVEE VINB mVpp full-scale differential input Digital outputs differentially terminated; (typical) 70°C. Full temperature range: -55°C 125°C
Parameter Accuracy Differential non-linearity (4)(5) Integral non-linearity (4)(5) missing codes Gain error Gain error drift Input offset voltage Transient Performance error rate (4)(6) Gsps settling time VinB mVpp Overvoltage recovery time Full 10-13 Error/ sample
Symbol
Temp
Test Level
Min.
Typ.
Max.
Unit
Full Full Full Full Full Full
0.35
Guaranteed over specified temperature range ppm/°C
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Electrical Operating Characteristics (Continued)
DVEE VINB mVpp full-scale differential input Digital outputs differentially terminated; (typical) 70°C. Full temperature range: -55°C 125°C
Parameter Performance Single-ended differential input mode, clock duty cycle (CLK, CLKB), binary output data format, 70°C, unless otherwise specified. Signal noise distortion ratio Gsps Gsps Gsps 1000 dBFs) Effective number bits Gsps Gsps Gsps 1000 dBFs) Signal noise ratio Gsps Gsps Gsps 1000 dBFs) Total harmonic distortion Gsps Gsps Gsps 1000 dBFs) Spurious free dynamic range Gsps Gsps Gsps 1000 dBFs) Gsps 1000 dBFs) tone intermodulation distortion FIN1 Gsps FIN2 Gsps
Symbol
Temp
Test Level
Min.
Typ.
Max.
Unit
SINAD
Full
Bits Bits Bits
ENOB
Full
Full
Full
SFDR
Full
Full
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Electrical Operating Characteristics (Continued)
DVEE VINB mVpp full-scale differential input Digital outputs differentially terminated; (typical) 70°C. Full temperature range: -55°C 125°C
Parameter Symbol Temp Test Level Min. Typ. Max. Unit
Switching Performance Characteristics Figures page Maximum clock frequency (binary output coding) Maximum clock frequency (Gray output coding) Minimum clock frequency Minimum clock pulse width (high) Minimum clock pulse width (low) Aperture delay
Jitter Full Full Full Full
0.285 0.350 0.500 0.500 1150 1110 1360 1320 Full
Gsps Gsps Msps
1660 1620 1000
(rms) Clock cycles
Aperture uncertainty (4)(7) Data output delay (3)(4)(9)(10) Output rise/fall time data (20% 80%)
TR/TF TR/TF TRDR TODTDR
Output rise/fall time data ready (20% 80%) Data ready output delay (4)(8)(9)(10) Data ready reset relay
(11)
timing diagram Gsps Data pipeline delay
Notes:
clock inputs indifferently entered differential single-ended mode, using levels typical power level into termination resistor in-phase clock input. into clock input correspond power level clock generator). Differential output buffers internally loaded resistors. Buffer bias current Specified loading conditions digital outputs: controlled impedance traces properly 50/75 terminated, unterminated controlled impedance traces. Controlled impedance traces far-end loaded standard ECLinPS register from Motorola® (e.g.: 10E452) (typical input parasitic capacitance including package protections). "Definitions Terms" page Histogram testing based sampling sinewave Msps Output error amplitude around worst code Maximum jitter value obtained single-ended clock input Gsps, 50/50 clock duty cycle, (TC1). -100 (typ) does depend sampling rate. Termination load parasitic capacitance derating values: controlled impedance traces properly terminated: additional ECLinPS load. Unterminated (source terminated) controlled impedance lines: additional ECLinPS termination load. Apply proper 50/75 impedance traces propagation time derating values: (155 ps/inch) TSEV8388B Evaluation Board. Values track each other over temperature percent variation degrees Celsius temperature variation). Therefore, variation over temperature negligible. Moreover, internal (on-chip) package skews between each Data effect considered negligible. Consequently, minimum values never more than apart. same true maximum values. "Applying JTS8388B" page
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Figure JTS8388B Timing Diagram Gsps Clock Rate) Data Ready Reset, Clock Held Level
(VIN, VINB)
TC=1000
(CLK, CLKB)
1360 TPD: Clock periods 3160
DIGITAL OUTPUTS
1000
DATA
DATA
1320
DATA
DATA
DATA
DATA
DATA
1320
TD1=TC1 -TOD TC1-40
DATA READY (DR, DRB)
TOD-TDR
TRDR=720
DRRB
(min)
Figure JTS8388B Timing Diagram Gsps Clock Rate) Data Ready Reset, Clock held HIGH Level
(VIN, VINB)
TC=1000
(CLK, CLKB)
1360
TPD: Clock periods
1360
DIGITAL OUTPUTS
1000
DATA
DATA
DATA
DATA
DATA
DATA
DATA
1320
1320
TD1=TC1 TDR-TOD
DATA READY (DR, DRB)
TRDR=720 TOD-TDR
DRRB
(min)
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Table Explanation Test Levels
Level Notes: Description 100% wafer tested C(2) 100% production tested C(2) (for packaged device) 100% production tested C(2), sample tested specified temperatures Sample tested only specified temperatures Parameter guaranteed design characterization testing (thermal steady-state conditions specified temperature) Parameter typical value only 100% production tested over specified temperature range Only min. max. values guaranteed (typical values issue from characterization results) Unless otherwise specified, tests pulsed tests: therefore
Table Wafer Screening
JTS8388B chip Parameter accuracy Mpsps/10 missing codes performance ENOB Note: C(1) Unless otherwise specified, tests pulsed tests: therefore Guaranteed C(1) Temperature Min. Max. Unit
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Functions Description
Name VPLUSD VIN, VINB CLK, CLKB <D0:D7> <D0B:D7B> GAIN GORB DIOD/DRRB Function Positive power supply Analog negative power supply Digital positive power supply Ground Differential analog inputs Differential clock inputs Differential output data port Differential data ready outputs Out-of-range outputs gain adjust Gray binary digital output select junction temp. measurement/ asynchronous data ready reset
VPLUSD (ECL) VPLUSD= (LVDS)
VINB CLKB GAIN GORB DIOD/ DRRB JTS8388B
DVEE= VEE=
Table Digital Coding (Non Return Zero) mode, ideal coding: does include gain, offset, linearity voltage errors.
Digital Output Differential Analog Input -124 -126 -249 -251 -251 Voltage Level Positive full-scale Positive full-scale Positive full-scale Positive scale Positive1/2 scale Bipolar zero Bipolar zero Negative scale Negative scale Negative full-scale Negative full-scale Negative full-scale Binary GORB floating 11111111 11111111 11111110 11000000 10111111 10000000 01111111 01000000 00111111 00000001 00000000 00000000 Gray GORB 10000000 10000000 10000001 10100000 11100000 11000000 01000000 01100000 00100000 00000001 00000000 00000000 Range
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Chip Description
Table JTS8388B Chip Functions Description
Symbol Number Function Analog ground Pads n°20, double Pads single bonding wires available analog ground access Digital positive supply compatibility, LVDS compatibility). double pads analog supply analog supply digital supply In-phase analog input signal differential Sample Hold preamplifier Inverted phase analog input signal In-phase clock input Inverted phase clock input In-phase digital outputs LSB. Inverted phase digital outputs. inverted LSB. inverted In-phase out-of-range output Out-of-range goes high leading edge code code Inverted phase out-of-range output In-phase output Data Ready signal Inverted phase output Data Ready signal Gray binary select output format control Binary output format GORB floating tied Gray output format GORB connected ground gain adjust DIOD: junction temperature measurement left floating grounded used DRRB: asynchronous data ready reset function
VPLUSD DVEE VINB CLKB D0B, D1B, D2B, D3B, D4B, D5B, D6B, GORB GAIN DIOD/DRRB
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Table JTS8388B Chip List, Coordinates Corresponding Functions
Number PosX -230 -390 -550 -710 -920 -1085 -1085 -1085 -1085 -1085 -1085 -1085 -1085 -1085 -1085 -1085 -1085 -905 -655 -455 -255 1085 1085 1085 PosY 1365 1365 1365 1365 1365 1365 1365 1365 1365 1365 1365 1115 -325 -595 -865 -1135 -1365 -1365 -1365 -1365 -1365 -1365 -1365 -1365 -1365 -1195 -995 -795 Chip Function VPLUSD DVEE VPLUSD GORB CLKB DIOD/DRRB Positive digital supply double
In-phase digital output, MSB: LSB: Inverted phase digital output, In-phase digital output, Inverted phase digital output, digital supply In-phase data ready Inverted Phase data ready In-phase digital output, Inverted phase digital output, Positive digital supply In-phase digital output, Inverted phase digital output, In-phase digital output, Inverted phase digital output, In-phase digital output, least significant Inverted phase digital output, least significant Gray binary data output format select supply Analog ground supply analog supply supply Analog ground In-phase clock input Analog ground Inverted phase clock input Analog ground analog supply supply analog supply double double double double double double double double double double double double
double
double
Diode input monitoring input asynchronous data ready reset Analog ground In-phase analog input Analog ground double
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Table JTS8388B Chip List, Coordinates Corresponding Functions (Continued)
Number Note: PosX 1085 1085 1085 1085 1085 1085 1085 1085 1085 1085 1085 PosY -595 -345 -145 1065 1225 Chip Function VINB GAIN Inverted phase analog input Analog ground gain adjust input supply supply In-phase out-of-range digital output Inverted phase out-of-range digital output In-phase digital output, most significant Inverted phase digital output, In-phase digital output, Inverted phase digital output, double double double
Coordinates relative centers. coordinates origin center die. dimensions given microns. pointed arrow Figure page Distance between (glass window) inner edge seaf-ring: size (inner edge seal-ring: (-1175, -1455) (1175, 1455). size (including scribe line): (-1230, -1510) (1230, 1510) (2.46 3.02 mm2). Actual size (after separation): (-1220, -1500) (1220, 1500) (2.44 3.00 mm). GORB tied floating: binary output data format. GORB tied GND: gray output data format. common mode level output buffers below positive digital supply. compatibility positive digital supply must (ground). LVDS compatibility (output common mode positive digital supply must subsequent LVDS circuitry withstand lower level input common mode, recommended lower positive digital supply level same proportion order spare power dissipation.
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Figure JTS8388B Chip Pads Designation size: 2.44 3.00 (after separation); area: 7.32
VPLUSD
DVEE
VPLUSD
GORB
GAIN
VINB
CLKB
DIOD/DRRB
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Table Mechanical Information
Mask Reference size size thickness Back side metallization Number layers Material Diffusion barrier Thickness Description Between scribe line axis After separation (single pad) (double pad) VH25B 2.46 3.02 2.44 3.00 None Ti/TiN Al-Si-Cu top) Ti/TiN Metal Metal Metal Ti/TiN Al-Si-Cu (Metal Ti/TiN Al-Si-Cu (Metal Oxide/Nitride (SiO2/SiN2): 4450 Epoxy filled high conductivity glue diameter CQFP68 (with restriction electrical performance)
Metallization
metallization(1)(2) Passivation Back side potential transistor count attach Bond wire Qualification package Notes:
layer etched step together with passivation layer. sandwich Metal Metal over field oxyde.
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Typical Characterization Results
Static Linearity
Msps; Figure Integral Non-linearity
Clock frequency Msps Positive peak: 0.78
Signal frequency Negative peak: -0.73
Figure Differential Non-linearity
Clock frequency Msps Positive peak:
Signal frequency Negative peak: -0.39
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Effective Number Bits Versus Power Supplies Variation
Figure Effective Number Bits (ENOB) (VEEA); Msps;
ENOB
-6.5
-6.0
-5.5 VEEA
-5.0
-4.5
-4.0
Figure Effective Number Bits (ENOB) (VCC); Msps;
ENOB
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Typical Results
Figure Gsps;
Figure Gsps;
Figure Gsps; MHz; Full-scale Input
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Spurious Free Dynamic Range Versus Input Amplitude
Sampling frequency Gsps; Input frequency MHz; Gray binary output coding Figure Reconstructed Signal Signal Spectrum Gsps, MHz, Full-scale
Full Scale
ENOB
SINAD 41.5
44.8
-44.4
SFDR
Figure Reconstructed Signal Signal Spectrum Gsps, MHz, Full-scale
Full Scale
ENOB
SINAD 41.5
44.8
-44.4
SFDR
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Dynamic Performance Versus Analog Input Frequency
Gsps; 1800 MHz; full-scale input (Fs); Clock duty cycle 50/50, binary/gray output coding, fully differential single-ended analog clock inputs Figure ENOB Versus Analog Input Frequency
ENOB (dB)
1000 1200 1400 1600 1800
Input Frequency (MHz)
Figure Versus Analog Input Frequency
(dB)
1000 1200 1400
1600
1800
Input Frequency (MHz)
Figure SFDR Versus Analog Input Frequency
SFDR (dBc)
1000 1200 1400
1600
1800
2000
Input Frequency (MHz)
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Figure ENOB Versus Sampling Frequency Analog input frequency: Nyquist conditions (Fin Fs/2) Clock duty cycle 50/50, binary output coding
Fs/2
(ENOB) Effective Number Bits
1000110012001300140015001600 Sampling Frequency (Msps
Figure SFDR Versus Sampling Frequency Analog input frequency: Nyquist conditions (Fin Fs/2) Clock duty cycle 50/50, binary output coding
SFDR
Fs/2
1000110012001300140015001600 Sampling Frequency (Msps)
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JTS8388B Performances Versus Junction Temperature
Figure ENOB Versus Junction Temperature
Effective number bits versus junction temperature Gsps Duty cycle
ENOB (bits)
Temperature
Figure Versus Junction Temperature
Signal noise ratio versus junction temperature Gsps differential clock, single-ended analog input (Vin -1dBFs)
(dB)
Temperature
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Figure Versus Junction Temperature
Total harmonic distorsion versus junction temperature Gsps differential clock, single-ended analog input (Vin -1dBFs)
(dB)
Temperature
Figure Power Consumption Versus Junction Temperature
Power consumption versus junction temperature Gsps Duty cycle
Power Consumption
Temperature
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Figure Typical Full Power Input Bandwidth Full Power Input)
1000
Frequency (MHz) 1200 1400 1600
1800
2000
2200
Magnitude (dB)
Step Response
Test pulse input characteristics: input full-scale rise time Figure Test Pulse Digitized with
mV/div ps/div
Time (ns)
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Figure Same Test Pulse Digitized with JTS8388B
Code
codes/div (Vpp ps/div
calculated rise time between
Time (ns)
Note:
Ripples test setup (they present both measurements)
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Jitter Performance
Sampling frequency Msps; Input frequency 1900 Figure Single-ended Analog Clock Inputs
Magnitude (dB)
-100
-120 Frequency (MHz)
Figure Single-ended Analog Clock Inputs
Total jitter (including test setup) jitter
Magnitude (code)
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Definitions Terms
Table Definitions Terms
Term Error Rate Full-power Input Bandwidth Differential Gain Description Probability exceed specified error threshold sample. error code code that differs more than from correct code analog input frequency which fundamental component digitally reconstructed output fallen with respect frequency value (determined analysis) input full-scale peak gain variation percent) five different levels signal fullscale peak peak amplitude. (TBC) differential non-linearity output code difference between measured step size code ideal step size. expressed LSBs. maximum value (i). error specification less than guarantees that there missing output codes that transfer function monotonic peak phase variation degrees) five different levels signal fullscale peak peak amplitude. (TBC) ASINAD 1.76 -V/2 ENOB -6.02 Where actual input amplitude full-scale range under test
Differential Nonlinearity
Differential Phase Effective Number Bits Inter Modulation Distortion Integral Non-linearity
ENOB
tones intermodulation distortion (IMD) rejection ratio either input tone worst third order intermodulation products. input tones levels full-scale integral non-linearity output code difference between measured input voltage which transition occurs ideal value this transition. expressed LSBs, maximum value sample sample variation aperture delay. voltage error jitter depends slew rate signal sampling point measured characterize ADC's performance response broad bandwidth signals. When using notch-filtered broadband white-noise generator input under test, Noise Power Ratio defined ratio average out-of-notch average in-notch power spectral density magnitudes spectrum output sample test. When input signal larger than upper bound input range, output code identical maximum code out-of-range logic one. When input signal smaller than lower bound input range, output code identical minimum code, out-of-range logic assumed that input signal amplitude remains within absolute maximum ratings) Time recover 0.2% accuracy output, after 150% full-scale step applied input reduced midscale PSRR ratio input offset variation change power supply voltage ratio expressed signal amplitude, below full-scale, value next highest spectral component (peak spurious spectral component). SFDR parameter selecting converter used frequency domain application (radar systems, digital receiver, network analyzer.). reported (i.e., degrades signal level lowered), dBFS (i.e. always related back converter full-scale)
JITTER
Aperture Uncertainty
Noise Power Ratio
(NRZ)
Return Zero
PSRR
Overvoltage Recovery Time Power Supply Rejection Ratio
SFDR
Spurious Free Dynamic Range
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Definitions Terms
Table Definitions Terms (Continued)
SINAD Signal Noise Distortion Ratio Signal Noise Ratio Aperture Delay Encoding Clock Period Time Delay from Data Data Ready Time Delay from Data Ready Data Fall Time Total Harmonic Distortion Digital Data Output Delay ratio expressed signal amplitude, below full-scale, other spectral components, including harmonics except ratio expressed signal amplitude, below full-scale, other spectral components excluding five first harmonics delay between rising edge differential clock inputs (CLK,CLKB) (zero crossing point), time which (VIN, VINB) sampled minimum clock pulse width (high) minimum clock pulse width (low) time difference between Data Data ready General expression with encoding clock period Time delay output data signals fall from delta between level high level ratio expressed first five harmonic components, value measured fundamental spectral component delay from falling edge differential clock inputs (CLK, CLKB) (zero crossing point) next point change differential output data (zero crossing) with specified load number clock cycles between sampling edge input data associated output data being made available (not taking account TOD). JTS8388B clock periods Time delay output data signals rise from delta between level high level Delay between falling edge Data Ready output asynchronous Reset signal (DDRB) reset digital zero transition Data Ready output signal (DR) Time delay achieve 0.2% accuracy converter output when full-scale step function applied differential analog input
Pipeline Delay
TRDR
Rise Time Data Ready Reset Delay Settling Time
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Applying JTS8388B
Timing Information
Timing Values JTS8388B Timing values given chip inputs/outputs, taking into account protection capacitance, diameter) bonding wire pad, specified termination loads. Propagation delays 50/75 impedance traces taken into account TDR. Apply proper derating values corresponding termination topology. min/max timing values valid over full temperature range following conditions: Specified termination load (differential output Data Data Ready): resistor parallel with standard ECLinPS register from Motorola® (e.g. 10E452). Typical ECLinPS inputs show typical input capacitance (including package protections). When addressing output DMUX, some digital outputs have same termination load, apply corresponding derating value given below. Output termination load derating values TDR: ps/pF additional ECLinPS load. Propagation time delay derating values also have applied TDR: ps/mm (155 ps/inch) TSEV8388B Evaluation Board. Apply proper time delay derating value different dielectric layer used.
Propagation Time Considerations
timing values given from include additional propagation times between pads input/output termination loads. TSEV8388B Chip Evaluation Board, propagation time delay ps/mm (155 ps/inch) corresponding GHz) dielectric constant RO4003 used board. different dielectric layer used (for instance teflon), appropriate propagation time values. does depend propagation times because differential data time difference between Data Ready output delay digital data output delay). also most straightforward data measure, again because differential: measured directly onto termination loads, with matched oscilloscope probes.
Variation Over Temperature
Values track each other over temperature percent variation degrees celsius temperature variation). Therefore, variation over temperature negligible. Moreover, internal (onchip) package skews between each data effect considered negligible. Consequently, minimum values never more than apart. same true maximum values. other words: will 1420 (maximum time delay TDR) 1460 will (minimum time delay TDR) However, external values dictated total digital data skews between each (each digital data) TDR: board, bonding wires differences output line lengths, mismatches output termination impedance.
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external board) skew effect been taken into account specification minimum maximum values TOD-TDR. Principle Operation analog input sampled rising edge external clock input (CLK,CLKB) after (aperture delay) typically digitized data available after clock periods latency (pipeline delay (TPD)), clock's rising edge, after 1160 typical propagation delay TOD. Data Ready differential output signal frequency (DR, DRB) half external clock frequency, that switches same rate digital outputs. Data Ready output signal (DR, DRB) switches external clock's falling edge after propagation delay typically 1120 Master Asynchronous Reset input command DRRB (ECL-compatible single-ended input) available initializing differential Data Ready output signal (DR, DRB). This feature mandatory certain applications using interleaved ADCs using single with demultiplexed outputs. Without Data Ready signal initialization, impossible store output digital data defined order.
Principle Data Ready Signal Control DRRB Input Command
Data Ready Output Signal Reset Data Ready signal reset falling edge DRRB input command, logical level (-1.8 DRRB also tied Data Ready output signal Master Reset. long DRRB remains logical level, tied Data Ready output remains logical zero independent external free-running encoding clock. Data Ready output signal (DR, DRB) reset logical zero after TRDR typical. TRDR measured between -1.3 point falling edge DRRB input command zero crossing point differential Data Ready output signal (DR, DRB). Data Ready Reset command pulse minimum time width. Data Ready Output Signal Restart Data Ready output signal restarts DRRB command's rising edge, logical high levels (-0.8 DRRB also grounded, allowed float, normal free-running Data Ready output signal. Data Ready signal restart sequence depends logical level external encoding clock, DRRB rising edge instant. DRRB rising edge occurs when external encoding clock input (CLK,CLKB) LOW: Data Ready output's first rising edge occurs after half clock period clock falling edge, after delay time 1120 already defined above. DRRB rising edge occurs when external encoding clock input (CLK,CLKB) HIGH:
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Data Ready output's first rising edge occurs after clock period clock falling edge, delay 1120 Consequently, analog input sampled clock's rising edge, first digitized data corresponding first acquisition after Data Ready signal restart (rising edge) always strobed third rising edge Data Ready signal. time delay (TD1) specified between last point change differential output data (zero crossing point) rising falling edge differential Data Ready signal (DR, DRB) (zero crossing point). normal initialization Data Ready output signal, external encoding clock signal frequency level must controlled. minimum encoding clock sampling rate Msps consequently clock cannot stopped. single used both DRRB input command junction temperature monitoring. denomination will DRRB/DIOD former version denomination DIOD). Temperature monitoring Data Ready control DRRB possible simultaneously.
Analog Inputs (VIN) (VINB)
analog input full-scale range (Vpp), into termination resistor. differential mode input configuration, that means 0.25 each input, ±125 around input common mode ground. typical input capacitance form (JTS8388B), taking into account bond wires capacitance. input capacitance mainly capacitance, protections connected (but present) inputs. Figure Differential Inputs Voltage Span
[mV] Full-scale Analog Input VINB
-250
-125 (VIN, VINB) ±250 diff
Differential Versus SingleThe JTS8388B operate full speed without performance degradation either ended Analog Input Operation differential single-ended configuration. This explained fact that uses high-input impedance differential preamplifier stage, (preceding Sample Hold stage), which been designed order entered either differential single-ended mode. This true long out-of-phase analog input VINB terminated very closely neighboring shield ground pads (33, 37), which constitute local ground reference in-phase analog input (VIN).
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JTS8388B
Thus, differential analog input preamplifier will fully reject local ground noise (and capacitively inductively coupled noise) common mode effects. typical single-ended configuration, enter (VIN) input pad, with inverted phase input (VINB) grounded through termination resistor. single-ended input configuration, in-phase input amplitude centered into inverted phase input ground potential through termination resistor. Figure Typical Single Ended Analog Input Configuration
[mV] Full-scale Analog Input VINB ±250 diff Reverse Termination VINB double (pins VINB
VINB
package)
-250
Clock Inputs (CLK) (CLKB)
JTS8388B clocked full speed without noticeable performance degradation either differential single-ended configuration. This explained fact uses differential preamplifier stage clock buffer, which been designed entered either differential single-ended mode.
Single-ended Clock Input (Ground Common Mode)
Although clock inputs were intended driven differentially with nominal -0.8 V/-1.8 levels, JTS8388B clock buffer manage single-ended sinewave clock signal centered around This most convenient clock input configuration does require power splitter. performance degradation (e.g. timing jitters) observed this particular single-ended configuration Gsps Nyquist conditions (Fin MHz). This true long inverted phase clock input terminated very closely neighboring shield ground pads, which constitutes local ground reference in-phase clock input. Thus, JTS8388B differential clock input buffer will fully reject local ground noise (and capacitively inductively coupled noise) common mode effects. Moreover, very low-phase noise sinewave generator must used enhanced jitter performance. typical in-phase clock input amplitude centered (ground) common mode. This corresponds typical clock input power level into termination resistor. exceed avoid saturation preamplifier input transistors. inverted phase clock input grounded through termination resistor.
2104A-BDC-09/03
Figure Single-ended Clock Input (Ground Common Mode) VLCLK common mode VCLKB typical clock input power level (into termination resistor
VCLK CLKB double (pins CLKB
VCLK VCLK -0.5
package)
reverse termination
Note:
exceed into termination resistor single clock input power level.
Differential Clock Input
clock inputs driven differentially with nominal -0.8 V/-1.8 levels. this mode, low-phase noise sinewave generator used drive clock inputs, followed power splitter (hybrid junction) order obtain degrees outof-phase sinewave signals. Biasing tees used offsetting common mode voltage levels.
Note: biasing tees propagation times matching, tunable delay line required order ensure signals degrees out-of-phase especially fast clock rates Gsps range.
Figure Differential Clock Inputs (ECL Levels)
[mV] -0.8 VCLK VCLKB
CLKB double (pins CLKB
Common mode -1.3
package)
-1.8
reverse termination
JTS8388B
2104A-BDC-09/03
JTS8388B
Single Ended Clock Input
single-ended configuration enter (resp. CLKB) pad, with inverted phase clock input CLKB (respectively CLK) connected -1.3 through termination resistor. in-phase input amplitude centered -1.3 common mode. Figure Single-ended Clock Input (ECL)
-0.8 VCLK
VCLKB -1.3
-1.8
VCLK common mode -1.3 VCLKB -1.3
Clock Signal Duty Cycle Adjust
fast sampling rates, Gsps above), device performance (especially SNR) improved tuning clock duty cycle (CLK, CLKB). single-ended configuration, when using sinewave clock generator, clock signal duty cycle easily adjusted simply offsetting in-phase clock signal using biasing tee, phase clock input ground level). Figure Single-ended Clock Input (In-phase Clock Input Common Mode Shifted)
VCLK VCLKB
-0.5
VCLK common mode -180 VCLKB Note: exceed into termination resistor single clock input power
level. input signal into typical offset value achieve 40/60 clock duty cycle -180 CLK.
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Noise Immunity Information
Circuit noise immunity performance begins design level. Efforts have been made design make device insensitive possible chip environment perturbations resulting from circuit itself induced external circuitry (cascade stages isolation, internal damping resistors, clamps, internal (on-chip) decoupling capacitors). Furthermore, fully differential operation from analog input digital output provides enhanced noise immunity common mode noise rejection. Common mode noise voltage induced differential analog clock inputs will canceled these balanced differential amplifiers. Moreover, proper active signals shielding been provided chip reduce amount coupled noise active inputs: analog inputs clock inputs TS8388B chip have been surrounded ground pads, which must directly connected external ground plane.
Digital Outputs
JTS8388B differential output buffers internally loaded. resistors connected digital ground pads through -0.8 level shift diode (see Figures page Figure page 39). JTS8388B output buffers designed driving (default) properly terminated impedance lines coaxial cables. bias current flowing alternately into resistors when switching, ensures 0.825 voltage drop across resistor (unterminated outputs). VPLUSD positive supply voltage allows adjustment output common mode level from -1.2 (VPLUSD output compatibility) (VPLUSD LVDS output compatibility). Therefore, single-ended output voltages vary approximately between -0.8 -1.625 (outputs unterminated), around -1.2 common mode voltage. Three possible line driving back termination scenarios proposed (assuming VPLUSD impedance transmission lines, differentially terminated (Figure 34): each output voltage varies between -1.42 (respectively leading ±0.41 0.825 differential, around -1.21 (respectively 1.21 common mode VPLUSD (respectively impedance transmission lines, differentially termination (Figure 35): each output voltage varies between -1.02 -1.35 (respectively 1.38 1.05 leading ±0.33 differential, around -1.18 (respectively 1.21 common mode VPLUSD (respectively impedance open transmission lines (Figure 36): each output voltage varies between -1.6 -0.8 (respectively which true levels, leading ±0.8 differential, around -1.2 (respectively common mode VPLUSD (respectively Therefore, possible drive high input impedance storing registers directly, without terminating transmission lines. time domain, this means incident wave will reflect transmission line output travel back generator (i.e. data output buffer). buffer output impedance back reflection will occur. Note: This longer true transmission line used, latter matching buffer output impedance.
JTS8388B
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JTS8388B
Each differential output termination length must kept identical. recommended decouple midpoint differential termination with capacitor avoid common mode perturbation case slight mismatch differential output line lengths. large mismatches (keep differential line lengths will lead switching currents flowing into decoupling capacitor, turn leading switching ground noise. differential output voltage levels termination) standard voltage levels. However, possible drive standard logic circuitry like ECLinPS logic line from Motorola®. sampling rates exceeding Gsps, difficult trigger HP16500 other acquisition system with digital outputs. becomes necessary regenerate digital data Data Ready means external amplifiers, order able test JTS8388B optimum performance conditions.
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Differential Output Loading Configurations
(levels compatibility) Figure Differential Output: Terminated
VPLUSD -0.8 impedance V/-1.41
Differential output: 0.41 0.825 Common mode level: -1.2 (-1.2 below VPLUSD level)
OutB DVEE
-1.41 V/-1
Figure Differential Output: Terminated
VPLUSD -0.8 impedance -1.02 V/-1.35
Differential output: 0.33 0.660 Common mode level: -1.2 (-1.2 below VPLUSD level)
OutB DVEE
-1.35 V/-1.02
JTS8388B
2104A-BDC-09/03
JTS8388B
Figure Differential Output: Open Loaded
VPLUSD -0.8 impedance -0.8 V/-1.6
Differential output: Common mode level: -1.2 (-1.2 below VPLUSD level)
OutB DVEE
-1.6 V/-0.8
2104A-BDC-09/03
Differential Output Loading Configurations
(levels LVDS compatibility) Figure Differential Output: Terminated
VPLUSD impedance V/0.99
Differential output: 0.41 0.825 Common mode level: -1.2 (-1.2 below VPLUSD level)
OutB DVEE
0.99 V/1.4
Figure Differential Output: Terminated
VPLUSD impedance 1.38 V/1.05
Differential output: 0.33 0.660 Common mode level: -1.2 (-1.2 below VPLUSD level)
OutB DVEE
1.05 V/1.38
JTS8388B
2104A-BDC-09/03
JTS8388B
Figure Differential Output: Open Loaded
VPLUSD impedance V/0.8
Differential output: Common mode level: -1.2 (-1.2 below VPLUSD level)
OutB DVEE
V/1.6
Out-of-range
out-of-range (OR, ORB) provided that reaches logical high state when input exceeds positive full-scale falls below negative full-scale. When analog input exceeds positive full-scale, digital outputs remain logical high state with logical When analog input falls below negative full-scale, digital outputs remain logical state with logical again.
Gray Binary Output Data Format Select
JTS8388B internal regeneration latches indecision (for inputs very close latches' threshold) produce errors logic encoding circuitry lead large amplitude output errors. This fact that latches regenerate internal analog residues into logical states with finite voltage gain value (Av) within given positive amount time (t): exp((t)/), with positive feedback regeneration time constant. JTS8388B been designed reducing probability occurrence such errors approximately 10-13 (targeted JTS8388B Gsps). standard technique reducing amplitude such errors down consists setting digital output data gray code format. Though JTS8388B been designed feature Error Rate 10-13 with binary output format, possible user choose between binary gray output data format, order reduce amplitude such errors when they occur, storing gray output codes. Digital data format selection: Binary output format GORB floating Gray output format GORB connected ground
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JTS8388B Thermal Requirements
JTS8388B currently mounted dedicated Chip Evaluation Board (CEB), which fulfills device's thermal requirements still room temperature. operation military temperature range, forced convection required maintain device junction temperature below specified maximum value. JTS8388B's power dissipation 70°C junction temperature, 125°C junction temperature. dimensions 2.44 7.32 mm2. maximum junction temperature 145°C. correctly manage power dissipation JTS8388B device, following thermal fixture profile used, taking into account dimensions power dissipation: 7.5°C/W typical value attach filled Epoxy glue, depending glue film thickness 0.5°C/W Copper block 1°C/W isolation foil 6.5°C/W heatsink (still air)
heatsink used 3334B heatsink from Thermalloy (also used cooling Power µP). dimensions 50.70 50.39 16.51 (1.996 1.984 0.650 measured junction ambient thermal resistance (RTHJA) Chip Evaluation Board approximately 15.5°C/W still air. room temperature (25°C), this yields device junction temperature approximately 80°C, thermal steady-state conditions.
JTS8388B
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JTS8388B
Diode
DIODE provided junction temperature monitoring. operating junction temperature must kept below 145°C, therefore adequate cooling system diode mounted transistor measured value versus junction temperature given below: Figure Diode
1000
(mV)
Junction Temperature (°C)
Gain Control gain adjustable means (input impedance parallel
with pF). gain adjust transfer function given below: Figure Gain Control
1.20 1.15 1.10 Gain 1.05 1.00 0.95 0.90 0.85 0.80 -500
-400
-300
-200
-100
Vgain (command voltage) (mV)
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Equivalent Input Output Schematics
Figure Equivalent Analog Input Circuit Protections
VCLAMP
-0.8 -0.8
-5.8 -5.8
1.65
VINB
capacitance
capacitance
-1.55
E21G
E21G
Note:
protections present connected Vinb.
Figure Equivalent Analog Clock Input Circuit Protections
-5.8 -0.8
-5.8
-5.8
-5.8 -5.8 E31V
capacitance
E31V
CLKB
capacitance
E21G
E21G
Note:
protections present connected Clkb.
JTS8388B
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JTS8388B
Figure Equivalent Data Output Buffer Circuit Protections
VPLUSD
-5.8
-5.8
E01V
E01V
OUTB
capacitance
capacitance
DVEE
Figure Gain Adjust Equivalent Input Circuits Protections
-0.8
NP1032C2
-5.8
E22V
capacitance
E22GA
2104A-BDC-09/03
Figure GORB Equivalent Input Schematic Protections
-0.8 -0.8 -5.8
E21VA
GORB
capacitance
E31G
GORB: gray binary select input; floating tied binary Figure DRRB Equivalent Input Schematic Protections
NP1032C2 -1.3 capacitance
DRRB
-2.6
E21G
Actual protection range: above VEE, fact stresses above clipped diode used monitoring
JTS8388B
2104A-BDC-09/03
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Gsps 8-bit Converter JTS8388B Description JTS8388B monolithi

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