Cores (3), Giving MIPS Maximum Processing Power with SYSCLK Includes S
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Servo Processing Unit (SPU), Using Dedicated 16-bit Instruction Cycle AVR® RISC
Cores (3), Giving MIPS Maximum Processing Power with SYSCLK Includes Single-clock Cycle On-chip Debugger Monitor Program Development (OCDM) Words Program Bytes Data On-chip Clock Frequency Synthesizer with Output Clock Buffers AT78C1501 Controller On-chip Timing State Machine (TSM) Conversion Focus, Tracking Signals 10-bit µsec with six-channel Synchronized Conversions with Interrupt Service Routine Three Fast 10-bit nsec (rise time) DACs Servo Loops Adjustments Three 8-bit DACs Offset Adjustment Spin Loop Bandgap Midpoint Reference Outputs Implemented Spindle Speed Control Spindle Interface Logic Hardware Support Both Spindle Control Modes Eight General Purpose Pins Servo Control Focus, Fine Track, Coarse Track Tray Load Motors High-speed Track Counter Accurate High-speed Track Counts (1.4 when used with AT78C1503 Read Channel) Lower Power Operations with 3.3V Core Tolerant I/Os 8-bit Data 14-bit Address Controller/Microprocessor Interface 3-pin Universal Serial Port Interface Program Read Channel Power Devices Power Management On-chip UART Access OCDM Unit
DVD/CD Servo AT78C1502
Description
Atmel AT78C1502 high-performance servo controller fully integrates control demodulation functions optical/mechanical systems. Packaged 128-lead TQFP fabricated 0.35 micron CMOS, device operates 3.3V logic/analog supply provides tolerance digital I/O. AVRbased Servo Processing Unit (SPU) embedded device provides programmable control spindle speed, coarse fine tracking, focus, sled, draw motor tilt. three parallel programmable microcontrollers heart system, offering range servo sample rates. With only system clock, MIPS processing power provided. Real-time notch filters also calculated. Fast 10-bit DACs provide real-time control servo loops other system adjustments. universal serial port many general purpose I/Os provided. AVR0 master three microcontrolloers, communicating with AVR1, AVR2 ARMTDMI AT78C1501 interface controller AT78C1503 read channel. On-Chip Debugger Monitor (OCDM) offered enable programmers easily observe theeffect changes code each AVR. System-level evaluation boards available with development code both native code basic operation servos. Simple changes code allow mechadeck interfaced AT78C1502.
Rev. 2050A-DVD-07/02
Figure System Block Diagram
DRAM
Flash
AT78C1502 Servo Control System
Power Drivers
Sled
AT78C1501 ATAPI Controller SRAM ARM7TDMI
Focus
Spindle
AT78C1503 Read Channel
Laser
AT78C1504 Laser Power Controller
T08XX Laser
AT78C1507 Read Channel Adj.
AT78C1505 Pre-amp
AT78C1502
2050A-DVD-07/02
AT78C1502
Figure Pin-out
DGND DVDD DGND CINT CINTAQK TESTMODE DVDD OCDM DGND MRST JTRIG DVDD MIRR HD1,2 DGND
DGND DVDD DGND XOUT CLK2 CLK1 DVDD FSFILT FSIS DGND
AT78C1502 128-lead TQFP
DGND GPP7 GPP6 GPP5 GPP4 GPP3 GPP2 GPP1 GPP0 DVDD SPCLK BEMF SCLK SDATA SDEN2 SDEN1 SDEN0 DGND AGND FDAC FDACREF FINDAC FINDACREF AVDD CRSDAC CRSDACREF DAC1 DAC0 AVDD 2VBG AGND
DGND HD3,4 CNTRST SINT ADCSTR AVDD MUXOUT AIN6 AIN5 MTRK MTRKFB AGND LPSFB FCSFB AVDD SUMFB RDSZ RDSZFB ADCREF AGND
2050A-DVD-07/02
External Definition
Power ground, Bidirectional, Digital Input, Digital Output. Analog Input, Analog Output. Table External Definition
Symbol DGND DVDD DGND CINT CINTACK TMODE DVDD OCDM_ENAB TM4/MUX4 TM3/MUX3 TM2/MUX2 TM1/MUX1 TM0/MUX0 DGND MRST JTRIG DVDD Type Description Digital Ground Data Data Data Data Digital Data Data Data Data Digital Ground Chip Write Select Chip Read Select Chip Select Input Interrupt Input from Controller Controller Interrupt Acknowledge Test Mode Select Input Active-low Digital On-chip Debug/Monitor Mode Test Mode Select Test Mode Select Input/MUX Output Test Mode Select Input/MUX Output Test Mode Select Input/MUX Output Test Mode Select Input/MUX Output Digital Ground Master Reset Input Write Gate Input from Controller Field Input from Controller Jump Trigger Input from Controller Laser High Power Input from Controller Digital Power Track Input from Read Channel Burst Cutting Area (Defect Flag Input)
AT78C1502
2050A-DVD-07/02
AT78C1502
Table External Definition (Continued)
Symbol MIRR HD1,2 DGND DGND HD3,4 CNTRST SINT ADCSTR AVDD MUX_OUT AIN6 AIN5 MTRK MTRKFB AGND FCSF AVDD SUMF RDSZ RDSZF ADCREF AGND AGND 2VBG AVDD Type Description Track Zero Crossing from Read Channel Mirror Input from Read Channel Focus Signal from Read Channel Header Input from Read Channel Digital Ground Digital Ground Header Input from Read Channel Counter Reset Signal Servo Interrupt Output Controller Servo Fault Output Controller Strobe Output from Analog Analog Output Analog Input Analog Input MUXed Track Track/Hold Input MUXed Track Filter Input Analog Ground Lens Position Sensor Track/Hold Input Lens Position Sensor Filter Input Focus Error Signal Track/Hold Input Focus Error Signal Filter Input Analog Slow Track/Hold Input Slow Input Filter Read Size Input Read Size Input Filter Connect Connect Reference Analog Analog Connect Bandgap Output Voltage 2*Bandgap Output Voltage Analog
2050A-DVD-07/02
Table External Definition (Continued)
Symbol DAC0 DAC1 CRSDAC CRSDACREF AVDD FINDAC FINDACREF FDAC FDACREF AGND DGND SDEN0 SDEN1 SDEN2 SDATA SCLK BEMF SPCLK DVDD GPP0 GPP1 GPP2 GPP3 GPP4 GPP5 GPP6 GPP7 DGND DGND FSIS FSFILT Type Description Connect 8-bit Offset Output 8-bit Offset Output 10-bit Coarse Tracking Coarse Input Analog 10-bit Fine Tracking Fine Input 10-bit Focus Focus Input Analog Digital Serial Data Enable Serial Data Enable Serial Data Enable Serial Data Serial UART Receive Data Input UART Transmit Data Output Back Zero Crossing Input Spin Pseudo Register Output Digital General Purpose Port General Purpose Port General Purpose Port General Purpose Port General Purpose Port General Purpose Port General Purpose Port General Purpose Port External Event Capture Connect Digital Ground Digital Ground Frequency Synthesizer Iset Frequency Synthesizer Filter
AT78C1502
2050A-DVD-07/02
AT78C1502
Table External Definition (Continued)
Symbol DVDD CLK1 CLK2 XOUT DGND DVDD DGND Type Description Connect Digital Clock Output Clock Output Crystal Connection Crystal Input/Clock Input Digital Ground Address Input Address Input Address Input Address Input Address Input Digital Address Input Address Input Address Input Address Input Address Input Address Input Address Input Address Input Address Input Digital
2050A-DVD-07/02
Figure Block Diagram
(13:0) (7:0) Controller Interface (CIF)
Program Space Data Space Dual-Port
UART
Serial Interface Port (SIP)
SDENA2 SDENA1 SDENA0 SDATA SCLK
CINT CINTACK SINT ADCREF MUXOUT
Interrupt Control Logic (ICL)
Servo Processing Unit (SPU)
General Purpose Port (GPP)
Output Block (DOB)
(7:0)
CRSDAC FINDAC FDAC DAC1 DAC0 CNTRST JTRIG HD1,2 HD3,4
MTRK RDSZ AIN4 AIN5 Track Hold Filter (THF) Timing State Machine (TSM)
(MAD)
Servo Input Block (SIB)
Band
Frequency Synthesizer (FQS)
Clock Distribution (COD)
Track Counter (TRCNT)
MIRR
Spindle Control Logic (SCL)
SPCLK BEMF
2.5V
1.25V
ISET
FILT
AT78C1502
2050A-DVD-07/02
CLK1 CLK2 XOUT
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2050A-DVD-07/02
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