Maximum Standby Maximum Active JEDEC Standard Packages 40-Lead PDIP 44
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Fast Read Access Time Power CMOS Operation
Maximum Standby Maximum Active JEDEC Standard Packages 40-Lead PDIP 44-Lead PLCC 40-Lead VSOP Direct Upgrade from 512K-bit, 1M-bit, 2M-bit (AT27C516, AT27C1024, AT27C2048) EPROMs Power Supply High Reliability CMOS Technology 2,000V Protection Latchup Immunity RapidProgramming Algorithm µs/word (typical) CMOS Compatible Inputs Outputs Integrated Product Identification Code Commercial Industrial Temperature Ranges
4-Megabit (256K EPROM AT27C4096
Description
AT27C4096 low-power, high-performance 4,194,304-bit one-time programmable read only memory (OTP EPROM) organized 256K bits. requires single power supply normal read mode operation. word accessed (continued)
Configurations
Name Note: Function Addresses Outputs Chip Enable Output Enable Connect Both pins must connected.
PLCC View
PDIP View
VSOP View Type
Rev. 0311F-10/98
less than eliminating need speed-reducing WAIT states. by-16 organization makes this part ideal high-performance 32-bit microprocessor systems. read mode, AT27C4096 typically consumes Standby mode supply current typically less than AT27C4 tand JEDEC-approved one-time programmable (OTP) plastic PDIP, PLCC, VSOP packages. device features two-line control (CE, eliminate contention high-speed systems. With high density 256K word storage capability, AT27C4096 allows firmware stored reliably accessed system without delays mass storage media. Atmel's AT27C4096 additional features that ensure high quality efficient production use. RapidProgramming Algorithm reduces time required program part guarantees reliable programming. Programming time typically only µs/word. Integrated Product Identification Code electronically identifies device
manufacturer. This feature used industry standard programming equipment select proper programming algorithms voltages.
System Considerations
Switching between active standby conditions Chip Enable produce transient voltage excursions. Unless accommodated system design, these transients exceed data sheet limits, resulting device non-conformance. minimum, high frequency, inherent inductance, ceramic capacitor should utilized each device. This capacitor should connected between Ground terminals device, close device possible. Additionally, stabilize supply voltage level printed circuit boards with large EPROM arrays, bulk electrolytic capacitor should utilized, again connected between Ground terminals. This capacitor should positioned close possible point where power supply connected array.
Block Diagram
AT27C4096
AT27C4096
Absolute Maximum Ratings*
Temperature Under Bias -55°C +125°C Storage Temperature -65°C +150°C Voltage with Respect Ground .-2.0V +7.0V(1) Voltage with Respect Ground .-2.0V +14.0V(1) Supply Voltage with Respect Ground .-2.0V +14.0V(1) Note: Maximum voltage -0.6V which undershoot -2.0V pulses less than Maximum output voltage 0.75V which overshoot +7.0V pulses less than *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions beyond those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
Operating Modes
Mode/Pin Read Output Disable Standby Rapid Program Verify Inhibit Product Identification(4) Notes: VIH. Refer Programming characteristics. 12.0 0.5V. identifier words selected. inputs held (VIL), except which which toggled (VIL) select Manufacturer's Identification word high (VIH) select Device Code word. Standby current (ISB) specified with VCC. will cause slight increase ISB.
VH(3)
Outputs DOUT High High DOUT High Identification Code
X(5)
Operating Conditions Read Operation
AT27C4096 Operating Temperature (Case) Power Supply Com. Ind. 70°C -40°C 85°C 70°C -40°C 85°C 70°C -40°C 85°C 70°C -40°C 85°C 70°C -40°C 85°C
Operating Characteristics Read Operation
Symbol IPP1(2) Parameter Input Load Current Output Leakage Current VPP(1) Read/Standby Current Condition VOUT ISB1 (CMOS) 0.3V ISB2 (TTL) 0.5V MHz, IOUT -0.6 -400 Units
Standby Current
Notes:
Active Current Input Voltage Input High Voltage Output Voltage Output High Voltage
must applied simultaneously before VPP, removed simultaneously after connected directly VCC, except during programming. supply current would then
Characteristics Read Operation
AT27C4096 Symbol tACC(3) tCE(2)
(2)(3)
Units
Parameter Address Output Delay Output Delay Output Delay
Condition
tDF(4)(5) tOH(4) Note:
High Output Float, whichever occurred first Output Hold from Address, whichever occurred first
Waveforms Read Operation diagram.
AT27C4096
AT27C4096
Waveforms Read Operation(1)
Notes:
Timing measurement references 0.8V 2.0V. Input drive levels 0.45V 2.4V, unless otherwise specified. delayed after falling edge without impact tCE. delayed tACC after address valid without impact tACC. This parameter only sampled 100% tested. Output float defined point when data longer driven.
Input Test Waveforms Measurement Levels
devices only:
Output Test Load
1.3V (1N914) OUTPUT 3.3K
(10% 90%) -70, -90, devices:
Note:
including capacitance, except devices, where
(10% 90%)
Capacitance
MHz, 25°C(1)
Symbol COUT Note: Units Conditions VOUT
Typical values nominal supply voltage. This parameter only sampled 100% tested.
Programming Waveforms(1)
Notes:
Input Timing Reference 0.8V 2.0V VIH. tDFP characteristics device must accommodated programmer. When programming AT27C4096, capacitor required across ground suppress spurious voltage transients.
Programming Characteristics
5°C, 0.25V, 13.0 0.25V
Limits Symbol ICC2 IPP2 Parameter Input Load Current Input Level Input High Level Output Voltage Output High Voltage Supply Current (Program Verify) Supply Current Product Identification Voltage 11.5 -400 12.5 Test Conditions VIL, -0.6 Units
AT27C4096
AT27C4096
Programming Characteristics
5°C, 0.25V, 13.0 0.25V
Limits Symbol tOES tDFP tVPS tVCS tPRT Notes: Parameter Address Setup Time Setup Time Data Setup Time Address Hold Time Data Hold Time High Output Float Delay(2) Setup Time Setup Time Program Pulse Width Data Valid from Pulse Rise Time During Programming
Test Conditions
Units
Input Rise Fall Times (10% 90%) Input Pulse Levels: 0.45V 2.4V Input Timing Reference Level: 0.8V 2.0V Output Timing Reference Level: 0.8V 2.0V
47.5 52.5
must applied simultaneously before removed simultaneously after This parameter only sampled 100% tested. Output Float defined point where data longer driven -see timing diagram. Program Pulse width tolerance µsec
Atmel's 27C4096 Intergrated Product Identification Code
Pins Codes Manufacturer Device Type O15-O8 Data 001E 00F4
Rapid Programming Algorithm
pulse width used program. address first location. raised 6.5V raised 13.0V. Each address first programmed with pulse without verification. Then verification/reprogramming loop executed each address. event word fails pass verification, successive pulses applied with verification after each pulse. word fails verify after pulses have been applied, part considered failed. After word verifies properly, next address selected until have been checked. then lowered 5.0V 5.0V. words read again compared with original data determine device passes fails.
AT27C4096
AT27C4096
Ordering Information
(mA) tACC (ns) Active Standby Ordering Code AT27C4096-55JC AT27C4096-55PC AT27C4096-55VC AT27C4096-55JI AT27C4096-55PI AT27C4096-55VI AT27C4096-70JC AT27C4096-70PC AT27C4096-70VC AT27C4096-70JI AT27C4096-70PI AT27C4096-70VI AT27C4096-90JC AT27C4096-90PC AT27C4096-90VC AT27C4096-90JI AT27C4096-90PI AT27C4096-90VI AT27C4096-12JC AT27C4096-12PC AT27C4096-12VC AT27C4096-12JI AT27C4096-12PI AT27C4096-12VI AT27C4096-15JC AT27C4096-15PC AT27C4096-15VC AT27C4096-15JI AT27C4096-15PI AT27C4096-15VI Package 40P6 40P6 40P6 40P6 40P6 40P6 40P6 40P6 40P6 40P6 Operation Range Commercial (0°C 70°C) Industrial (-40°C 85°C) Commercial (0°C 70°C) Industrial (-40°C 85°C) Commercial (0°C 70°C) Industrial (-40°C 85°C) Commercial (0°C 70°C) Industrial (-40°C 85°C) Commercial (0°C 70°C) Industrial (-40°C 85°C)
Package Type
40P6 44-Lead, Plastic J-Leaded Chip Carrier (PLCC) 40-Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) 40-Lead, Plastic Thin Small Outline Package (VSOP)
Packaging Information
44J, 44-Lead, Plastic J-Leaded Chip Carrier (PLCC) Dimensions Inches (Millimeters)
JEDEC STANDARD MS-018
40P6, 40-Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) Dimensions Inches (Millimeters)
JEDEC STANDARD MS-011
.045(1.14)
IDENTIFY
.045(1.14)
.012(.305) .008(.203)
2.07(52.6) 2.04(51.8)
.656(16.7) .650(16.5) .032(.813) .026(.660) .695(17.7) .685(17.4)
.630(16.0) .590(15.0) .021(.533) .013(.330)
.566(14.4) .530(13.5)
.050(1.27) .500(12.7)
.043(1.09) .020(.508) .120(3.05) .090(2.29) .180(4.57) .165(4.19)
1.900(48.26) .220(5.59) SEATING PLANE .161(4.09) .125(3.18)
.090(2.29) .005(.127)
.022(.559) (3X)
.110(2.79) .090(2.29)
.065(1.65) .041(1.04) .630(16.0) .590(15.0) .690(17.5) .610(15.5)
.065(1.65) .015(.381) .022(.559) .014(.356)
.012(.305) .008(.203)
40V, 40-Lead, Plastic Thin Small Outline Package (TSOP) Dimensions Millimeters (Inches)
JEDEC OUTLINE MO-142
AT27C4096
AT27C4096
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0311F-10/98/xM
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