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· Fast Read Access Time - 55 ns · Low Power CMOS Operation ·

4-Megabit (256K x 16) OTP EPROM AT27C4096

Features
· Fast Read Access Time - 55 ns · Low Power CMOS Operation ·
4-Megabit (256K x 16) OTP EPROM AT27C4096
Description
The AT27C4096 is a low-power, high-performance 4, 194, 304-bit one-time programmable read only memory (OTP EPROM) organized 256K by 16 bits. It requires a single 5V power supply in normal read mode operation. Any word can be accessed in (continued)
Pin Configurations
Pin Name A0 - A17 O0 - O15 CE OE NC Note: Function Addresses Outputs Chip Enable Output Enable No Connect Both GND pins must be connected.
O12 O11 O10 O9 O8 GND NC O7 O6 O5 O4
PLCC Top View
O13 O14 O15 CE VPP NC VCC A17 A16 A15 A14
A9 A10 A11 A12 A13 A14 A15 A16 A17 VCC VPP CE O15 O14 O13 O12 O11 O10 O9 O8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
PDIP Top View
VPP CE O15 O14 O13 O12 O11 O10 O9 O8 GND O7 O6 O5 O4 O3 O2 O1 O0 OE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC A17 A16 A15 A14 A13 A12 A11 A10 A9 GND A8 A7 A6 A5 A4 A3 A2 A1 A0
A13 A12 A11 A10 A9 GND NC A8 A7 A6 A5
VSOP Top View Type 1
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 GND A8 A7 A6 A5 A4 A3 A2 A1 A0 OE O0 O1 O2 O3 O4 O5 O6 O7 GND
Rev. 0311F-10 / 98
and manufacturer. This feature is used by industry standard programming equipment to select the proper programming algorithms and voltages.
System Considerations
Switching between active and standby conditions via the Chip Enable pin may produce transient voltage excursions. Unless accommodated by the system design, these transients may exceed data sheet limits, resulting in device non-conformance. At a minimum, a 0.1 µF high frequency, low inherent inductance, ceramic capacitor should be utilized for each device. This capacitor should be connected between the V CC and Ground terminals of the device, as close to the device as possible. Additionally, to stabilize the supply voltage level on printed circuit boards with large EPROM arrays, a 4.7 µF bulk electrolytic capacitor should be utilized, again connected between the VCC and Ground terminals. This capacitor should be positioned as close as possible to the point where the power supply is connected to the array.
Block Diagram
AT27C4096
Absolute Maximum Ratings
Temperature Under Bias ................ -55°C to +125°C Storage Temperature ................... -65°C to +150°C Voltage on Any Pin with Respect to Ground .....................-2.0V to +7.0V(1) Voltage on A9 with Respect to Ground ...................-2.0V to +14.0V(1) VPP Supply Voltage with Respect to Ground ....................-2.0V to +14.0V(1) Note: 1. Maximum voltage is -0.6V dc which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is VCC + 0.75V dc which may overshoot to +7.0V for pulses of less than 20 ns. NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Operating Modes
CE VIL X VIH VIL VIH VIH VIL
OE VIL VIH X VIH VIL VIH VIL
Outputs DOUT High Z High Z DIN DOUT High Z Identification Code
X X(5) VPP VPP VPP VCC
DC and AC Operating Conditions for Read Operation
DC and Operating Characteristics for Read Operation
Standby Current
ICC VIL VIH VOL VOH Notes:
VCC Active Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
1. VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP . 2. VPP may be connected directly to VCC, except during programming. The supply current would then be the sum of ICC and IPP .
AC Characteristics for Read Operation
AT27C4096 -55 Symbol tACC(3) tCE(2) tOE
-70 Min Max 70 70 30 20 7 0 Min
-90 Max 90 90 35 20 0 Min
-12 Max 120 120 40 30 0 Min
-15 Max 150 150 50 35 Units ns ns ns ns ns
Parameter Address to Output Delay CE to Output Delay OE to Output Delay
Max 55 55 20 20
tDF(4)(5) tOH(4) Note:
OE or CE High to Output Float, whichever occurred first Output Hold from Address, CE or OE, whichever occurred first 7
2, 3, 4, 5. See the AC Waveforms for Read Operation diagram.
AT27C4096
AC Waveforms for Read Operation(1)
Notes:
Input Test Waveforms and Measurement Levels
For -55 devices only:
Output Test Load
1.3V (1N914) OUTPUT PIN 3.3K
Note:
Pin Capacitance
Programming Waveforms(1)
Notes:
The Input Timing Reference is 0.8V for VIL and 2.0V for VIH. tOE and tDFP are characteristics of the device but must be accommodated by the programmer. When programming the AT27C4096, a 0.1 µF capacitor is required across VPP and ground to suppress spurious voltage transients.
DC Programming Characteristics
AT27C4096
AC Programming Characteristics
Limits Symbol tAS tOES tDS tAH tDH tDFP tVPS tVCS tPW tOE tPRT Notes: Parameter Address Setup Time OE Setup Time Data Setup Time Address Hold Time Data Hold Time OE High to Output Float Delay(2) VPP Setup Time VCC Setup Time CE Program Pulse Width Data Valid from OE VPP Pulse Rise Time During Programming
Test Conditions
Units µs µs µs µs µs
Pins Codes Manufacturer Device Type A0 0 1 O15-O8 0 0 O7 0 1 O6 0 1 O5 0 1 O4 1 1 O3 1 0 O2 1 1 O1 1 0 O0 0 0 Hex Data 001E 00F4
Rapid Programming Algorithm
A 50 µs CE pulse width is used to program. The address is set to the first location. V CC is raised to 6.5V and V PP is raised to 13.0V. Each address is first programmed with one 50 µs CE pulse without verification. Then a verification / reprogramming loop is executed for each address. In the event a word fails to pass verification, up to 10 successive 50 µs pulses are applied with a verification after each pulse. If the word fails to verify after 10 pulses have been applied, the part is considered failed. After the word verifies properly, the next address is selected until all have been checked. VPP is then lowered to 5.0V and VCC to 5.0V. All words are read again and compared with the original data to determine if the device passes or fails.
AT27C4096
Ordering Information
ICC (mA) tACC (ns) 55 Active 40 Standby 0.1 Ordering Code AT27C4096-55JC AT27C4096-55PC AT27C4096-55VC AT27C4096-55JI AT27C4096-55PI AT27C4096-55VI AT27C4096-70JC AT27C4096-70PC AT27C4096-70VC AT27C4096-70JI AT27C4096-70PI AT27C4096-70VI AT27C4096-90JC AT27C4096-90PC AT27C4096-90VC AT27C4096-90JI AT27C4096-90PI AT27C4096-90VI AT27C4096-12JC AT27C4096-12PC AT27C4096-12VC AT27C4096-12JI AT27C4096-12PI AT27C4096-12VI AT27C4096-15JC AT27C4096-15PC AT27C4096-15VC AT27C4096-15JI AT27C4096-15PI AT27C4096-15VI Package 44J 40P6 40V 44J 40P6 40V 44J 40P6 40V 44J 40P6 40V 44J 40P6 40V 44J 40P6 40V 44J 40P6 40V 44J 40P6 40V 44J 40P6 40V 44J 40P6 40V Operation Range Commercial (0°C to 70°C) Industrial (-40°C to 85°C) Commercial (0°C to 70°C) Industrial (-40°C to 85°C) Commercial (0°C to 70°C) Industrial (-40°C to 85°C) Commercial (0°C to 70°C) Industrial (-40°C to 85°C) Commercial (0°C to 70°C) Industrial (-40°C to 85°C)
Package Type
44J 40P6 40V 44-Lead, Plastic J-Leaded Chip Carrier (PLCC) 40-Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) 40-Lead, Plastic Thin Small Outline Package (VSOP) 10 x 14 mm
Packaging Information
44J, 44-Lead, Plastic J-Leaded Chip Carrier (PLCC) Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-018 AC
40P6, 40-Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-011 AC
.045(1.14) X 45°
PIN NO. 1 IDENTIFY
.045(1.14) X 30° - 45°
.656(16.7) SQ .650(16.5) .032(.813) .026(.660) .695(17.7) SQ .685(17.4)
.050(1.27) TYP .500(12.7) REF SQ
1.900(48.26) REF .220(5.59) MAX SEATING PLANE .161(4.09) .125(3.18)
.090(2.29) MAX .005(.127) MIN
.022(.559) X 45° MAX (3X)
.065(1.65) .041(1.04) .630(16.0) .590(15.0) 0 REF 15 .690(17.5) .610(15.5)
40V, 40-Lead, Plastic Thin Small Outline Package (TSOP) Dimensions in Millimeters and (Inches)
JEDEC OUTLINE MO-142 CA
AT27C4096
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0311F-10 / 98 / xM
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