Read Reprogramming Fast Read Access Time Internal Program Control Time

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Read Reprogramming Fast Read Access Time Internal Program Control Time

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Single-voltage Operation
Read Reprogramming Fast Read Access Time Internal Program Control Timer Sector Architecture Byte Boot Block with Programming Lockout Byte Parameter Blocks Main Memory Blocks (96K, 128K Bytes) Fast Erase Cycle Time seconds Byte-by-byte Programming µs/Byte Typical Hardware Data Protection DATA Polling Program Detection Power Dissipation Active Current CMOS Standby Current Typical 10,000 Write Cycles
2-megabit (256K 5-volt Only Flash Memory AT49F002 AT49F002N AT49F002T AT49F002NT
Description
AT49F002(N)(T) 5-volt only in-system reprogrammable Flash memory. megabits memory organized 262,144 words bits. Manufactured with Atmel's advanced nonvolatile CMOS technology, device offers access times with power dissipation just over commercial temperature range. (continued)
Configurations
Name RESET I/O0 I/O7 Function Addresses Chip Enable Output Enable Write Enable RESET Data Inputs/Outputs Don't Connect PLCC View
RESET
View
RESET I/O0 I/O1 I/O2 I/O7 I/O6 I/O5 I/O4 I/O3
VSOP View TSOP View Type
RESET I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
I/O1 I/O2 I/O3 I/O4 I/O5 I/O6
I/O0
I/O7
Rev. 1017D-10/99
*Note: This AT49F002(N)(T).
When device deselected, CMOS standby current less than AT49F002N(T) PLCC packages TSOP package don't connect pins. allow simple in-system reprogrammability, AT49F002(N)(T) does require high input voltages programming. Five-volt-only commands determine read programming operation device. Reading data device similar reading from EPROM; standard inputs avoid contention. Reprogramming AT49F002(N)(T) performed erasing block data then programming byte byte basis. byte programming time fast program cycle optionally detected DATA polling feature. Once byte program cycle been detected, access read program begin. typical number program erase cycles excess 10,000 cycles.
device erased executing erase command sequence; device internally controls erase operations. There byte parameter block sections main memory blocks. device capability protect data boot block; this feature enabled command sequence. 16K-byte boot block section includes reprogramming lock feature provide data integrity. boot sector designed contain user secure code, when feature enabled, boot sector protected from being reprogrammed. AT49F002(N)(T), once boot block programming lockout feature enabled, contents boot block permanent cannot changed. AT49F002(T), once boot block programming lockout feature enabled, contents boot block cannot changed with input voltage levels volts less.
Block Diagram
AT49F002(N) DATA INPUTS/OUTPUTS I/O7 I/O0 RESET INPUT/OUTPUT BUFFERS PROGRAM DATA LATCHES Y-GATING 3FFFF DECODER MAIN MEMORY BLOCK (128K BYTES) MAIN MEMORY BLOCK (96K BYTES) PARAMETER BLOCK BYTES) PARAMETER BLOCK BYTES) BOOT BLOCK (16K BYTES) BOOT BLOCK (16K BYTES) 20000 1FFFF PARAMETER BLOCK BYTES) PARAMETER BLOCK BYTES) MAIN MEMORY BLOCK (96K BYTES) MAIN MEMORY BLOCK (128K BYTES) AT49F002(N)T DATA INPUTS/OUTPUTS I/O7 I/O0 INPUT/OUTPUT BUFFERS PROGRAM DATA LATCHES Y-GATING 3FFFF 3C000 3BFFF
CONTROL LOGIC
DECODER ADDRESS INPUTS
08000 07FFF
3A000 39FFF
06000 05FFF
38000 37FFF
04000 03FFF 00000
20000 1FFFF
00000
AT49F002(N)(T)
AT49F002(N)(T)
Device Operation
READ: AT49F002(N)(T) accessed like EPROM. When high, data stored memory location determined address pins asserted outputs. outputs high impedance state whenever high. This dual-line control gives designers flexibility preventing contention. COMMAND SEQUENCES: When device first powered will reset read standby mode depending upon state control line inputs. order perform other device functions, series command sequences entered into device. command sequences shown Command Definitions table. command sequences written applying pulse input with (respectively) high. address latched falling edge whichever occurs last. data latched first rising edge Standard microprocessor write timings used. address locations used command sequences affected entering command sequences. RESET: RESET input provided ease some system applications. When RESET logic high level, device standard operating mode. level RESET input halts present device operation puts outputs device high impedance state. RESET makes high transition during program erase operation, operation successfully completed operation will have repeated after high level applied RESET pin. When high level reasserted RESET pin, device returns read standby mode, depending upon state control inputs. applying 0.5V input signal RESET pin, boot block array reprogrammed even boot block lockout feature been enabled (see Boot Block Programming Lockout Override section). RESET feature available AT49F002N(T). ERASURE: Before byte reprogrammed, main memory block parameter block which contains byte must erased. erased state memory bits logical "1". entire device erased time using 6-byte software code. software chip erase code consists 6-byte load commands specific address locations with specific data pattern (please refer Chip Erase Cycle Waveforms). After software chip erase been initiated, device will internally time erase operation that external clocks required. maximum time needed erase whole chip tEC. boot block lockout feature been enabled, data boot sector will erased. CHIP ERASE: boot block lockout been enabled, Chip Erase function will erase Parameter Block Parameter Block Main Memory Block Main Memory Block boot block. Boot Block Lockout been enabled, Chip Erase function will erase entire chip. After full chip erase device will return back read mode. command during chip erase will ignored. SECTOR ERASE: alternative full chip erase, device organized into sectors that individually erased. There 8K-byte parameter block sections main memory blocks. 8K-byte parameter block sections independently erased reprogrammed. main memory sections designed used alternative memory sectors. That whenever blocks been erased reprogrammed, other block should erased reprogrammed before first block again erased. Sector Erase command cycle operation. sector address latched falling edge sixth cycle while data input command latched rising edge sector erase starts after rising edge sixth cycle. erase operation internally controlled; will automatically time completion. BYTE PROGRAMMING: Once memory array erased, device programmed logical "0") byte-by-byte basis. Please note that data cannot programmed back "1"; only erase operations convert "0"s "1"s. Programming accomplished internal device command register cycle operation (please refer Command Definitions table). device will automatically generate required internal program pulses. program cycle addresses latched falling edge whichever occurs last, data latched rising edge whichever occurs first. Programming completed after specified cycle time. DATA polling feature also used indicate program cycle. BOOT BLOCK PROGRAMMING LOCKOUT: device designated block that programming lockout feature. This feature prevents programming data designated block once feature been enabled. size block bytes. This block, referred boot block, contain secure code that used bring system. Enabling lockout feature will allow boot code stay device while data rest device updated. This feature does have activated; boot block's usage write protected region optional user. address range boot block 00000 03FFF AT49F002(N) while address
range boot block 3C000 3FFFF AT49F002(N)T. Once feature enabled, data boot block longer erased programmed with input voltage levels 5.5V less. Data main memory block still changed through regular programming method. activate lockout feature, series program commands specific addresses with specific data must performed. Please refer Command Definitions table. BOOT BLOCK LOCKOUT DETECTION: software method available determine programming boot block section locked out. When device software product identification mode (see Software Product Identification Entry Exit sections) read from address location 00002H will show programming boot block locked AT49F002(N), read from address location 3C002H will show programming boot block locked AT49F002(N)T. data I/O0 low, boot block programmed; data I/O0 high, program lockout feature been activated block cannot programmed. software product identification exit code should used return standard operation. BOOT BLOCK PROGRAMMING LOCKOUT OVERRIDE: user override boot block programming lockout taking RESET volts. doing this, protected boot block data altered through chip erase, sector erase word programming. When RESET brought back levels boot block programming lockout feature again active. This feature available AT49F002N(T).
PRODUCT IDENTIFICATION: product identification mode identifies device manufacturer Atmel. accessed hardware software operation. hardware operation mode used external programmer identify correct programming algorithm Atmel product. details, Operating Modes (for hardware operation) Software Product Identification. manufacturer device code same both modes. DATA POLLING: AT49F002(N)(T) features DATA polling indicate program cycle. During program cycle attempted read last byte loaded will result complement loaded data I/O7. Once program cycle been completed, true data valid outputs next cycle begin. DATA polling begin time during program cycle. DATA AT49F002(N)(T) provides another method determining program erase cycle. During program erase operation, successive attempts read data from device will result I/O6 toggling between zero. Once program cycle completed, I/O6 will stop toggling valid data will read. Examining toggle begin time during program cycle. HARDWARE DATA PROTECTION: Hardware features protect against inadvertent programs AT49F002(N)(T) following ways: sense: below 3.8V (typical), program function inhibited. Program inhibit: holding low, high high inhibits program cycles. Noise filter: pulses less than (typical) inputs will initiate program cycle.
AT49F002(N)(T)
AT49F002(N)(T)
Command Definition Hex)(1)
Command Sequence Read Chip Erase Sector Erase Byte Program Boot Block Lockout Product Entry Product Exit Product Exit Notes:
Cycles
Cycle Addr Addr 5555 5555 5555 5555 5555 5555 XXXX Data DOUT
Cycle Addr Data
Cycle Addr Data
Cycle Addr Data
Cycle Addr Data
Cycle Addr Data
2AAA 2AAA 2AAA 2AAA 2AAA 2AAA
5555 5555 5555 5555 5555 5555
5555 5555 Addr 5555
2AAA 2AAA
5555 SA(4)
2AAA
5555
DATA FORMAT each cycle follows: I/O7 I/O0 (Hex) byte boot sector address range 00000H 03FFFH AT49F002(N) 3C000H 3FFFFH AT49F002(N)T Either Product Exit commands used. sector addresses: AT49F002(N): 00000 03FFF BOOT BLOCK Nothing will happen device goes back read mode 04000 05FFF PARAMETER BLOCK 06000 07FFF PARAMETER BLOCK 08000 1FFFF MAIN MEMORY ARRAY BLOCK This command will erase PB1, MMB1 20000 3FFFF MAIN MEMORY ARRAY BLOCK AT49F002(N)T: 3C000 3FFFF BOOT BLOCK Nothing will happen device goes back read mode 3A000 3BFFF PARAMETER BLOCK 38000 39FFF PARAMETER BLOCK 20000 37FFF MAIN MEMORY ARRAY BLOCK This command will erase PB1, MMB1 00000 IFFFF MAIN MEMORY ARRAY BLOCK
Absolute Maximum Ratings*
Temperature Under Bias. -55°C +125°C Storage Temperature -65°C +150°C Input Voltages (including Pins) with Respect Ground .-0.6V +6.25V Output Voltages with Respect Ground .-0.6V 0.6V Voltage with Respect Ground .-0.6V +13.5V *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions beyond those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
Operating Range
AT49F002(N)(T)-55 Operating Temperature (Case) Power Supply Com. Ind. 70°C -40°C 85°C AT49F002(N)(T)-70 70°C -40°C 85°C AT49F002(N)(T)-90 70°C -40°C 85°C AT49F002(N)(T)-12 70°C -40°C 85°C
Operating Modes
Mode Read Program/Erase
RESET(6)
DOUT High
Standby/Write Inhibit Program Inhibit
Output Disable Reset Product Identification Hardware
High High
VIL, VH,(3) VIL, VH,(3) VIL, A17=VIL VIH, A17=VIL
Manufacturer Code(4) Device Code(4) Manufacturer Code(4) Device Code(4)
Software(5)
Notes:
VIH. Refer Programming Waveforms. 12.0V 0.5V. Manufacturer Code: 1FH, Device Code: AT49F002(N), AT49F002(N)T details under Software Product Identification Entry/Exit. This available AT49F002N(T).
Characteristics
Symbol ISB1 ISB2 ICC(1) VOH1 VOH2 Parameter Input Load Current Output Leakage Current Standby Current CMOS Standby Current Active Current Input Voltage Input High Voltage Output Voltage Output High Voltage Output High Voltage CMOS -400 -100 4.5V 0.45 Condition VI/O Com. 0.3V 2.0V MHz; IOUT Ind. Units
Note:
erase mode,
AT49F002(N)(T)
AT49F002(N)(T)
Read Characteristics
AT49F002(N)(T) Symbol tACC
Units
Parameter Address Output Delay Output Delay Output Delay Output Float Output Hold from Address, whichever occurred first
tDF(3)(4)
Read Waveforms (1)(2)(3)(4)
ADDRESS ADDRESS VALID
tACC
OUTPUT VALID
OUTPUT
HIGH
Notes:
delayed tACC after address transition without impact tACC. delayed after falling edge without impact tACC after address change without impact tACC. specified from whichever occurs first pF). This parameter characterized 100% tested.
Input Test Waveform Measurement Level
Output Load Test
5.0V 1.8K OUTPUT
70/90/120
5.0V 1.8K OUTPUT
1.3K
1.3K
Capacitance
MHz, 25°C(1)
Symbol COUT Note: Units Conditions VOUT
This parameter characterized 100% tested.
Byte Load Characteristics
Symbol tAS, tOES tDH, tOEH tWPH Parameter Address, Set-up Time Address Hold Time Chip Select Set-up Time Chip Select Hold Time Write Pulse Width Data Set-up Time Data, Hold Time Write Pulse Width High Units
Byte Load Waveforms
Controlled
tOES ADDRESS tWPH DATA tOEH
Controlled
tOES ADDRESS tWPH DATA tOEH
AT49F002(N)(T)
AT49F002(N)(T)
Program Cycle Characteristics
Symbol tWPH Parameter Byte Programming Time Address Set-up Time Address Hold Time Data Set-up Time Data Hold Time Write Pulse Width Write Pulse Width High Erase Cycle Time Units seconds
Program Cycle Waveforms
Sector Chip Erase Cycle Waveforms
Notes:
must high only when both low. chip erase, address should 5555. sector erase, address depends what sector erased. (See note under command definitions.) chip erase, data should 10H, sector erase, data should 30H.
Data Polling Characteristics(1)
Symbol tOEH Notes: Parameter Data Hold Time Hold Time Output Delay
Units
Write Recovery Time These parameters characterized 100% tested. spec Read Characteristics.
Data Polling Waveforms
tOEH I/O7 A0-A17 HIGH
Toggle Characteristics(1)
Symbol tOEH tOEHP Notes: Parameter Data Hold Time Hold Time Output Delay(2) High Pulse Write Recovery Time These parameters characterized 100% tested. spec Read Characteristics. Units
Toggle Waveforms(1)(2)(3)
tOEH I/O6 HIGH tOEHP
Notes:
Toggling either both will operate toggle bit. tOEHP specification must toggling input(s). Beginning ending state I/O6 will vary. address location used address should vary.
AT49F002(N)(T)
AT49F002(N)(T)
Software Product Identification Entry(1)
LOAD DATA ADDRESS 5555 LOAD DATA ADDRESS 2AAA LOAD DATA ADDRESS 5555 ENTER PRODUCT IDENTIFICATION MODE(2)(3)(5)
Boot Block Lockout Feature Enable Algorithm(1)
LOAD DATA ADDRESS 5555 LOAD DATA ADDRESS 2AAA LOAD DATA ADDRESS 5555 LOAD DATA ADDRESS 5555 LOAD DATA ADDRESS 2AAA LOAD DATA ADDRESS 5555
Software Product Identification Exit(1)
LOAD DATA ADDRESS 5555 LOAD DATA ADDRESS 2AAA LOAD DATA ADDRESS 5555 EXIT PRODUCT IDENTIFICATION MODE(4)
LOAD DATA ADDRESS EXIT PRODUCT IDENTIFICATION MODE(4)
PAUSE second(2)
Notes software product identification Data Format: I/O7 I/O0 (Hex); Address Format: (Hex). VIL. Manufacture Code read VIL; Device Code read VIH. device does remain identification mode powered down. device returns standard operation mode. Manufacturer Code: Device Code: AT49F002(N) AT49F002(N)T
Notes boot block lockout feature enable: Data Format: I/O7 I/O0 (Hex); Address Format: (Hex). Boot block lockout feature enabled.
AT49F002 Ordering Information
tACC (ns) (mA) Active Standby Ordering Code AT49F002-55JC AT49F002-55PC AT49F002-55TC AT49F002-55VC AT49F002-55JI AT49F002-55PI AT49F002-55TI AT49F002-55VI AT49F002-70JC AT49F002-70PC AT49F002-70TC AT49F002-70VC AT49F002-70JI AT49F002-70PI AT49F002-70TI AT49F002-70VI AT49F002-90JC AT49F002-90PC AT49F002-90TC AT49F002-90VC AT49F002-90JI AT49F002-90PI AT49F002-90TI AT49F002-90VI AT49F002-12JC AT49F002-12PC AT49F002-12TC AT49F002-12VC AT49F002-12JI AT49F002-12PI AT49F002-12TI AT49F002-12VI Package 32P6 32P6 32P6 32P6 32P6 32P6 32P6 32P6 Operation Range Commercial 70°C)
Industrial (-40° 85°C)
Commercial 70°C)
Industrial (-40° 85°C)
Commercial 70°C)
Industrial (-40° 85°C)
Commercial 70°C)
Industrial (-40° 85°C)
Package Type 32P6 32-lead, Plastic J-leaded Chip Carrier Package (PLCC) 32-pin, 0.600" Wide, Plastic Dual Inline Package (PDIP) 32-lead, Plastic Thin Small Outline Package (TSOP) 32-lead, Plastic Thin Small Outline Package (VSOP)
AT49F002(N)(T)
AT49F002(N)(T)
AT49F002N Ordering Information
tACC (ns) (mA) Active Standby Ordering Code AT49F002N-55JC AT49F002N-55PC AT49F002N-55TC AT49F002N-55VC AT49F002N-55JI AT49F002N-55PI AT49F002N-55TI AT49F002N-55VI AT49F002N-70JC AT49F002N-70PC AT49F002N-70TC AT49F002N-70VC AT49F002N-70JI AT49F002N-70PI AT49F002N-70TI AT49F002N-70VI AT49F002N-90JC AT49F002N-90PC AT49F002N-90TC AT49F002N-90VC AT49F002N-90JI AT49F002N-90PI AT49F002N-90TI AT49F002N-90VI AT49F002N-12JC AT49F002N-12PC AT49F002N-12TC AT49F002N-12VC AT49F002N-12JI AT49F002N-12PI AT49F002N-12TI AT49F002N-12VI Package 32P6 32P6 32P6 32P6 32P6 32P6 32P6 32P6 Operation Range Commercial 70°C)
Industrial (-40° 85°C)
Commercial 70°C)
Industrial (-40° 85°C)
Commercial 70°C)
Industrial (-40° 85°C)
Commercial 70°C)
Industrial (-40° 85°C)
Package Type 32P6 32-lead, Plastic J-leaded Chip Carrier Package (PLCC) 32-pin, 0.600" Wide, Plastic Dual Inline Package (PDIP) 32-lead, Plastic Thin Small Outline Package (TSOP) 32-lead, Plastic Thin Small Outline Package (VSOP)
AT49F002T Ordering Information
tACC (ns) (mA) Active Standby Ordering Code AT49F002T-55JC AT49F002T-55PC AT49F002T-55TC AT49F002T-55VC AT49F002T-55JI AT49F002T-55PI AT49F002T-55TI AT49F002T-55VI AT49F002T-70JC AT49F002T-70PC AT49F002T-70TC AT49F002T-70VC AT49F002T-70JI AT49F002T-70PI AT49F002T-70TI AT49F002T-70VI AT49F002T-90JC AT49F002T-90PC AT49F002T-90TC AT49F002T-90VC AT49F002T-90JI AT49F002T-90PI AT49F002T-90TI AT49F002T-90VI AT49F002T-12JC AT49F002T-12PC AT49F002T-12TC AT49F002T-12VC AT49F002T-12JI AT49F002T-12PI AT49F002T-12TI AT49F002T-12VI Package 32P6 32P6 32P6 32P6 32P6 32P6 32P6 32P6 Operation Range Commercial 70°C)
Industrial (-40° 85°C)
Commercial 70°C)
Industrial (-40° 85°C)
Commercial 70°C)
Industrial (-40° 85°C)
Commercial 70°C)
Industrial (-40° 85°C)
Package Type 32P6 32-lead, Plastic J-leaded Chip Carrier Package (PLCC) 32-pin, 0.600" Wide, Plastic Dual Inline Package (PDIP) 32-lead, Plastic Thin Small Outline Package (TSOP) 32-lead, Plastic Thin Small Outline Package (VSOP)
AT49F002(N)(T)
AT49F002(N)(T)
AT49F002NT Ordering Information
tACC (ns) (mA) Active Standby Ordering Code AT49F002NT-55JC AT49F002NT-55PC AT49F002NT-55TC AT49F002NT-55VC AT49F002NT-55JI AT49F002NT-55PI AT49F002NT-55TI AT49F002NT-55VI AT49F002NT-70JC AT49F002NT-70PC AT49F002NT-70TC AT49F002NT-70VC AT49F002NT-70JI AT49F002NT-70PI AT49F002NT-70TI AT49F002NT-70VI AT49F002NT-90JC AT49F002NT-90PC AT49F002NT-90TC AT49F002NT-90VC AT49F002NT-90JI AT49F002NT-90PI AT49F002NT-90TI AT49F002NT-90VI AT49F002NT-12JC AT49F002NT-12PC AT49F002NT-12TC AT49F002NT-12VC AT49F002NT-12JI AT49F002NT-12PI AT49F002NT-12TI AT49F002NT-12VI Package 32P6 32P6 32P6 32P6 32P6 32P6 32P6 32P6 Operation Range Commercial 70°C)
Industrial (-40° 85°C)
Commercial 70°C)
Industrial (-40° 85°C)
Commercial 70°C)
Industrial (-40° 85°C)
Commercial 70°C)
Industrial (-40° 85°C)
Package Type 32P6 32-lead, Plastic J-leaded Chip Carrier Package (PLCC) 32-pin, 0.600" Wide, Plastic Dual Inline Package (PDIP) 32-lead, Plastic Thin Small Outline Package (TSOP) 32-lead, Plastic Thin Small Outline Package (VSOP)
Packaging Information
32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC) Dimensions Inches (Millimeters)
JEDEC STANDARD MS-016
32P6, 32-pin, 0.600" Wide, Plastic Dual Inline Package (PDIP) Dimensions Inches (Millimeters)
.045(1.14)
IDENTIFY
.025(.635) .012(.305) .008(.203) .530(13.5) .490(12.4) .021(.533) .013(.330) .030(.762) .015(.381) .095(2.41) .060(1.52) .140(3.56) .120(3.05)
1.67(42.4) 1.64(41.7)
.032(.813) .026(.660)
.553(14.0) .547(13.9) .595(15.1) .585(14.9)
.566(14.4) .530(13.5)
.050(1.27)
.300(7.62) .430(10.9) .390(9.90) CONTACT POINTS
1.500(38.10) .220(5.59) SEATING PLANE .161(4.09) .125(3.18)
.090(2.29) .005(.127)
.022(.559) (3X) .453(11.5) .447(11.4) .495(12.6) .485(12.3)
.110(2.79) .090(2.29)
.065(1.65) .041(1.04) .630(16.0) .590(15.0) .690(17.5) .610(15.5)
.065(1.65) .015(.381) .022(.559) .014(.356)
.012(.305) .008(.203)
32T, 32-lead, Plastic Thin Small Outline Package (TSOP) Dimensions Millimeters (Inches)*
32V, 32-lead, Plastic Thin Small Outline Package (TSOP) Dimensions Millimeters (Inches)
INDEX MARK
INDEX MARK
18.5(.728) 18.3(.720)
20.2(.795) 19.8(.780)
12.5(.492) 12.3(.484)
14.2(.559) 13.8(.543)
0.50(.020)
7.50(.295) 8.20(.323) 7.80(.307)
0.25(.010) 0.15(.006)
0.50(.020)
7.50(.295) 8.10(.319) 7.90(.311)
0.25(.010) 0.15(.006)
1.20(.047)
1.20(.047)
0.15(.006) 0.05(.002) 0.20(.008) 0.10(.004) 0.70(.028) 0.50(.020)
0.15(.006) 0.05(.002) 0.20(.008) 0.10(.004) 0.70(.028) 0.50(.020)
*Controlling dimension: millimeters
AT49F002(N)(T)
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1017D-10/99/xM
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Read Reprogramming Fast Read Access Time Internal Program Control Time

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