SERIOUS ABOUT CONVERSIONS When We're Leader FPGA-to-ASIC Conversi

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SERIOUS ABOUT CONVERSIONS When We're Leader FPGA-to-ASIC Conversi

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SERIOUS ABOUT CONVERSIONS
When We're Leader FPGA-to-ASIC Conversions, Mean
more experience with FPGA-to-ASIC conversions than American Microsystems, Inc. (AMI). started converting FPGAs fifteen years when introduced NETRANSpackage conversion services. Since then, converted over 1,400 FPGA-to-ASIC ASIC-to-ASIC designs working silicon. have converted designs from nearly every type discrete TTL, PLD, FPGA, ASIC device. AMI's mapping libraries have been fully validated leading FPGA vendors. these one-hundred-percent validated libraries conjunction with scan-test insertion, automatic test program generation (ATPG), static timing analysis, AMI's internal translation methodologies allows seamless FPGA translations. AMI's vectorless option handles many designs that have simulation data available, avoiding need your engineering resources conversion process. industry's broadest conversion experience proven design verification methodology, resulting predictable production timetables. We'll translate your design into ASIC quickly. sure will work correctly first time.
Conversion Service
Take Conversion Business Seriously
Orca Actel Altera Xilinx
Other Toshiba
Netlist conversion services important part AMI's ASIC business company dedicated remaining industry leader. When bring your conversion AMI, you'll working with ASIC Translation Team, focused group ASIC design engineers with more than fifteen years specialized conversion experience.
NETRANS
ASIC
foregoing names constitute protected trade names, trademarks and/or service marks their respective owners.
Don't Need Tools
need tools NETRANS service. NETRANS interfaces directly with your existing netlist simulation data formats. What about "ideal" conversions that everyone talking about: design level, synthesize FPGA prototyping, then synthesize ASIC production? most cases converts designs faster than re-synthesize, preserving your engineering resources.
Compatibility Count
design that's converted true ASIC take advantage AMI's capabilities design, packaging, processing, testing meet your conversion requirements. also take advantage number special features that have been built into AMI's ASIC technology. example, embedded RAM, PLLs, DLLs, extensive standards, programmable power pins, even cores used maintain socket compatibility. don't stop there. supports several unique strategies reduce your overall cost risk. replace multiple interconnected FPGAs with single ASIC, reducing cost board space increasing reliability. also convert multiple disjoint FPGAs into single ASIC with chip select pins select desired FPGA functionality. This strategy will reduce NREs, give higher-volume piece price, reduce inventories.
Take Care
Unlike some competitors, modern fabrication facilities offering competitive CMOS process technologies. currently design 0.35 micron geometries, with 2.5-volt, 3.3-volt, 5-volt, mixed-voltage options, company proceeding with development deep submicron process geometries increased performance, higher levels integration, 1.8-volt operation. modular fabrication facilities allow build older processes using same modern equipment utilized with submicron technologies. result, offers long-term process support, maintaining fabrication processes over years-a rather unusual feature this fast-paced industry.
continues invest latest technology, like this stepper.
BENEFITS ECONOMICS CONVERTING
Convert?
Reduce costs dedicated team experts help decide when makes sense convert from FPGA where silicon package costs significant ASIC with same better performance characteristics. Improve performance Conversion FPGA older ASIC technology optimized ASIC solution refresh your product's competitive edge with increased speeds, clock frequencies, reduced power consumption. Reduce power consumption Many FPGA CPLD families dissipate significant amounts power their programmable interconnect high performance bias circuits. optimized ASIC solution will provide with significant power savings. Smaller footprint While your FPGA-based design large number pins, gate count often forces large FPGAs large packages. converted ASIC solution allows smaller package with right number pins, thereby reducing both cost footprint printed circuit board. Higher levels integration conversion experts have extensive experience consolidating multiple parts, including mixes FPGAs, ASICs, other logic devices. These multiple-to-one conversions improve reliability reduce both number devices board power consumption, again reducing cost. Fast prototyping NETRANS allows prototype that meets your requirements. want your initial prototype limited production FPGAs, NETRANS allows convert ASIC once system design stable. Second sourcing Sole sourcing critical ASIC leave without needed production. converted virtually every type ASIC netlist customers want avoid this risk. We've even provided second sourcing customers running ASIC their fab. Migration from obsolete processes Suddenly, your ASIC FPGA vendor wants drop older manufacturing process that your still-successful product depends Unable predict lifetime demands, lifetime question. Although committed providing long-term process support, continuously developing state-of-the-art processes. result, convert your design ASIC that generally newer, more cost-effective process.
When Does Make Sense Convert?
should consider converting when total cost converted ASIC more cost-effective than FPGA. simple break-even analysis shows this point usually somewhere between five hundred five thousand units, depending FPGA size package.
$160
-ASI
Gate Design/240 PQFP
Price/Unit (Includes NRE)
1,000
10,000 Volume/Year
Xilinx XCV100
100,000
ASIC (NRE Assumption $30K)
This Hewlett-Packard printed circuit assembly used four expensive FPGAs running reduced clock rate. Reaching required clock rate easy with AMI's gate arrays. Unlike FPGAs with their constrained architecture, gate arrays offer flexibility place route critical cells needed. Hewlett-Packard saves more than over cost FPGAs.
NETRANS SERVICNETRANS Netlist Formats Table ABEL Actel Altera Altera Max+Plus Atmel AT&T Cadat Cadence Cadence Cadence Cadnetics Compass Crosspoint CUPL Cypress Daisy EDIF Fairchild Fujitsu Funsim FutureNet NetList FutureNet PinList Gatefield Harris MIMIC Harris Zeus Hewlett Packard HILO Hughes Intel Jedec Fuse JEDEC Lasar Lattice Logic Mentor Mentor Nrel Mextra MINC Mostek Motorola National Semi Orcad Orcad Palasm PCAD Plessey Classic QuickLogic QDIF Silos Silvar Lisco SMos Spice Symbios (NCR) Synopsys Tango Telesis Texas Instruments Toshiba Valid Verilog VHDL Viewlogic Xerox Xilinx Zycad ZyMos
Universal FlexibleDesigned Real World
AMI's NETRANS designed comprehensive suite services addressing your FPGA ASIC netlist conversion requirements. Table shows netlist formats that NETRANS accommodates. Table shows currently supported simulation data formats. Table shows some leading FPGA families that NETRANS supports. Real world experience taught that there designs that fully synchronous. because they easiest convert, synchronous designs what most conversion services demand, leaving without avenue cost-efficient conversion your asynchronous design. NETRANS been developed meet demand reliable, flexible conversion technology that supports both synchronous asynchronous designs.
foregoing names constitute protected trade names, trademarks and/or service marks their respective owners.
NETRANS Simulation Data Formats Table
Advantest AIDA Scan Altera Ando Aspect AT&T Tquote Cadat Cadence Tabular Trace Chip Express Compass Credence Crosspoint Daisy Fujitsu Generic* GenRad GR16 Harris MIMIC Hewlett Packard HILO Holixz IKOS Trace IKOS Voyager IKOS WAVE SimGen Intel Jedec Vector LASAR Synchromaster Mach Detect Mentor Force Mentor Mentor LSim Mentor QuickSim Motorola Utic Orcad Palasm QuickLogic Raytheon Mtruth Sentry Silos Synopsys WIF2TAB Tegas Texas Instruments Toshiba Toshiba Trace Trillium TSSI TSSI Valid Veclink Verilog Verilog Tabular Trace Viewlogic Command Viewlogic Generic Viewlogic Print Viewlogic Trace Viewlogic Dynamic Trace Qsim Dynamic Trace Tabular Trace
Reads most columnar file formats. foregoing names constitute protected trade names, trademarks and/or service marks their respective owners.
FPGA-to-ASIC Conversion
Xilinx Input: xnf, wir, edif, Verilog, VHDL, XC2000, 3000, 4000, 5200, 7300, 9500, Spartan/II, Virtex/E LUT/Block RAM, Set/Reset selection JTAG boundry scan Certified Mapping Libraries X-Blox Synthesis, Altera
Table
Actel Input: adl, edif, Verilog, VHDL, ACT1, ACT2, ACT3,
Input: edif, Verilog, VHDL, Classic, Max, FLEX, APEX/E, ACEX
EAB/ESB RAM, Power reset logic JTAG boundry scan Certified Mapping Libraries Library Parameterized Modules (LPM)
3200DX ASIC-like architecture JTAG boundry scan Clock tree synthesis Certified Mapping Libraries
Inputs Outputs
NETRANS won't overwhelm with endless list requirements. inputs simple: your design netlist available simulation data files. simulation data files should include simulation stimulus expected response. outputs from NETRANS just what expect: reliable ASICs optional models.
Netlist
Inputs
Simulation Data
NETRANS
ASICs Outputs Model
Flow
Netlist Translation Logic Mapping ASIC Optimization Design Analysis Static Timing Analysis Test Bench Generation 5-Corner Logic Simulation Manufacturing Test Preparation Layout ASIC Fabrication
NETRANS Methodology
AMI's NETRANS methodology result industry's most extensive experience netlist conversion. assured converted design that meets functionality requirements fastest, most cost-effective manner possible. Netlist Translation translation step converts incoming netlist into format. Because AMI's list supported netlists extensive, there delay translating your design. (See Table page Logic Mapping Each logic function netlist mapped into ASIC equivalent. Cellsprogram, AMI's proprietary mapping software, flexible enough support one-to-multiple multiple-to-one transformations. addition, descriptions user-definable, making easy keep mapping libraries updated handle cells fly. Frequently used mapping libraries fully certified through rigorous process that insures each accurate. Finally, translation mapping processes completely preserve original design hierarchy node names. ASIC Optimization Optimization consists efficiency-enhancing operations such trimming unused gates, applying Demorgan's Theorem, combining simple logic into And/Or logic structures. Further optimization achieved stripping internal buffers re-buffering heavy loads. High-fanout, low-skew clock signals optimally buffered using clock tree synthesis. While gate count reductions significant CPLD FPGA conversions, ASIC conversions typically require less optimization. Although optimization process optional, encourage customers take advantage this process. Optimized designs significantly more efficient: smaller, faster, require less power. example, optimized designs, heavy loads driven properly sized buffers clock trees, resulting efficient performance elimination clock skew issues. AMI's buffer optimization software buffers different types loads best fashion.
Design Analysis AMI's Design Checkersoftware performs automated design review, looking design practices which known cause problems; specifically, whether design synchronous asynchronous. This includes checks simple things like floating inputs, classical problems such gated clocks pulse generators. software distinguishes between serious "glitch" generators ones that would never problem, thus keeping your conversion from being delayed unnecessary review. Static Timing Analysis AMI's Static Timing Analyzer software performs exhaustive timing path analysis reporting chip-level clock-to-out times, register-to-register delays set-up, hold-time requirements. These simple reports easily compared against FPGA development system reports system specifications. Because more efficient interconnect, ASIC technology typically faster than FPGA devices, allowing ensure proper timing achieved.
Test Bench Generation Final design validation proceeds simulating original circuit against ASIC design. Logic simulation verifies that translated design works. this stage gross timing issues resolved. simulation test bench generated several ways depending type circuit available simulation data. designer developed type simulations, either chip level, board level system level, will convert these into test bench. best format single file which data column each input, output, design. cases where there simulation vectors available, will Automatic Test Pattern Generation (ATPG) software develop test bench. This approach works well fully synchronous circuits acceptable many asynchronous circuits. When necessary, will manually develop simulation vectors validate conversion. Customers request ASIC model back from Verilog VHDL format. ASIC model plugged into regression test benches place FPGA model. This allows re-run board system level regression tests ASIC design. AMI-generated test benches also available creating extending existing regression test suites.
Five-Corner Diagram
[WC0,WC1] [BC0,WC1]
Time Delay, Rising Signals
Typical
BC0-Best Case Zero BC1-Best Case WC0-Worst Case Zero WC1-Worst Case
[BC0,BC1]
[WC0,BC1]
Time Delay, Falling Signals
Five-Corner LogicSimulation Five-Corner Logic Simulation technique used make sure design manufacturable. Similar technique min-max best-case/worst-case simulation, Five-Corner Logic Simulation accounts other timing issues unique CMOS technology. diagram above illustration Five-Corner Logic Simulation. Manufacturing Test Preparation FPGA devices pre-tested manufacturer using standard test program. other hand, ASIC devices fully customized require custom test program. develops Automatic Test Equipment (ATE) test programs based simulation test bench. fault coverage improvement necessary, ATPG used, internal scan chain inserted combined with ATPG.
Verification Methodology Works
AMI's NETRANS methodology focuses creating functionally equivalent part which fully optimized ASIC technology giving best overall results terms both cost performance. Typically, most problems with conversions revolve around timing issues. AMI's NETRANS methodology seeks first discover actual potential race condition, then ensures they will occur over acceptable range process, temperature, voltage parameter variations. This means that your design stable reliable. aspect NETRANS methodology that while design modified, general form original design maintained. Preserving this information makes conversion process smooth fast, especially necessary refer back original design.
Test Methodology
Once design fully converted, AMI's comprehensive netlist conversion methodology addresses major test issues: Simulation Manufacturing Test There significant difference between simulation data files manufacturing test programs conversion process. Simulations provide valuable tool verify conversion. Manufacturing test vectors used test individual parts insure that they defect-free. With advent various testing tools methodologies, necessary simulation data test vectors. verify FPGA-toASIC migration compare simulations FPGA ASIC designs. This easy designer developed simulation test bench kind. Often these test benches developed board-level system-level simulations. simply printing FPGA control signals file, designer capture very useful simulation data file. This file particularly helpful simulations exercise asynchronous timing issues.
Obtaining Sufficient Fault Coverage
100% ATPG with Scan
Fault Coverage
ATPG
Customer Supplied Simulations
Design Verification
want your prototype work first time. also want assured that will work after transferred volume production. That's AMI's ASIC Translation team uses combination fully certified mapping libraries, netlist checking, static timing analysis, Five-Corner Logic Simulation, either with customer-developed test benches with ATPG vectors. Strict adherence design verification protocols more helps ensure that remain competitive, whether issue cost reduction, timely introduction market, manufacturability.
When capturing this data designer should careful simulations timing mode. This means that simulator uses real internal delays FPGA, just unit zero delays. designer should also request that signal changes printed file when they actually occur. This normally called Print Change format. Functional simulation patterns make good test program. manufacturing test randomly injected defects silicon. Hence, manufacturing test needs have high fault coverage. Obtaining high fault coverage different issue than demonstrating that design functions properly. some cases simulation patterns provide adequate fault coverage, will simply convert them into test program. case customer-developed simulation patterns, these vectors augmented with ATPG-produced vectors. other cases, recommends that internal scan path inserted into design. AMI's NETSCANsoftware tools perform this entire task fully automated fashion.
Automatic Test Program Generation Most Automatic Test Program Generation (ATPG) programs available today limited their ability handle complex asynchronous circuits. Typical applications ATPG include pure combinational logic, used with scan testing sequential logic, provided design fully synchronous. Asynchronous circuits difficult because they require accurate delay modeling require long, compute-intensive ATPG runs. developed ATPG approach that accurately handles asynchronous circuits with reasonable times achieves high fault coverage most circuits. Internal Scan Path Test Support offers automatic scan path insertion ATPG service with NETSCAN. NETSCAN creates tests with fault coverage typically range. Adding internal scan path typically adds 15-25% gate count your design easiest most reliable obtain high-fault coverage manufacturing test. pad-limited conversions there area increase. Most scan path software expects work with fully synchronous designs. Since many designs asynchronous, NETSCAN designed handle them. This unique feature allows support asynchronous synchronous circuits with equal facility. JTAG Test Support AMI's NETTAGsoftware automatically inserts JTAG-compatible (IEEE 1149) boundary scan into your design, ensuring compatibility with growing popularity JTAG board-level test methodology. also offer option controlling NETSCAN-inserted scan path from JTAG Test Access Port (TAP).
DESIGN CONVERSION
FPGASICSM Design Techniques Seminar
Quickturn prototyping logic critical system development meeting critical market demands. FPGAs provide flexible solution develop product and, hence, system quickly. When considering production, lower cost ASIC solutions necessary provide competitive product marketplace. Anticipating designing migration portability pivotal factor smooth successful conversions. example: Were FPGA-specific structures avoided? Were packaging board layout issues brought into consideration? other words, FPGA designed portability? Knowing design portability distilled from experience. And, we've learned tricks along way. Plan conversion early stages product development, looking pinouts, board layout, other creative ways anticipate conversion process. thorough prototype testing with FPGA ensure design will work expected when converted ASIC. Reduce timing issues avoiding asynchronous designs. Develop simulation data files verify conversion, plus much more. AMI's FPGASIC Design Techniques Seminar created engineers anyone interested learning about FPGA-to-ASIC conversion issues targeted technical people, such designers engineering management. seminar includes introduction NETRANS, session designing FPGAs migration portability ASICs, segment ASIC implementation. NETRANS Introduction discusses NETRANS' capabilities, including software tools convert over FPGA/ASIC formats. This session covers technology, manufacturing processes, methodology, field support available. Design Portability discusses, great technical detail, design anticipate conversion. addresses issues documentation, synchronous design techniques, core usage, test bench development, considerations. ASIC Implementation discusses migration strategies. This segment covers board system-level simulations functional timing verification. also addresses design testability, vectorless conversions, FPGA-specific issues, working with ASIC vendor. find more about FPGASIC Seminar, visit AMI's page
designe enginee enginee Presente
Half-D Design Techniq Seminar
ASIC SERVICES
ASIC Design Methodology ASIC Design Tools
addition AMI's NETRANS service, also supports ASIC design kits industry-leading tools. Design kits include cell libraries ACCESS Design Tools, which include AMI's Delay Calculator, Design Checker, Static Timing Analysis, generation tools. Combined with highly accurate equation-based timing models clock tree synthesis, AMI's design kits provide tight coupling ASIC processes.
ASIC Std. Library Megacell Memory Block supported Synthesis Tool
Design Specification
Customer Design Activity
Synthesis/ Schematic Capture Logic/Timing Simulation Fault Simulation
ASIC families supported popular third party products: Synopsys® Viewlogic® Mentor Graphics® Cadence®
Netlist Transfer
Test Vectors
Intergraph® Verilog® sign-off simulation VHDL Vital sign-off simulation
Simulation Verification Place Route
Design Responsibility
Back Annotation Customer
IKOS® simulation hardware accelerator back annotation
foregoing names constitute protected trade names, trademarks and/or service marks their respective owners.
Layout Parameter Extraction Post Layout Simulation Physical Design Verification
Customer Approval
Final Review Mask Creation, Fabrication Test
ASIC PRODUCTS
AMI's ASIC Features
AMI's gate array families exploit proprietary power grid track routing architecture compact, channelless, sea-of-gates design provide highest performance, most cost-effective array products available today. Gate counts 5.9M useable gates (standard cell) Gate counts 2.0M useable gates (gate array) Embedded 1.5M dual port bits gate array 2.5V, 3.3V, operation: 2.5V core with 2.5V, 3.3V, tolerant I/O. 3.3V core with 3.3V, tolerant, I/O. core with I/O. voltage banking. Operating Temp range -55° 125°C: competing products allow this range. Excellent performance: 990MHz maximum toggle rate clocked flip-flops (Tj=135°C). little 65ps delay (FO=2; L=0mm) 2-input NAND gate. clock management circuits: Minimize clock insertion delay, deskew board level clock, synthesize clock frequencies. Clock tree synthesis: Clock drivers placed minimize clock skew latency effects circuit performance. Parameterized clock buffers model clock trees before layout. matches simulation parameters pre-layout models with physical clock tree during layout. 24mA drive single cell (3.3V, 18mA drive single cell (2.5V): Selectable drive with controllable slew rate. Extensive library quick design: Complete primary cell library. Transceivers: 33/66MHz, USB, LVPECL, LVDS, others. Embedded configurable dual-port RAM. Synchronous single port compilers. Megacells USB, PCI, 10/100 Ethernet MAC, others. Full operating voltage range from 2.25V 5.5V protection 2KV; latchup 100mA Power 0.57µW/MHz/gate (FO=1, VDD=3.3V)
XLArray Family (0.5 Micron, XL5H-5.0V, XL5L-3.3V) Base Array
XL5H/L72 XL5H/L104 XL5H/L148 XL5H/L164 XL5H/L212 XL5H/L260 XL5H/L324 XL5H/L392 XL5H/L460 XL5H/L456 XL5H/L532 XL5H/L600 XL5H/L664 XL5H/L728 XL5H/L792
Useable Gates 2L4,620 9,680 19,600 24,000 40,000 60,000 93,000 135,000 190,000 330,000 450,000 570,000 700,000 840,000 995,000
3L8,300 7,400 35,300 43,200 72,000 109,000 168,000 250,000 300,000 525,000 720,000 855,000 1,050,000 1,265,000 1,500,000
Avail. Bond Pads
XLArray Family (0.35 Micron, XL3H-3.3V, XL3L-2.5V)
Preliminary Information
Base Array
XL3H/L52G XL3H/L1 XL3H/L164 XL3H/L232G XL3H/L232 XL3H/L316 XL3H/L368G XL3H/L368 XL3H/L452 XL3H/L568 XL3H/L716 XL3H/L768G XL3H/L768 XL3H/L868 XL3H/L952 XL3H/L1072 XL3H/L1216
Useable Gates
9,900 9,320 35,600 158,000 63,000 16,000 388,000 139,000 215,000 375,000 478,000 1,650,000 623,000 479,000 619,000 2,050,000 702,000
Embedded Dual-Port Bits
8,192 16,384 36,864 65,536 102,400 147,456 229,376 409,600 450,560 745,472 860,160 524,288 1,548,288
Avail. Bond Pads
1,072 1,216
PACKAGING
Packaging Options
offers comprehensive line packaging meet your requirements. more commonly used packages listed below. AMI's packaging equivalent Xilinx MQ/HQFP Altera RQFP. However, these thermally enhanced packages usually required ASIC reduced power dissipation.
Gate Array Family (0.5 Micron) Packaging Options Array
XL5H/L72 XL5H/L104 XL5H/L148 XL5H/L164 XL5H/L212 XL5H/L260 XL5H/L324 XL5H/L392 XL5H/L460 XL5H/L456
PQFP
44,52,64,80,100 44,52,64,80,100,160 44,52,64,80,100,128,144,160 44,52,64,80,100,128,1 44,1 44,52,64,80,100,120,128,1 44,1 60,208 44,52,64,80,100,120,128,1 44,1 60,208 44,52,64,80,100,120,128,1 44,1 60,208,240 52,64,80,100,120,128,1 44,1 60,208,240 80,100,120,128,1 44,1 60,208,240,256 128,144,1 60,208,240,256,304
TQFP
32,44,48,64,80,100 32,44,48,64,80,100 32,44,48,64,80,100,128,176 32,44,48,64,80,100,128,144, 44,64,80,100,128,144,176 44,64,80,100,128,144,176,208 44,64,80,100,128,144,176,208 44,100,128,144,176,208 100,128,144,176,208 128,176
Array
XL5H/L72 XL5H/L104 XL5H/L148 XL5H/L164 XL5H/L212 XL5H/L260 XL5H/L324 XL5H/L392 XL5H/L460 XL5H/L456
PLCC
20,28,32,44,68 20,28,32,44,68 20,28,32,44,52,68,84 20,28,32,44,52,68,84 28,32,44,52,68,84 28,32,44,52,68,84 32,44,52,68,84 44,52,68,84 44,52,68
121,169 121,169 121,169 121,169,225,256 169,225,256 169,225,256 225,256,313,352,388 225,256,313,352,388
AMI's complete package availability, please request Packaging Capabilities folder.
Gate Array Family (0.35 Micron) Packaging Options Array
XL3H/L52 XL3H/L116 XL3H/L164 XL3H/L232 XL3H/L316 XL3H/L368 XL3H/L452 XL3H/L568 XL3H/L716 XL3H/L768 XL3H/L868 XL3H/L952 XL3H/L1072 XL3H/L1216 TQFP44, PQFP44 PQFP80, PLCC84, VQFP100, PQFP100 TQFP80, VQFP100, PQFP160 VQFP100, TQFP144, PQFP208, BGA256 TQFP144, PQFP208, PQFP240, BGA256 TQFP144, PQFP208, PQFP240, BGA352 PQFP208, PQFP240, BGA432 PQFP240, BGA432 PQFP240 BGA560 BGA560 BGA560
AMI's Facilities
Corporate headquarters AMI's ASIC design manufacturing operations located 492,000 square foot facility Pocatello, Idaho. ceramic prototyping performed here, including layout, fabrication, sorting, assembly, testing. maintains global presence with sales offices, technical service centers, design centers located throughout U.S. world. This includes Worldwide Headquarters Diego, California, software facility Twain Harte, California, sort test facility Manila, Philippines.
AMI's Class-1, state-of-the-art wafer facility, capable supporting geometries down 0.25µ.
SALES OFFICES
Corporate Offices
California
WORLDWIDE HEADQUARTERS 16644 Bernardo Drive, Ste. Diego, 92127 858.385.1808 858.385.1809 (FAX)
Japan-1,3
AMI-JAPAN Floor, Otsuka Bldg., 13-17, 1-chome, Kitaotsuka Toshima-ku, Tokyo, Japan +81.3.5961.7861 +81.3.5961.7860 (FAX)
Colorado-2,3
North Carolina-2
6640 Gunpark Drive, Ste. Boulder, 80301 303.581.4141 303.581.9121 (FAX)
1130 Kildaire Farm Road Cary, 27511 919.465.0188 919.465.0187 (FAX)
Idaho-4
Philippines-1
Idaho
CORPORATE HEADQUARTERS 2300 Buckskin Pocatello, 83201 208.233.4690 208.234.6796 (FAX)
9701 Santos Ave. Paranaque, Metro Manila Philippines +632.825.6011 +632.844.1331 (FAX)
Avenue Pocatello, 83201 208.234.9898 208.234.9693 (FAX) Sweet Avenue Moscow, 83843 208.885.3800 208.885.3803 (FAX)
Oregon-4
8215 Tualatin Sherwood Rd., Ste. Portland, 97062 503.691.7030 503.691.7031 (FAX)
Pennsylvania-5
United Kingdom-2
Japan
JAPAN ENERGY CORPORATION 10-1 Toranomon 2-Chome Minato-ku Tokyo Japan +81.3.5573.6543 +81.3.5573.6777 (FAX)
Suite Sandhurst House Yorktown Road, Sandhurst Surrey, GU47 United Kingdom +44.1276.600680 +44.1276.600681 (FAX)
Illinois-2
1250 Northwest Highway, Ste. Palatine, 60067 847.776.4500 847.776.5067 (FAX)
Timing Generator Products Bethlehem Pike Gwynedd Office Park, Ste. Lower Gwynedd, 19002-2659 215.654.9700 215.654.9791 (FAX)
Texas-2
NORTH AMERICAN INTERNATIONAL OFFICES OFFICES Arizona-6
Finland-1
Lonnrotinkatu 22A19a FIN-00120 Helsinki Finland +358.9.694.3425 +358.9.694.3425 (FAX)
Indiana-3
Airport North Office Park Fort Wayne, 46825 219.490.1107 219.490.0119 (FAX)
5068 Plano Parkway, Ste. Plano, 75093 972.248.7770 972.248.2681 (FAX)
Utah-4
Massachusetts-2,3
Andover Tech Center Tech Drive Andover, 01810 978.989.9999 978.989.9980 (FAX)
11811 Tatum Blvd., Ste. 3031 Phoenix, 85028 602.953.6655 602.953.6656 (FAX)
East South, Ste. American Fork, 84003 801.763.5436 801.763.0781 (FAX)
California, North-2,3
1731 Technology Drive, Ste. Jose, 95110 408.452.8550 408.452.7602 (FAX)
Minnesota-2
Germany-2,5
GmbH Bertolt-Brecht-Allee D-01309 Dresden Germany +49.351.31.530.23 +49.351.31.530.21 (FAX)
California, South-2,3
13891 Newport Avenue, Ste. Tustin, 92780 714.573.8199 714.573.8190 (FAX)
Corporate Center 7300 Metro Boulevard, Ste. Edina, 55439 612.893.1214 612.893.0888 (FAX)
Jersey-2
Italy-1
Suno I-28010 Agrate Conturbia (NO), Italy +39.0322.832307 +39.0322.832307 (FAX)
Summit Avenue, Bldg. Montvale, 07645 201.930.1350 201.930.9820 (FAX)
Sales Personnel Sales Application Engineering Personnel Technical Services Center Application Engineering Personnel Only Business Unit Headquarter
Copyright©2000 American Microsystems, Inc.
Please visit site www.amis.com most current information available.
Devices sold covered warranty patent indemnification provisions appearing Terms Sale only. makes warranty, express, statutory implied description, regarding information forth herein regarding freedom described devices from patent infringement. makes warranty merchantability fitness purposes. reserves right discontinue production change specifications prices time without notice. AMI's products intended commercial applications. Applications requiring extended temperature range, unusual environmental requirements, high reliability applications, such military, medical life-support life-sustaining equipment, specifically recommended without additional processing such applications.
American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, 83201, (208) 233-4690, (208) 234-6796
Printed Recycled Paper
NETRANSBRO GA00011(5K)CX3/00
American Microsystems, Inc. 2300 Buckskin Road Pocatello, 83201 Telephone: (208) 233-4690 FAX: (208) 234-6795 http://www.amis.com

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